π/4-DQPSK调制解调关键技术研究及FPGA实现
摘要
近年来,随着数字信号处理技术不断成熟,各种数字处理器件性能不断完善,以现代通信理论为基础,以数字信号处理为核心,以微电子技术为支撑的软件无线电技术或称软件可定义无线电技术应运而生。它的基本概念是把硬件作为无线通信的基本平台,而把尽可能多的无线通信及个人通信功能用软件实现。无线通信系统、新产品的开发将逐步转到软件上来,而无线通信的产品价值将越来越多地体现在软件上。这是无线通信领域继固定到移动、模拟到数字之后的第三次革命,对末来通信事业的发展将产生深远的影响。
本课题的任务是用可编程逻辑门阵列(Field Programmable Gate Array,简称FPGA)实现基带到中频的全数字π/4-DQPSK调制解调系统。π/4-DQPSK是一种线性窄带数字相位调制技术,因其频谱利用率高,频谱特性好,抗多径性能强等突出特点,在移动通信、卫星通信中得到广泛应用。
本文首先研究π/4-DQPSK调制解调系统中调制部分的基本原理和各个模块的设计方案,重点研究成形滤波器和直接数字频率合成器(Direct Digital FrequencySynthesis,简称DDS),并针对各个关键模块算法进行matlab设计仿真,展示仿真结果。其次,研究调制解调系统解调部分的基本原理和各个模块的设计方案,重点研究差分解调,数字下变频和位同步算法,也针对其各个关键模块进行算法的Matlab设计仿真。然后用Matlab对整个系统进行理论仿真,得出结论。在此基础上,采用超高速集成电路硬件描述语言(Very High Speed Integrated Circuit HardwareDescription Language,简称VHDL)在Altera公司QuartusⅡ7.0开发环境下设计并实现各个功能块,通过仿真来证明功能正确性。再次,用Protel 99SE进行印制电路板(print circuit board,简称PCB)设计,从原理图到封装,再到布局布线。焊接调试完毕后,将设计好的程序下载至FPGA主芯片。最后观察信号时域波形、星座图、眼图。本系统信源输入符号速率100kbps,调制中频10MHz。测试结果验证系统的正确性,实现了从数字基带到中频的π/4-DQPSK调制解调系统。
In recent years,software defined radio emerges as the times require along with the technique of digital signal processing growing up and the performance of digital processing instrument being consummate.It's based on the principles of modern communication with digital signal processing for core,and supported by the technique of micro-electronics.Its basic concept is making hardware as the platform,realizing the function of wireless communication system and personal communication system by software as much as possible.Software defined radio is called the third revolution in wireless communication field following digital communication and mobile communication,and it will influence the future deeply.
The task of topic is realizingπ/4-DQPSK modulation and demodulation system from baseband to intermediate frequency by FPGA.π/4-DQPSK modulation is a linear narrowband technology,which possesses features of high spectrum utilization ratio, better spectrum speciality and stronger anti-fading performance.The modem method has been applied widely in mobile communication system,satellite communication system because of its excellences.
Firstly,This thesis studies basic principle ofπ/4-DQPSK modulation part in modem system and makes solution to each module,emphasizes pulse shaping filter and DDS,emulates each key module in Matlab and presents the results.Secondly,the research studies basic principle ofπ/4-DQPSK demodulation part in modem system and makes solution to each module,emphasizes differential detection,DDC and bit synchronization,emulates each key module in Matlab and presents the results also.The next step is using Matlab to emulate the whole system and get the result.On this foundation,each module will be designed by VHDL(Very High Speed Integrated Circuit Hardware Description Language) in QuartusⅡ7.0 of Altera,and the accuracy of function will be proved through the emulation result.Next,design PCB from schematic Document to encapsulation,then to layout in Protel 99 SE.When finishing jointing, download the designed procedure to FPGA main chip.Finally,observing signal waveform,constellation diagram and eye diagram in oscillograph.This system signal source rate 100 kbps,modulated intermediate frequency 10 MHz.The accuracy of the system will be proved by test result.Theπ/4-DQPSK modulation and demodulation system from baseband to intermediate frequency has been realized.
本课题的任务是用可编程逻辑门阵列(Field Programmable Gate Array,简称FPGA)实现基带到中频的全数字π/4-DQPSK调制解调系统。π/4-DQPSK是一种线性窄带数字相位调制技术,因其频谱利用率高,频谱特性好,抗多径性能强等突出特点,在移动通信、卫星通信中得到广泛应用。
本文首先研究π/4-DQPSK调制解调系统中调制部分的基本原理和各个模块的设计方案,重点研究成形滤波器和直接数字频率合成器(Direct Digital FrequencySynthesis,简称DDS),并针对各个关键模块算法进行matlab设计仿真,展示仿真结果。其次,研究调制解调系统解调部分的基本原理和各个模块的设计方案,重点研究差分解调,数字下变频和位同步算法,也针对其各个关键模块进行算法的Matlab设计仿真。然后用Matlab对整个系统进行理论仿真,得出结论。在此基础上,采用超高速集成电路硬件描述语言(Very High Speed Integrated Circuit HardwareDescription Language,简称VHDL)在Altera公司QuartusⅡ7.0开发环境下设计并实现各个功能块,通过仿真来证明功能正确性。再次,用Protel 99SE进行印制电路板(print circuit board,简称PCB)设计,从原理图到封装,再到布局布线。焊接调试完毕后,将设计好的程序下载至FPGA主芯片。最后观察信号时域波形、星座图、眼图。本系统信源输入符号速率100kbps,调制中频10MHz。测试结果验证系统的正确性,实现了从数字基带到中频的π/4-DQPSK调制解调系统。
In recent years,software defined radio emerges as the times require along with the technique of digital signal processing growing up and the performance of digital processing instrument being consummate.It's based on the principles of modern communication with digital signal processing for core,and supported by the technique of micro-electronics.Its basic concept is making hardware as the platform,realizing the function of wireless communication system and personal communication system by software as much as possible.Software defined radio is called the third revolution in wireless communication field following digital communication and mobile communication,and it will influence the future deeply.
The task of topic is realizingπ/4-DQPSK modulation and demodulation system from baseband to intermediate frequency by FPGA.π/4-DQPSK modulation is a linear narrowband technology,which possesses features of high spectrum utilization ratio, better spectrum speciality and stronger anti-fading performance.The modem method has been applied widely in mobile communication system,satellite communication system because of its excellences.
Firstly,This thesis studies basic principle ofπ/4-DQPSK modulation part in modem system and makes solution to each module,emphasizes pulse shaping filter and DDS,emulates each key module in Matlab and presents the results.Secondly,the research studies basic principle ofπ/4-DQPSK demodulation part in modem system and makes solution to each module,emphasizes differential detection,DDC and bit synchronization,emulates each key module in Matlab and presents the results also.The next step is using Matlab to emulate the whole system and get the result.On this foundation,each module will be designed by VHDL(Very High Speed Integrated Circuit Hardware Description Language) in QuartusⅡ7.0 of Altera,and the accuracy of function will be proved through the emulation result.Next,design PCB from schematic Document to encapsulation,then to layout in Protel 99 SE.When finishing jointing, download the designed procedure to FPGA main chip.Finally,observing signal waveform,constellation diagram and eye diagram in oscillograph.This system signal source rate 100 kbps,modulated intermediate frequency 10 MHz.The accuracy of the system will be proved by test result.Theπ/4-DQPSK modulation and demodulation system from baseband to intermediate frequency has been realized.
引文
[1]Chang jiang,zhang naitong.A new signal processing technique of π/4DQPSK modern based on software radio[J].Journal of systems engineering and electronics,2003,vol.14,no.2,pp.20-24.
[2]杨小牛,楼才义,徐建良.软件无线电原理与应用[M].电子工业出版社,2001.
[3]谢红,刘艳艳.π/4DQPSK渊制与解调住SystemView中的仿真实现[J].应用科技,2005,Vol.32,no.8.
[4]F.M.Gardner,Carrier and clock synchronization for TDMA[J].digital communications,Euro.Space Agency,Dec.1976.Noordwijk,the Netherlands,Rep.ESA TM-169(ESTEC).
[5]C.S.Ng,T.T.Thiang,F.Adachi,K.M.Lye.On the Error Rate of Differentially Detected Narrowband π/4DQPSK in Rayleigh Fading and Gaussian Noise[J].IEEE Transactions on Vehicular Technology,1993,vol.42,no.3,pp.259-265.
[6]F.Adachi,K.Ohno,and M.Ikura,Postdetection selection diversity reception with correlated,unequal average power Rayleigh fading signals for π/4-DQPSK mobile radio[J],IEEE Trans.Veh.Technol,vol.41,pp.199-209,May 1992.
[7]P.Y.Kam,Bit error probabilities of MDPSK over the nonselective Rayleigh fading channel with diversity reception[J],IEEE Trans.Commun.,Feb.1991,vol.39,pp.220-224.
[8]K.Feher,moderns for Emerging Digital Cellular-Mobile Radio system[J],IEEE Transactions on Vehicular Technology,May 1991,vol.40,no.2,pp.355-365.
[9]苏仁宏,杨士中.移动通信中的π/4-DQPSK调制解调技术及DSP实现[J].电讯技术.1998年第38卷第4期.pp.24-29..
[10]王诚,吴继华,范丽珍.Altera FPGA/CPLD设计(基础篇)[M].人民邮电出版社,2005.
[11]廖红舒.π/4-DQPSK调制解调算法设计及DSP实现[D].成都:电子科技大学,2004.
[12]彭飞,赵继勇.基于FPGA的全数字低中频QPSK调制解调器实现[J].电子设计应用,2003,2(9):21-23.
[13]王永和,卜长彷.采用FPGA实现π/4DQPSK调制器[J].北方交通大学学报(自然科学版),2000,24(5):53-57.
[14]赵杭生,甘仲民,屈德新.π/4-DQPSK调制的快速何同步捕获和位同步跟踪[J].电子学报,1999,4(27).
[15]廖长清,卢建川,曾利.基于TMS320C54x实现〗/4-DQPSK调制[J].电讯技术.2002年第1期.pp.1-4.
[16]U.Mengali,A self bit synchronizer matched to the signal shape[J],IEEE Trans.Aerosp. Electron.Syst.,July 1971.vol.AES-7,pp.686-693.
[17]樊平毅,冯重熙.窗函数住成形滤波器设计中的应用[J].通信学报,1996年3月,第17卷第2期.
[18]樊平毅,冯重熙.几种成形滤波器的抗时钟抖动性能的比较[J].通信学报,1996年1月,第17卷第1期.
[19]王建新,蒋立平,吉训生,陈小梅.基带成形滤波器的FPGA实现[J].电讯技术,2001年第5期.
[20]魏祸立.直接数字频率合成技术的应用[J].电子技术应用,1993年第5期.
[21]崔文.基于FPGA的数字上下变频器的研究与实现[D].西安电子科技大学,2006年.
[22]罗正岳.基于FPGA的直扩凋制解调器的设计与实现[D].重庆大学,2007年.
[23]Walther J S.A unied algorithm for elementary functions[J].AFIPS Spring Joint Computer Conference,1971,38:379-385.
[24]Leonard E.Miller,Jhong S.Lee.Bet expressions for differentially detected π/4DQPSK modulation[J].IEEE transactions on communications,1998,vol.46,no.1.
[25]S.H.Goode,H.L.Kazecki and D.W.Dennis.A comparison of a limiter-discriminator,delay and coherentdetection for π/4 QPSK[J].IEEE Vehicular Technology Conference,Orlando,1990,pp.687-694.
[26]L.E.Miller,and J.S.Lee,New Closed-Form BER Expressions for Differentially Detected π/4-DQPSK[J],IEEE International Symposium on Information Theory,1994,Trond-heim,Norway.
[27]S.Chennakeshu and G.J.Saulnier,Differential detection of π/4-DQPSK for digital cellular radio[J],IEEE Trans.Veh.Technol,Feb.1993,vol.42,pp.46-57.
[28]蒋娜,钟洪卢.π/4-DQPSK调制解调硬件实现中的误码率分析[J].电子工程师,2004年12月,第30卷第12期.
[29]李鸣,颜彪,周平,杨娟.基于希尔伯特变换的数字下变频器[J].淮阴师范学院学报(自然科学版).2005年5月,第4卷第2期.
[30]张贤达,保铮.通信信号处理[M].国防工业出版社.2000年.
[31]柯炜,殷奎喜.平滑相位的π/4DQPSK调制及其在移动通信系统中应用[J].电讯技术,2003,43(1):88-91.
[32]曹志刚,钱亚生.现代通信原理[M].清华大学出版社,1992.
[33]K.H.Mueller and M.Muller,Timing recovery in digital synchronous data receivers[J],IEEE Trans.Commun.,May 1976,vol..COM-14,pp.516-530.
[34]M.Moeneclaey,Comment on Tracking performance of the filter and square bit synchronizer [J],IEEE Trans.Commun.,Feb.1982vol.COM-30,pp.407-410.
[35]C.P.J.Tzeng,D.A.Hodges,and D.G.Messerschmitt,Timing recovery in digital subscriber loops using baudrate sampling[J],in Conf.Rec.Int.Conf.Cornmun.,1985,vol.3,pp.37.
[36]O.Agazzi,C.-P.J.Tzeng,D.G.Messerschmitt,and D.A.Hodges,Timing recovery in digital subscriber loops[J],IEEE Trans.Commun.,June 1985.vol.COM-33,pp.558-569.
[37]L.E.Franks,Carrier and bit synchronization in data communication[J],IEEE Trans.Commun.,Aug.1980.vol.COM-28,pp.1107-1120.
[38]Floy M.Gardner.A BPSK/QPSK timing error detector for sampled receivers[J].IEEE Trans.on Communications,1986,COM-34(5):423-429.
[39]I.S.Xezonakis,M.S.Sangriotis.Algorithm for the construction of an all digital early-late BPSK/QPSK symbol synchronizer[J].INT.J.Electronics,1991,70(1):1-10.
[40]Marvin K.,Dariush Divsalar.Doppler corrected differential detection of MPSK[J].IEEE transactions on Communications.1989,37(2):99-109.
[41]N.A.DAndrea and U.Mengali,A simulation study of clock recovery in QPSK and 9QPRS systems[J],IEEE Trans.Commun.,Oct.1985 vol.COM-33,pp.1139-1142.
[42]刑建平,曾繁泰.VHDL程序设计教程(第3版)[M].清华大学出版社,2005.
[2]杨小牛,楼才义,徐建良.软件无线电原理与应用[M].电子工业出版社,2001.
[3]谢红,刘艳艳.π/4DQPSK渊制与解调住SystemView中的仿真实现[J].应用科技,2005,Vol.32,no.8.
[4]F.M.Gardner,Carrier and clock synchronization for TDMA[J].digital communications,Euro.Space Agency,Dec.1976.Noordwijk,the Netherlands,Rep.ESA TM-169(ESTEC).
[5]C.S.Ng,T.T.Thiang,F.Adachi,K.M.Lye.On the Error Rate of Differentially Detected Narrowband π/4DQPSK in Rayleigh Fading and Gaussian Noise[J].IEEE Transactions on Vehicular Technology,1993,vol.42,no.3,pp.259-265.
[6]F.Adachi,K.Ohno,and M.Ikura,Postdetection selection diversity reception with correlated,unequal average power Rayleigh fading signals for π/4-DQPSK mobile radio[J],IEEE Trans.Veh.Technol,vol.41,pp.199-209,May 1992.
[7]P.Y.Kam,Bit error probabilities of MDPSK over the nonselective Rayleigh fading channel with diversity reception[J],IEEE Trans.Commun.,Feb.1991,vol.39,pp.220-224.
[8]K.Feher,moderns for Emerging Digital Cellular-Mobile Radio system[J],IEEE Transactions on Vehicular Technology,May 1991,vol.40,no.2,pp.355-365.
[9]苏仁宏,杨士中.移动通信中的π/4-DQPSK调制解调技术及DSP实现[J].电讯技术.1998年第38卷第4期.pp.24-29..
[10]王诚,吴继华,范丽珍.Altera FPGA/CPLD设计(基础篇)[M].人民邮电出版社,2005.
[11]廖红舒.π/4-DQPSK调制解调算法设计及DSP实现[D].成都:电子科技大学,2004.
[12]彭飞,赵继勇.基于FPGA的全数字低中频QPSK调制解调器实现[J].电子设计应用,2003,2(9):21-23.
[13]王永和,卜长彷.采用FPGA实现π/4DQPSK调制器[J].北方交通大学学报(自然科学版),2000,24(5):53-57.
[14]赵杭生,甘仲民,屈德新.π/4-DQPSK调制的快速何同步捕获和位同步跟踪[J].电子学报,1999,4(27).
[15]廖长清,卢建川,曾利.基于TMS320C54x实现〗/4-DQPSK调制[J].电讯技术.2002年第1期.pp.1-4.
[16]U.Mengali,A self bit synchronizer matched to the signal shape[J],IEEE Trans.Aerosp. Electron.Syst.,July 1971.vol.AES-7,pp.686-693.
[17]樊平毅,冯重熙.窗函数住成形滤波器设计中的应用[J].通信学报,1996年3月,第17卷第2期.
[18]樊平毅,冯重熙.几种成形滤波器的抗时钟抖动性能的比较[J].通信学报,1996年1月,第17卷第1期.
[19]王建新,蒋立平,吉训生,陈小梅.基带成形滤波器的FPGA实现[J].电讯技术,2001年第5期.
[20]魏祸立.直接数字频率合成技术的应用[J].电子技术应用,1993年第5期.
[21]崔文.基于FPGA的数字上下变频器的研究与实现[D].西安电子科技大学,2006年.
[22]罗正岳.基于FPGA的直扩凋制解调器的设计与实现[D].重庆大学,2007年.
[23]Walther J S.A unied algorithm for elementary functions[J].AFIPS Spring Joint Computer Conference,1971,38:379-385.
[24]Leonard E.Miller,Jhong S.Lee.Bet expressions for differentially detected π/4DQPSK modulation[J].IEEE transactions on communications,1998,vol.46,no.1.
[25]S.H.Goode,H.L.Kazecki and D.W.Dennis.A comparison of a limiter-discriminator,delay and coherentdetection for π/4 QPSK[J].IEEE Vehicular Technology Conference,Orlando,1990,pp.687-694.
[26]L.E.Miller,and J.S.Lee,New Closed-Form BER Expressions for Differentially Detected π/4-DQPSK[J],IEEE International Symposium on Information Theory,1994,Trond-heim,Norway.
[27]S.Chennakeshu and G.J.Saulnier,Differential detection of π/4-DQPSK for digital cellular radio[J],IEEE Trans.Veh.Technol,Feb.1993,vol.42,pp.46-57.
[28]蒋娜,钟洪卢.π/4-DQPSK调制解调硬件实现中的误码率分析[J].电子工程师,2004年12月,第30卷第12期.
[29]李鸣,颜彪,周平,杨娟.基于希尔伯特变换的数字下变频器[J].淮阴师范学院学报(自然科学版).2005年5月,第4卷第2期.
[30]张贤达,保铮.通信信号处理[M].国防工业出版社.2000年.
[31]柯炜,殷奎喜.平滑相位的π/4DQPSK调制及其在移动通信系统中应用[J].电讯技术,2003,43(1):88-91.
[32]曹志刚,钱亚生.现代通信原理[M].清华大学出版社,1992.
[33]K.H.Mueller and M.Muller,Timing recovery in digital synchronous data receivers[J],IEEE Trans.Commun.,May 1976,vol..COM-14,pp.516-530.
[34]M.Moeneclaey,Comment on Tracking performance of the filter and square bit synchronizer [J],IEEE Trans.Commun.,Feb.1982vol.COM-30,pp.407-410.
[35]C.P.J.Tzeng,D.A.Hodges,and D.G.Messerschmitt,Timing recovery in digital subscriber loops using baudrate sampling[J],in Conf.Rec.Int.Conf.Cornmun.,1985,vol.3,pp.37.
[36]O.Agazzi,C.-P.J.Tzeng,D.G.Messerschmitt,and D.A.Hodges,Timing recovery in digital subscriber loops[J],IEEE Trans.Commun.,June 1985.vol.COM-33,pp.558-569.
[37]L.E.Franks,Carrier and bit synchronization in data communication[J],IEEE Trans.Commun.,Aug.1980.vol.COM-28,pp.1107-1120.
[38]Floy M.Gardner.A BPSK/QPSK timing error detector for sampled receivers[J].IEEE Trans.on Communications,1986,COM-34(5):423-429.
[39]I.S.Xezonakis,M.S.Sangriotis.Algorithm for the construction of an all digital early-late BPSK/QPSK symbol synchronizer[J].INT.J.Electronics,1991,70(1):1-10.
[40]Marvin K.,Dariush Divsalar.Doppler corrected differential detection of MPSK[J].IEEE transactions on Communications.1989,37(2):99-109.
[41]N.A.DAndrea and U.Mengali,A simulation study of clock recovery in QPSK and 9QPRS systems[J],IEEE Trans.Commun.,Oct.1985 vol.COM-33,pp.1139-1142.
[42]刑建平,曾繁泰.VHDL程序设计教程(第3版)[M].清华大学出版社,2005.