基于高速LVDS的串并转换电路设计与研究
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摘要
随着信息技术的发展,数据量越来越大,传统的I/O接口由于自身的限制越来越不能满足现实需求。低压差分信号传输技术(Low Voltage Differential Signaling,LVDS)具有低噪声、低功耗、高可靠、节省成本和强集成能力等优点,因此成为了解决I/O接口问题的一种新技术。
本文基于ANSI/TIA/EIA-644标准,研究了基于高速LVDS的串并转换电路。在此基础上,根据功能将其分为LVDS接收电路和串并转换电路两个主要模块。在LVDS接收电路中,通过ESD保护电路、轨对轨放大电路、迟滞比较电路、整形缓冲电路和失效保护电路的设计,完成了将2.5Gbps的LVDS信号转化为CMOS信号的工作。仿真结果表明,整个LVDS接收电路的延时为0.45ns,上升时间为0.04ns,下降时间为0.03ns,占空比为37:36,满足设计要求。
在串并转换电路中,为了满足高速和低时钟的要求,采用一种树型结构和移位寄存器结构级联的串并转换电路。通过占空比为1:4的5分频器、树型结构串并转换电路和移位寄存器结构串并转换电路的设计,将1路2.5Gbps的数据转化为10路250Mbps的数据。仿真结果表明,整个串并转换电路的功能正确,满足设计要求。
此外,本文在版图方面进行了研究,对匹配、串扰、噪声、寄生效应、闩锁效应和天线效应分别进行了论述,给出相应的解决办法。并基于1P8M 0.13μm CMOS工艺,采用全定制完成了版图设计。LVDS接收电路版图面积为74×96 ? m2,满足I/O标准;串并转换电路版图面积为80×83 ? m2。后仿真结果表明,本文设计的串并转换电路满足要求。
With the development of information technology, the amount of data transmission is more and more increasing. Due to its limitations, the traditional I/O interfaces can not meet people's needs. Low Voltage Differential Signal Transmission Technology has low noise, low power, high reliability, saving cost and strong integration capability. So it becomes a new technology to the solution of I/O interface.
This paper which studies the deserializer based on high speed LVDS is under ANSI/TIA/EIA-644. On this basis, according to the function, it can be parted two main modules—the receive circuit of the LVDS and deserializer.
In LVDS receiver circuit, the ESD protection circuit, rail to rail amplifier, comparator circuit, shaping-buffer circuits and fail-safe circuits transform 2.5Gbps of LVDS signals into CMOS signals. Through Simulation, the LVDS receiver circuit delay 0.45ns. The rise time is 0.04ns, and the fall time is 0.03ns ,Duty cycle is 37:36. It meets the design requirements.
In deserializer, in order to meet the requirements of high speed and low clock requirements, it is wonderful to use a tree structure deserializer and register structure deserializers. Through the duty cycle of 1:4 divider(divide-by-5), tree structure deserializer and register structure deserializer, it completed down to a 2.5Gbps data into the data of 10 road 250Mbps. Through simulation, it has the correct function and it is enough to meet the design requirements.
Besides, layout is researched in-depth. Discussing the matching, crosstalk, noise, parasitic effects, the latch and antenna effect, I give appropriate solutions. The design based on 1P8M 0.13μm CMOS process is completed using full-custom layout method. Layout of the LVDS receiver circuit is 74×96 ? m2 and it meets the standard of I/O. Layout of the deserializer is 80×83 ? m2. Post-simulation shows that the deserializer meets the design requirements.
本文基于ANSI/TIA/EIA-644标准,研究了基于高速LVDS的串并转换电路。在此基础上,根据功能将其分为LVDS接收电路和串并转换电路两个主要模块。在LVDS接收电路中,通过ESD保护电路、轨对轨放大电路、迟滞比较电路、整形缓冲电路和失效保护电路的设计,完成了将2.5Gbps的LVDS信号转化为CMOS信号的工作。仿真结果表明,整个LVDS接收电路的延时为0.45ns,上升时间为0.04ns,下降时间为0.03ns,占空比为37:36,满足设计要求。
在串并转换电路中,为了满足高速和低时钟的要求,采用一种树型结构和移位寄存器结构级联的串并转换电路。通过占空比为1:4的5分频器、树型结构串并转换电路和移位寄存器结构串并转换电路的设计,将1路2.5Gbps的数据转化为10路250Mbps的数据。仿真结果表明,整个串并转换电路的功能正确,满足设计要求。
此外,本文在版图方面进行了研究,对匹配、串扰、噪声、寄生效应、闩锁效应和天线效应分别进行了论述,给出相应的解决办法。并基于1P8M 0.13μm CMOS工艺,采用全定制完成了版图设计。LVDS接收电路版图面积为74×96 ? m2,满足I/O标准;串并转换电路版图面积为80×83 ? m2。后仿真结果表明,本文设计的串并转换电路满足要求。
With the development of information technology, the amount of data transmission is more and more increasing. Due to its limitations, the traditional I/O interfaces can not meet people's needs. Low Voltage Differential Signal Transmission Technology has low noise, low power, high reliability, saving cost and strong integration capability. So it becomes a new technology to the solution of I/O interface.
This paper which studies the deserializer based on high speed LVDS is under ANSI/TIA/EIA-644. On this basis, according to the function, it can be parted two main modules—the receive circuit of the LVDS and deserializer.
In LVDS receiver circuit, the ESD protection circuit, rail to rail amplifier, comparator circuit, shaping-buffer circuits and fail-safe circuits transform 2.5Gbps of LVDS signals into CMOS signals. Through Simulation, the LVDS receiver circuit delay 0.45ns. The rise time is 0.04ns, and the fall time is 0.03ns ,Duty cycle is 37:36. It meets the design requirements.
In deserializer, in order to meet the requirements of high speed and low clock requirements, it is wonderful to use a tree structure deserializer and register structure deserializers. Through the duty cycle of 1:4 divider(divide-by-5), tree structure deserializer and register structure deserializer, it completed down to a 2.5Gbps data into the data of 10 road 250Mbps. Through simulation, it has the correct function and it is enough to meet the design requirements.
Besides, layout is researched in-depth. Discussing the matching, crosstalk, noise, parasitic effects, the latch and antenna effect, I give appropriate solutions. The design based on 1P8M 0.13μm CMOS process is completed using full-custom layout method. Layout of the LVDS receiver circuit is 74×96 ? m2 and it meets the standard of I/O. Layout of the deserializer is 80×83 ? m2. Post-simulation shows that the deserializer meets the design requirements.
引文
[1]王胜,王新宇.LVDS技术及其在高速系统中的应用.遥测遥控,2005年第26卷4期:41-46.
[2]彭勇,黄秋元.LVDS的接口电路设计.武汉理工大学学报信息与工程版,2005.10第27卷第5期:189-192.
[3]司朝良.LVDS接口电路及设计.今日电子,应用天地,2003年第一期.
[4]贾小燕.在FPGA中利用SoftSerDes技术实现信号串并转换的研究.硕士论文.2008.5
[5] http:// www.national.com
[6] http:// www.ti.com
[7] Uwe Vogel, Rolf J?hne, Steffen Ulbricht, etc.LVDS I/O Cells with Rail-to-Rail Receiver Input for SONET/SDH at 1.25Gb/s.IEEE
[8] Gunjan Mandal, Pradip Mandal.Low-Power LVDS Receiver for 1.3Gbps Physical Layer(PHY) Interface.IEEE.2005.2180-2183.
[9] Kwan-Woo Yoo, Jeong Beom Kim.Design of a High-Speed LVDS I/O Interface Using Telescopic Amplifier.IEEE.2006.
[10] Nguyen Thi Hang Nga, Min Hyuk Lee, Tae-Woo Lee, etc.10 Gb/s SerDes for Bidirectional Chip-to-Memory Optical Interconnection.IEEE.
[11] Yifei Luo, Gang Chen, Kuan Zhou . 60Gb/s Low Jitter 4:1 Mux and 1:4 DeMux.IEEE.2008.590-593.
[12] Byung-Guk Kim, Lee-Sup Kim, Sangjin Byun.A 20 Gb/s 1:4 DEMUX Without Inductors and Low-Power Divide-by-2 Circuit in 0.13um CMOS Technology.IEEE.2008.541-549.
[13] Takayuki Sekiguchi, Shuhei Amakawa, Noboru Ishihara.An 8.9mW 25Gb/s Inductorless 1:4 DEMUX in 90nm CMOS.IEEE.2009.404-407.
[14] A. Mineyamal, T. Suzuki, H. Ito, etc.A 20 Gb/s 1:4 DEMUX with Near-Rail-to-Rail Logic Swing in 90 nm CMOS process.IEEE.Feb.19-20,2009.119-122.
[15]尤扬,陈岚.一种高性能CMOS LVDS接收电路的设计.微电子学.2007.12.第37卷第6期.899-902.
[16]张家川,刘伯安.高速多电平LVDS收发器设计.微电子学与计算机.2007.第24卷第4期.69-71,75.
[17] Feng Zhang, Zongren Yang, Wei Feng, etc.A High Speed CMOS Transmitter And Rail-to-Rail Receiver.IEEE.2008.67-70.
[18]卞振鹏,姚若河,郑学仁等.1Gbps低功耗轨到轨mini-LVDS接收器.桂林电子科技大学学报.2008.8.第28卷第4期.285-289.
[19]殷弼君,李苗.用于网络通信的LVDS收发器的设计.计算机工程.2008.9.第34卷第17期.232-234.
[20] Wang Xihu, Wu Longsheng, Liu Youbao.LOW-POWER LVDS I/O INTERFACE FOR ABOVE 2GB/S-PER-PIN OPERATION.JOURNAL OF ELECTRONICS (CHINA).July, 2009.Vol.26, No.4.525-531.
[21]马鸿开,陈岚,刘力珂.10GB/s高速SERDES电路的MUX/DEMUX设计.微电子学与计算机.2007年第24卷第12期.174-176.
[22] Yu-Hao Hsu, Ming-Hao Lu, Ping-Lin Yang, etc.A 28Gbps 4×4 Switch with Low Jitter SerDes Using Area-Saving RF Model in 0.13μm CMOS Technology.IEEE.2008.3086-3089.
[23] XiaoLei, Liu Wei, Yang Lianxing.A Low Jitter Design of Ring Oscillators in 1.25GHz Serdes.半导体学报.2008.3.第29卷第3期.490-496.
[24]洪建勋,周建新,陈水平等.基于微环谐振器的光分组头串并转换研究.武汉理工大学学报.2009.12.第31卷第23期.85-88.
[25]王堃，许文强,马卓.PCI Express中2.5Gbps高速SerDes的设计与实现.计算机工程与科学.2009年第31卷第11期.62-65,120.
[26]刘玮,肖磊,杨莲兴.1.25 Gbps串并并串转换接收器的低抖动设计.固体电子学研究与进展.2009.3.第29卷第1期.99-105.
[27]郭之光.LVDS设计及应用.硕士论文.2007.1
[28]吴显灵,张金平,张定会.电路中的ESD保护.仪器仪表学报.第27卷第6期增刊.2006.6:2560-2561.
[29] JEDEC Std A114-A, Electrostatic discharge(ESD) sensitivity testing human body model(HBM),IEEE,1997.
[30] JEDEC Std A115-A, Electrostatic discharge(ESD) sensitivity testing machine model(MM),IEEE,1997.
[31]刘军,傅东兵.混合信号IC的ESD保护电路设计.微电子学.2009.2.第39卷第1期.62-64,68.
[32]莫迟,应建华,邹望辉.LVDS高速数据驱动器电路设计与研究.华中科技大学学报(自然科学版) ,2003.10.第31卷第10期:13-15.
[33] Electrical characteristics of low-voltage differential-signaling (LVDS) interface circuits, TIA/EIA-644, National Semiconductor Corp, ANSI/TIA/EIA, 1996.
[34] National Semiconductor, LVDS Owner’s Manual: A General Design Guide for National’s Low Voltage Differential Signaling (LVDS) and Bus LVDS Products, www.national.com/appinfo/lvds.
[35]刘祥远,陈书明.LVDS高速I/ O接口单元的设计研究.计算机工程与科学,2001年第23卷第4期:52-56,60.
[36]李爱玲,张伯珩,边川平,达远福.LVDS低功耗高速驱动电路设计.科学技术与工程.2005年10月第5卷19期:1307-1311.
[37]宋正勋,谭宝华.低压差份信号技术.长春光学精密机械学院学报.2000年:23(2):33-36.
[38]倪春波,应建华,刘三清,邹雪城.LVDS高速I/O接口电路设计.华中科技大学学报(自然科学版).2003年10月:第31卷第10期:16-18.
[39] Ajith Amerasekera, Charvaka Duvvury . ESD in Silicon Integrated Circuits, 2nd Edition,87,2002.
[40]杜鸣,赫跃.CMOS工艺中栅耦合ESD保护电路.西安电子科技大学学报(自然科学版),第33卷第4期,2006.8.
[41] Behzad Razavi. Design of Analog CMOS Integrated Circuits. 2003.2.92-94
[42] Phillip E.Allen et al. CMOS模拟集成电路设计.2005.3.359-361,388-390.
[43] RAZAVIB,WOOLEY A.Design techniques for high-speed, high-resolution comparators [J].IEEE J SolSta Circ,1992,27(12):1916-1926.
[44] Willy M.C Sansen,陈莹梅译.模拟集成电路设计精粹.清华大学出版社,2008.3
[45]肖海鹏.2.5Gbps高速LVDS收发器的设计与实现.硕士论文.2009.7.
[46] Jan M . Rabaey, Anantha Chandrakasan . Digital Integrated Circuits A Design Perspective(second Edition).电子工业出版社,2004
[47] LVDS Receiver Failsafe Biasing Network.http://www.fairchild.com
[48]蔡敏,王谧.LVDS接收器的失效保护电路设计.半导体技术,2005,30(4):61-64.
[49]朱江.高速数据发接器的研究与实现[D].上海复旦大学博士学位论文..2001.
[50]沈桢.千兆/万兆以太网串并转换集成电路设计.硕士论文.2004.3.
[51] Ching—Yuan Yang,GK Dehng,J.M Hsu,and S.I Liu.new dynamic flip-flops for high-speed dual-modulus prescaler.IEEE journal of solid-state circuits.1998.vol.33.1568-1571,Oct.1998.
[52] Jiren Yuan,and C.Svensson.High-Speed CMOS Circuit Technique.IEEE journal of solid-state circuits.Feb.1989.Vol.24.No.1.62—67.
[53] Jiren Yuan,and C.Svensson.New single-Clock CMOS Latches and Fipflops with ImprovedSpeed and Power Savings.IEEE journal of solid-state circuits.Jan.1997.Vol.32 No.l.62-69.
[54] Alan Hastings,王志功等译.模拟电路版图的艺术.2004.4,第一版.
[55] Christopher Saint, Judy Saint. IC Mask Design. 2004.1.
[56] Behzad Razavi. Design of Analog CMOS Integrated Circuits. 2003.2.517-520.
[57] National Semiconductor.SCAN921025 and SCAN921226 30-80 MHz 10 Bit Bus LVDS Serializer and Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST.
[58] R.R.Troutman. Latchup in CMOS Technology-The Problem and Its Cure, Kluwer Academic Press, 1986.
[59] Clein Dan, Gregg SHIMOKURA. CMOS IC Layout. 1999. .
[2]彭勇,黄秋元.LVDS的接口电路设计.武汉理工大学学报信息与工程版,2005.10第27卷第5期:189-192.
[3]司朝良.LVDS接口电路及设计.今日电子,应用天地,2003年第一期.
[4]贾小燕.在FPGA中利用SoftSerDes技术实现信号串并转换的研究.硕士论文.2008.5
[5] http:// www.national.com
[6] http:// www.ti.com
[7] Uwe Vogel, Rolf J?hne, Steffen Ulbricht, etc.LVDS I/O Cells with Rail-to-Rail Receiver Input for SONET/SDH at 1.25Gb/s.IEEE
[8] Gunjan Mandal, Pradip Mandal.Low-Power LVDS Receiver for 1.3Gbps Physical Layer(PHY) Interface.IEEE.2005.2180-2183.
[9] Kwan-Woo Yoo, Jeong Beom Kim.Design of a High-Speed LVDS I/O Interface Using Telescopic Amplifier.IEEE.2006.
[10] Nguyen Thi Hang Nga, Min Hyuk Lee, Tae-Woo Lee, etc.10 Gb/s SerDes for Bidirectional Chip-to-Memory Optical Interconnection.IEEE.
[11] Yifei Luo, Gang Chen, Kuan Zhou . 60Gb/s Low Jitter 4:1 Mux and 1:4 DeMux.IEEE.2008.590-593.
[12] Byung-Guk Kim, Lee-Sup Kim, Sangjin Byun.A 20 Gb/s 1:4 DEMUX Without Inductors and Low-Power Divide-by-2 Circuit in 0.13um CMOS Technology.IEEE.2008.541-549.
[13] Takayuki Sekiguchi, Shuhei Amakawa, Noboru Ishihara.An 8.9mW 25Gb/s Inductorless 1:4 DEMUX in 90nm CMOS.IEEE.2009.404-407.
[14] A. Mineyamal, T. Suzuki, H. Ito, etc.A 20 Gb/s 1:4 DEMUX with Near-Rail-to-Rail Logic Swing in 90 nm CMOS process.IEEE.Feb.19-20,2009.119-122.
[15]尤扬,陈岚.一种高性能CMOS LVDS接收电路的设计.微电子学.2007.12.第37卷第6期.899-902.
[16]张家川,刘伯安.高速多电平LVDS收发器设计.微电子学与计算机.2007.第24卷第4期.69-71,75.
[17] Feng Zhang, Zongren Yang, Wei Feng, etc.A High Speed CMOS Transmitter And Rail-to-Rail Receiver.IEEE.2008.67-70.
[18]卞振鹏,姚若河,郑学仁等.1Gbps低功耗轨到轨mini-LVDS接收器.桂林电子科技大学学报.2008.8.第28卷第4期.285-289.
[19]殷弼君,李苗.用于网络通信的LVDS收发器的设计.计算机工程.2008.9.第34卷第17期.232-234.
[20] Wang Xihu, Wu Longsheng, Liu Youbao.LOW-POWER LVDS I/O INTERFACE FOR ABOVE 2GB/S-PER-PIN OPERATION.JOURNAL OF ELECTRONICS (CHINA).July, 2009.Vol.26, No.4.525-531.
[21]马鸿开,陈岚,刘力珂.10GB/s高速SERDES电路的MUX/DEMUX设计.微电子学与计算机.2007年第24卷第12期.174-176.
[22] Yu-Hao Hsu, Ming-Hao Lu, Ping-Lin Yang, etc.A 28Gbps 4×4 Switch with Low Jitter SerDes Using Area-Saving RF Model in 0.13μm CMOS Technology.IEEE.2008.3086-3089.
[23] XiaoLei, Liu Wei, Yang Lianxing.A Low Jitter Design of Ring Oscillators in 1.25GHz Serdes.半导体学报.2008.3.第29卷第3期.490-496.
[24]洪建勋,周建新,陈水平等.基于微环谐振器的光分组头串并转换研究.武汉理工大学学报.2009.12.第31卷第23期.85-88.
[25]王堃，许文强,马卓.PCI Express中2.5Gbps高速SerDes的设计与实现.计算机工程与科学.2009年第31卷第11期.62-65,120.
[26]刘玮,肖磊,杨莲兴.1.25 Gbps串并并串转换接收器的低抖动设计.固体电子学研究与进展.2009.3.第29卷第1期.99-105.
[27]郭之光.LVDS设计及应用.硕士论文.2007.1
[28]吴显灵,张金平,张定会.电路中的ESD保护.仪器仪表学报.第27卷第6期增刊.2006.6:2560-2561.
[29] JEDEC Std A114-A, Electrostatic discharge(ESD) sensitivity testing human body model(HBM),IEEE,1997.
[30] JEDEC Std A115-A, Electrostatic discharge(ESD) sensitivity testing machine model(MM),IEEE,1997.
[31]刘军,傅东兵.混合信号IC的ESD保护电路设计.微电子学.2009.2.第39卷第1期.62-64,68.
[32]莫迟,应建华,邹望辉.LVDS高速数据驱动器电路设计与研究.华中科技大学学报(自然科学版) ,2003.10.第31卷第10期:13-15.
[33] Electrical characteristics of low-voltage differential-signaling (LVDS) interface circuits, TIA/EIA-644, National Semiconductor Corp, ANSI/TIA/EIA, 1996.
[34] National Semiconductor, LVDS Owner’s Manual: A General Design Guide for National’s Low Voltage Differential Signaling (LVDS) and Bus LVDS Products, www.national.com/appinfo/lvds.
[35]刘祥远,陈书明.LVDS高速I/ O接口单元的设计研究.计算机工程与科学,2001年第23卷第4期:52-56,60.
[36]李爱玲,张伯珩,边川平,达远福.LVDS低功耗高速驱动电路设计.科学技术与工程.2005年10月第5卷19期:1307-1311.
[37]宋正勋,谭宝华.低压差份信号技术.长春光学精密机械学院学报.2000年:23(2):33-36.
[38]倪春波,应建华,刘三清,邹雪城.LVDS高速I/O接口电路设计.华中科技大学学报(自然科学版).2003年10月:第31卷第10期:16-18.
[39] Ajith Amerasekera, Charvaka Duvvury . ESD in Silicon Integrated Circuits, 2nd Edition,87,2002.
[40]杜鸣,赫跃.CMOS工艺中栅耦合ESD保护电路.西安电子科技大学学报(自然科学版),第33卷第4期,2006.8.
[41] Behzad Razavi. Design of Analog CMOS Integrated Circuits. 2003.2.92-94
[42] Phillip E.Allen et al. CMOS模拟集成电路设计.2005.3.359-361,388-390.
[43] RAZAVIB,WOOLEY A.Design techniques for high-speed, high-resolution comparators [J].IEEE J SolSta Circ,1992,27(12):1916-1926.
[44] Willy M.C Sansen,陈莹梅译.模拟集成电路设计精粹.清华大学出版社,2008.3
[45]肖海鹏.2.5Gbps高速LVDS收发器的设计与实现.硕士论文.2009.7.
[46] Jan M . Rabaey, Anantha Chandrakasan . Digital Integrated Circuits A Design Perspective(second Edition).电子工业出版社,2004
[47] LVDS Receiver Failsafe Biasing Network.http://www.fairchild.com
[48]蔡敏,王谧.LVDS接收器的失效保护电路设计.半导体技术,2005,30(4):61-64.
[49]朱江.高速数据发接器的研究与实现[D].上海复旦大学博士学位论文..2001.
[50]沈桢.千兆/万兆以太网串并转换集成电路设计.硕士论文.2004.3.
[51] Ching—Yuan Yang,GK Dehng,J.M Hsu,and S.I Liu.new dynamic flip-flops for high-speed dual-modulus prescaler.IEEE journal of solid-state circuits.1998.vol.33.1568-1571,Oct.1998.
[52] Jiren Yuan,and C.Svensson.High-Speed CMOS Circuit Technique.IEEE journal of solid-state circuits.Feb.1989.Vol.24.No.1.62—67.
[53] Jiren Yuan,and C.Svensson.New single-Clock CMOS Latches and Fipflops with ImprovedSpeed and Power Savings.IEEE journal of solid-state circuits.Jan.1997.Vol.32 No.l.62-69.
[54] Alan Hastings,王志功等译.模拟电路版图的艺术.2004.4,第一版.
[55] Christopher Saint, Judy Saint. IC Mask Design. 2004.1.
[56] Behzad Razavi. Design of Analog CMOS Integrated Circuits. 2003.2.517-520.
[57] National Semiconductor.SCAN921025 and SCAN921226 30-80 MHz 10 Bit Bus LVDS Serializer and Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST.
[58] R.R.Troutman. Latchup in CMOS Technology-The Problem and Its Cure, Kluwer Academic Press, 1986.
[59] Clein Dan, Gregg SHIMOKURA. CMOS IC Layout. 1999. .