面向全定制与半定制混合设计方法的噪声分析与设计
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摘要
随着工艺尺寸的日益缩小,集成电路已经进入了深亚微米甚至超深亚微米时代。在新的工艺水平下,噪声和其它的电学问题更加严重:线间串扰加大了时序的不确定性和耦合电平,IR压降降低了电路的性能,漏流效应使得电路的可靠性降低等等,信号完整性问题已经成为了集成电路设计的一个挑战。
动态电路是一种高速但对噪声非常敏感的电路,被广泛使用。本文深入分析了动态节点上的噪声影响以及动态节点的噪声容限,提出了一种新的抗噪声的动态电路(CBL),它可以有效地改善多米诺逻辑的噪声容限,而又不丧失多米诺逻辑的性能。此外,针对Cluster设计中的高速译码电路中的电荷分享问题,提出了一种改进电路,有效地解决了电荷分享问题;针对一种高速寄存器文件中长线末端驱动动态电路的问题,提出了一种改进方案,大大提高了电路的可靠性。
当前,大规模的集成电路设计必须依赖于CAD辅助工具来保证信号完整性。对于半定制的设计方法,我们可以使用PTSI等工具分析门级电路的噪声;对于小规模的全定制设计,可以使用HSPICE对晶体管级电路进行模拟以确保电路的正常工作。但是,当前有一种工具支持全定制与半定制混合设计方法的噪声分析(HSPICE工具受限于规模,不能做大规模的模拟)。本文针对这一难点,从分析方法上着手,提出了一种噪声分析流程。该流程以现有的EDA工具为基础,通过对全定制电路模块进行特征化封装,有效地解决了混合设计方法的噪声分析问题。最后,使用该流程对一个4位的地址译码器进行分析,然后将分析结果与HSPICE模拟结果进行对比,表明该流程是准确而有效的。
Continuous scaling of technologies towards deep submicron, even ultra-deep submicron will severely aggravate noise and other electrical problems, such as interconnect crosstalk, IR-drop, leakage current, and so on, which may lead to different kinds of unexpected behaviors including logic or functional failure of digital circuits. Since the impact of noise is becoming critical, it's important to study signal integrity in deep submicron IC design.
The usage of noise sensitive dynamic circuits has become commonplace due to speed and area requirements, making the noise issue even more serious. This paper focuses on the capaci-tive coupling and its effects on dynamic node. The paper proposes a new leakage tolerant dynamic circuit style, Complementary Boost Logic (CBL), which highly improves domino's noise immunity and keeps high performance. A new circuit style improving the charge sharing noise of the high speed decoder logic in the cluster design is presented in this dissertation. To solve the long wire runs feeding domino gate inputs, we give an improved circuit, which efficiently increases the circuit's reliability.
Today, we have to employ CAD tools to analysis signal integrity in the large scale circuits. For semi-custom design method, we can use PTSI or other tools to analyze the noise of gate-level netlist, and for full-custom design method, we can employ HSPICE to simulate small scale transistor-level netlist, whereas there are no EDA tools to support the signal integrity analysis for the full-custom & semi-custom mixed design method. We propose a new noise analyze flow, making use of existing EDA tools by characterizing full-custom functional module, which completely solves this problem. Finally, we compare the analysis result of a full-custom & semi-custom mixed designed four-bit address decoder with its HSPICE simulation result. The results prove this flow accurate and effective.
动态电路是一种高速但对噪声非常敏感的电路,被广泛使用。本文深入分析了动态节点上的噪声影响以及动态节点的噪声容限,提出了一种新的抗噪声的动态电路(CBL),它可以有效地改善多米诺逻辑的噪声容限,而又不丧失多米诺逻辑的性能。此外,针对Cluster设计中的高速译码电路中的电荷分享问题,提出了一种改进电路,有效地解决了电荷分享问题;针对一种高速寄存器文件中长线末端驱动动态电路的问题,提出了一种改进方案,大大提高了电路的可靠性。
当前,大规模的集成电路设计必须依赖于CAD辅助工具来保证信号完整性。对于半定制的设计方法,我们可以使用PTSI等工具分析门级电路的噪声;对于小规模的全定制设计,可以使用HSPICE对晶体管级电路进行模拟以确保电路的正常工作。但是,当前有一种工具支持全定制与半定制混合设计方法的噪声分析(HSPICE工具受限于规模,不能做大规模的模拟)。本文针对这一难点,从分析方法上着手,提出了一种噪声分析流程。该流程以现有的EDA工具为基础,通过对全定制电路模块进行特征化封装,有效地解决了混合设计方法的噪声分析问题。最后,使用该流程对一个4位的地址译码器进行分析,然后将分析结果与HSPICE模拟结果进行对比,表明该流程是准确而有效的。
Continuous scaling of technologies towards deep submicron, even ultra-deep submicron will severely aggravate noise and other electrical problems, such as interconnect crosstalk, IR-drop, leakage current, and so on, which may lead to different kinds of unexpected behaviors including logic or functional failure of digital circuits. Since the impact of noise is becoming critical, it's important to study signal integrity in deep submicron IC design.
The usage of noise sensitive dynamic circuits has become commonplace due to speed and area requirements, making the noise issue even more serious. This paper focuses on the capaci-tive coupling and its effects on dynamic node. The paper proposes a new leakage tolerant dynamic circuit style, Complementary Boost Logic (CBL), which highly improves domino's noise immunity and keeps high performance. A new circuit style improving the charge sharing noise of the high speed decoder logic in the cluster design is presented in this dissertation. To solve the long wire runs feeding domino gate inputs, we give an improved circuit, which efficiently increases the circuit's reliability.
Today, we have to employ CAD tools to analysis signal integrity in the large scale circuits. For semi-custom design method, we can use PTSI or other tools to analyze the noise of gate-level netlist, and for full-custom design method, we can employ HSPICE to simulate small scale transistor-level netlist, whereas there are no EDA tools to support the signal integrity analysis for the full-custom & semi-custom mixed design method. We propose a new noise analyze flow, making use of existing EDA tools by characterizing full-custom functional module, which completely solves this problem. Finally, we compare the analysis result of a full-custom & semi-custom mixed designed four-bit address decoder with its HSPICE simulation result. The results prove this flow accurate and effective.
引文
[1]ITRS Roadmap 2005.http://public.itrs.net
[2]ITRS 2006 Update.http://public.itrs.net/Files/2006Update/2006Update.pdf
[3]Jan M.Rabaey,Anantha Chandrakasan,Borivoje Nikolic.Digital Integrated Circuits A Design Perspective(Second Edition).Tsinghua University Press,March 2004
[4]Nagaraj NS.Interconnect Modeling,Signal Integrity and Reliability Analysis for Deep Sub-Micron Integrated Circuits.Ph.D.dissertation,2003
[5]M.Masud Hasan Chowdhury.Noise Analysis and Design Methodologies in Deep Sub-Micron VLSI Circuits.Ph.D.dissertation,2004
[6]Mohamed A.Elgamel.Interconnect Noise Analysis and Optimization for High-Performance Designs in Nanometer Technologies.Ph.D.dissertation,2003
[7]利用Liberty CCS建模技术实现高精密度EDA分析.http://www.eettaiwan.com/ART_8800472021 480102 TA e64d9540.HTM
[8]文梅等.Imagine流体系结构研究与评测.体系结构会议,2004
[9]Wei Sufeng.Crosstalk Noise Analysis and Repair Methodology with PrimeTime-SI.Synopsys World Leader in EDA Software and Services,2003
[10]王强.全定制版图设计中信号完整性的分析.山东大学,2005
[11]http://developer.intel.com/technology/itj/q12001/articles/art_5.htm
[12]W.R.Hunter.Self-Consistent Solutions for Allowed Interconnect Current Density--Part Ⅰ:Implications for Technology Evolution.IEEE Trans.Electron Devices,vol.44,no.2,February 1997
[13]Andrew B.Kahng,Sudhakar Muddu,and Devendra Vidhani.Noise and Delay Uncertainty Studies for Coupled RC Interconnects.IEEE International ASIC/SOC Conferrence,September 1999
[14]Masud H.Chowdhury,Y.I.Ismail,C.V.Kashyap,and B.L.Krauter.Preformance Analysis of Deep Sub-Micron VLSI Circuits in the Presence of Self and Mutual Inductance.IEEE International Symposium on Circuits And Systems(ISCAS),Low-Noise Circuits and Interconnect Issues,May 2002
[15]J.Cong.An Interconnect-centric Design Flow for Nanometer Technologies.Int.Symp.VLSI Technology,Systems,and Applications,June 1999
[16]M.R.Stan and W.P.Buileson.Bus-invert Coding for Low-power I/O.IEEE Trans.On VLSI SYSTEMS,Mar.1995
[17]L.Benini,A.Macii,E.Macii,M.Poncino,and R.Scarsi.Synthesis of Low-overhead Interfaces for Power-efficient Communication Over Wide Buses.ACM/IEEE Design Automation ConS,1999
[18]P.R.Panda and N.D.Dutt.Reducing Address Bus Transitions for Low Power Memory Mapping. European Design and Test Conz, Mar. 1996
[19]H. Mehta, R. M. Owens, and M. J. Irwin. Some Issues in Gray Code Addressing, the Great Lakes Symp. VLSI, Mar. 1996
[20]C. L. Su, C. Y. Tsui, and A. M. Despain. Saving Power in the Control Path of Embedded Processors. IEEE Design and Test of Computers, 1994
[21]L. Benini, G. De Micheli, E. Macii, D. Sciuto and C. Silvano. Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-power Microprocessor-based Systems, the Great Lakes Symp. VLSI, 1997
[22] E. Musoll, T. Lang, and J. Cortadella. Working-zone Encoding for Reducing the Energy in Microprocessor Address Buses. IEEE Trans. on VLSI Systems, vol. 6, no. 4, Dec. 1998
[23] Y. Zhang, W. Ye, and M. J. Irwin. An Alternative Architecture for On-chip Global Interconnect: Segmented Bus Power Modeling. Asilomar Con$ on Signals, Systems, and Computers, 1998
[24] F. Catthoor, F. Franssen, S. Wuytack, L. Nachtergaele, and H. D. Man. Global Communication and Memory Optimizing Transformations for Low Power Signal Processing Systems. VLSI Signal Processing VII, 1994
[25] L. Benini, G. De Micheli, E. Macii, D. Sciuto, and C. Silvano. Address Bus Encoding Techniques for System-level Power Optimization. Design, Automation and Test in Europe, Feb. 1998
[26] Lei He and Kevin M. Lepak. Simultaneous Shield Insertion and Net Ordering for Capaci-tive and Inductive Coupling Minimization. In proceedings of the 2000 International Symposium on Physical Design (ISPD-2000)
[27] H. Kaul, D. Sylvester, and D. Blaauw. Active Shield: A New Approach to Shield Global Wires. Proc. of GLSVLSI, April, 2002
[28] Y. Massoud, J. Kawa, D. MacMillen, and J. White. Modeling and Analysis of Different Signaling for Minimizing Inductive Cross-Talk. Proceedings of the 38th Design Automation Conference, 2001
[29] M. D. Powell, S.H. Yang, B. Falsafi, K. Roy, and T. N. Vijayku-mar. Gated-Vdd: A Circuit Technique to Reduce Leakage in Cache Memories. Intl. Symposium on Low Power Electronics and Design, July 2000
[30] G. P. D'Souza. Dynamic Logic Circuit with Reduced Charge Leakage. U.S. Patent 5483181,1996
[31]J. J. Covino. Dynamic CMOS Circuits with noise immunity. U.S. Patent 5650733,1997
[32] L. Wang and N. R. Shanbhag. Noise-tolerant dynamic circuit design. IEEE Intl. Symp. on Circuits and Systems, pp. 549-552, Orlando, FL, May/June 1999
[33]G. Balammgan and N. R. Shanbhag. A noise-tolerant dynamic circuit design tech-nique. 2000 Custom Integrated Circuits Conference, May 21-24, 2000
[34] James T. Kao, and Anantha P. Chandrakasan. Dual-Threshold Voltage Techniques for Low-Power Digital Circuits. IEEE Journ. Solid-State Circuits, vol. 35, July 2000
[35]Assaderaghi Fariborz,Sinitsky Dennis,Parko Stephen,Bokor Jaffiey,KO Ping,Hu,Chenming.Dynamic Threshold-voltage MOSFET(DTMOS) for Ultra-low Voltage VLSI," IEEE Transactions on Electron Devices vol.44,no.3,March 1997
[36]N.D.Arora,K.V.Raol,R.Schumann,and L.M.Richardson.Modeling and Extr-action of Interconnect Capacitance for Multi-layer VLSI Circuits.IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems,vol.15,no.1,January 1996
[37]D.Sylvester,C.Hu,O.S.Nakagawa,and S.Y.Oh.Interconnect Scaling:Signal Integrity and Performance in Future High-Speed CMOS Designs.Symposium on VLSI Technology,1998
[38]T.Sakurai and A.R.Newton.Alpha-power law MOSFET model and its applic-ation to CMOS inverter delay and other formulas.IEEE Journal of Solid-State Circuits,vol.25,mo.2,April 1990
[39]Jae-Joon Kim and Kaushik Roy.A leakage tolerant high fan-in dynamic circuit design technique.IEEE
[40]Lei Wang,Ram K.Krishnamuithy,K.soumyanath,and Naresh R.Shanbhag.An energy-efficient leakage-tolerant dynamic circuit technique.IEEE 2000
[41]Ram K.Krishnamurthy,Atila Alvandpour,Ganesh Balamurugan,Naresh R.Shanbhag,K.Soumyanath,Shekhar Y.Borkar.A 130-nm 6-GHz 256 32 bit Leakage-Tolerant Register File.IEEE JOURNAL OF SOLID-STATE CIRCITS,VOL.37,NO.5,MAY 2002
[42]Synopsys:Library Compiler User Guide,Version 2006-12
[43]CCS Timing Technical White Paper.www.synopsys.com/products/libertyccs/ccs_timin g_wp.pdf
[44]Composite Current Source(CCS) Modeling Technology Backgrounder.www.synops ys.com/products/solutions/galaxy/ccs/ccs_bgr.pdf
[45]CCS噪声模型:用于串扰噪声分析的高精确度建模.http://www.eettaiwan.com/ARTP 8800408038 480102.HTM
[2]ITRS 2006 Update.http://public.itrs.net/Files/2006Update/2006Update.pdf
[3]Jan M.Rabaey,Anantha Chandrakasan,Borivoje Nikolic.Digital Integrated Circuits A Design Perspective(Second Edition).Tsinghua University Press,March 2004
[4]Nagaraj NS.Interconnect Modeling,Signal Integrity and Reliability Analysis for Deep Sub-Micron Integrated Circuits.Ph.D.dissertation,2003
[5]M.Masud Hasan Chowdhury.Noise Analysis and Design Methodologies in Deep Sub-Micron VLSI Circuits.Ph.D.dissertation,2004
[6]Mohamed A.Elgamel.Interconnect Noise Analysis and Optimization for High-Performance Designs in Nanometer Technologies.Ph.D.dissertation,2003
[7]利用Liberty CCS建模技术实现高精密度EDA分析.http://www.eettaiwan.com/ART_8800472021 480102 TA e64d9540.HTM
[8]文梅等.Imagine流体系结构研究与评测.体系结构会议,2004
[9]Wei Sufeng.Crosstalk Noise Analysis and Repair Methodology with PrimeTime-SI.Synopsys World Leader in EDA Software and Services,2003
[10]王强.全定制版图设计中信号完整性的分析.山东大学,2005
[11]http://developer.intel.com/technology/itj/q12001/articles/art_5.htm
[12]W.R.Hunter.Self-Consistent Solutions for Allowed Interconnect Current Density--Part Ⅰ:Implications for Technology Evolution.IEEE Trans.Electron Devices,vol.44,no.2,February 1997
[13]Andrew B.Kahng,Sudhakar Muddu,and Devendra Vidhani.Noise and Delay Uncertainty Studies for Coupled RC Interconnects.IEEE International ASIC/SOC Conferrence,September 1999
[14]Masud H.Chowdhury,Y.I.Ismail,C.V.Kashyap,and B.L.Krauter.Preformance Analysis of Deep Sub-Micron VLSI Circuits in the Presence of Self and Mutual Inductance.IEEE International Symposium on Circuits And Systems(ISCAS),Low-Noise Circuits and Interconnect Issues,May 2002
[15]J.Cong.An Interconnect-centric Design Flow for Nanometer Technologies.Int.Symp.VLSI Technology,Systems,and Applications,June 1999
[16]M.R.Stan and W.P.Buileson.Bus-invert Coding for Low-power I/O.IEEE Trans.On VLSI SYSTEMS,Mar.1995
[17]L.Benini,A.Macii,E.Macii,M.Poncino,and R.Scarsi.Synthesis of Low-overhead Interfaces for Power-efficient Communication Over Wide Buses.ACM/IEEE Design Automation ConS,1999
[18]P.R.Panda and N.D.Dutt.Reducing Address Bus Transitions for Low Power Memory Mapping. European Design and Test Conz, Mar. 1996
[19]H. Mehta, R. M. Owens, and M. J. Irwin. Some Issues in Gray Code Addressing, the Great Lakes Symp. VLSI, Mar. 1996
[20]C. L. Su, C. Y. Tsui, and A. M. Despain. Saving Power in the Control Path of Embedded Processors. IEEE Design and Test of Computers, 1994
[21]L. Benini, G. De Micheli, E. Macii, D. Sciuto and C. Silvano. Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-power Microprocessor-based Systems, the Great Lakes Symp. VLSI, 1997
[22] E. Musoll, T. Lang, and J. Cortadella. Working-zone Encoding for Reducing the Energy in Microprocessor Address Buses. IEEE Trans. on VLSI Systems, vol. 6, no. 4, Dec. 1998
[23] Y. Zhang, W. Ye, and M. J. Irwin. An Alternative Architecture for On-chip Global Interconnect: Segmented Bus Power Modeling. Asilomar Con$ on Signals, Systems, and Computers, 1998
[24] F. Catthoor, F. Franssen, S. Wuytack, L. Nachtergaele, and H. D. Man. Global Communication and Memory Optimizing Transformations for Low Power Signal Processing Systems. VLSI Signal Processing VII, 1994
[25] L. Benini, G. De Micheli, E. Macii, D. Sciuto, and C. Silvano. Address Bus Encoding Techniques for System-level Power Optimization. Design, Automation and Test in Europe, Feb. 1998
[26] Lei He and Kevin M. Lepak. Simultaneous Shield Insertion and Net Ordering for Capaci-tive and Inductive Coupling Minimization. In proceedings of the 2000 International Symposium on Physical Design (ISPD-2000)
[27] H. Kaul, D. Sylvester, and D. Blaauw. Active Shield: A New Approach to Shield Global Wires. Proc. of GLSVLSI, April, 2002
[28] Y. Massoud, J. Kawa, D. MacMillen, and J. White. Modeling and Analysis of Different Signaling for Minimizing Inductive Cross-Talk. Proceedings of the 38th Design Automation Conference, 2001
[29] M. D. Powell, S.H. Yang, B. Falsafi, K. Roy, and T. N. Vijayku-mar. Gated-Vdd: A Circuit Technique to Reduce Leakage in Cache Memories. Intl. Symposium on Low Power Electronics and Design, July 2000
[30] G. P. D'Souza. Dynamic Logic Circuit with Reduced Charge Leakage. U.S. Patent 5483181,1996
[31]J. J. Covino. Dynamic CMOS Circuits with noise immunity. U.S. Patent 5650733,1997
[32] L. Wang and N. R. Shanbhag. Noise-tolerant dynamic circuit design. IEEE Intl. Symp. on Circuits and Systems, pp. 549-552, Orlando, FL, May/June 1999
[33]G. Balammgan and N. R. Shanbhag. A noise-tolerant dynamic circuit design tech-nique. 2000 Custom Integrated Circuits Conference, May 21-24, 2000
[34] James T. Kao, and Anantha P. Chandrakasan. Dual-Threshold Voltage Techniques for Low-Power Digital Circuits. IEEE Journ. Solid-State Circuits, vol. 35, July 2000
[35]Assaderaghi Fariborz,Sinitsky Dennis,Parko Stephen,Bokor Jaffiey,KO Ping,Hu,Chenming.Dynamic Threshold-voltage MOSFET(DTMOS) for Ultra-low Voltage VLSI," IEEE Transactions on Electron Devices vol.44,no.3,March 1997
[36]N.D.Arora,K.V.Raol,R.Schumann,and L.M.Richardson.Modeling and Extr-action of Interconnect Capacitance for Multi-layer VLSI Circuits.IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems,vol.15,no.1,January 1996
[37]D.Sylvester,C.Hu,O.S.Nakagawa,and S.Y.Oh.Interconnect Scaling:Signal Integrity and Performance in Future High-Speed CMOS Designs.Symposium on VLSI Technology,1998
[38]T.Sakurai and A.R.Newton.Alpha-power law MOSFET model and its applic-ation to CMOS inverter delay and other formulas.IEEE Journal of Solid-State Circuits,vol.25,mo.2,April 1990
[39]Jae-Joon Kim and Kaushik Roy.A leakage tolerant high fan-in dynamic circuit design technique.IEEE
[40]Lei Wang,Ram K.Krishnamuithy,K.soumyanath,and Naresh R.Shanbhag.An energy-efficient leakage-tolerant dynamic circuit technique.IEEE 2000
[41]Ram K.Krishnamurthy,Atila Alvandpour,Ganesh Balamurugan,Naresh R.Shanbhag,K.Soumyanath,Shekhar Y.Borkar.A 130-nm 6-GHz 256 32 bit Leakage-Tolerant Register File.IEEE JOURNAL OF SOLID-STATE CIRCITS,VOL.37,NO.5,MAY 2002
[42]Synopsys:Library Compiler User Guide,Version 2006-12
[43]CCS Timing Technical White Paper.www.synopsys.com/products/libertyccs/ccs_timin g_wp.pdf
[44]Composite Current Source(CCS) Modeling Technology Backgrounder.www.synops ys.com/products/solutions/galaxy/ccs/ccs_bgr.pdf
[45]CCS噪声模型:用于串扰噪声分析的高精确度建模.http://www.eettaiwan.com/ARTP 8800408038 480102.HTM