电子系统内建自测试技术研究
摘要
近年来,随着DSP、FPGA等超大规模集成电路的发展,国防军事装备等领域的电子系统性能大大提高,但同时给电子系统带来了新的测试和故障诊断问题。传统的电子系统测试技术存在着测试流程复杂、测试时间长、测试费用高、故障检测率低、无法实现在线测试等诸多问题,已经不能适应当前电子系统的测试要求,因此必须深入研究电子系统的测试理论和测试方法。
本文在研究电子系统可测试性设计和可测性理论的基础上,针对包含大规模集成电路的电子系统,提出内建自测试(Built-in Self Test,BIST)的解决方案。该方案通过电子系统自身资源生成测试矢量、加载测试激励、进行故障特征提取与优化,从而完成测试工作。本文从电子系统内建自测试的自动测试矢量生成、故障特征提取与优化、可测性建模和测试序列优化等方面开展研究工作,克服传统测试方法的不足,其研究成果可广泛应用于国防军事和工业现场的电子系统快速故障定位。
首先,针对目前电子系统内建自测试测试矢量生成方法存在故障检测率低的缺点,提出D-Tent(Digital Tent,D-Tent)和D-PL(Digital Piecewise Linear,D-PL)两种混沌自动测试矢量生成模型。将这两种模型经过参数优化选择和混沌特性分析后应用于标准测试电路进行实验研究,结果表明本文提出的自动测试矢量生成方法比其它方法的故障检测率更高。在此基础上,将混沌模型产生的时间序列测试矢量应用到模拟电路的内建自测试,利用输入混沌时间序列和输出时间序列的相关性作为故障特征,通过实验验证该方法的可行性。
为了降低电子系统内建自测试中模拟电路自动测试矢量生成的复杂性,并克服经过数模转换器而增加硬件电路面积和引入误差的缺点,提出一种利用电子系统中内建自测试控制器自身产生的方波作为模拟电路的测试矢量,并针对其输出响应进行分析的多维故障特征提取优化算法。通过模拟电路内建自测试故障字典法验证所提出方法的实用性和有效性。
电子系统经过内建自测试可测性设计之后,必需采取有效的可测性建模方法来评估其可测性改善的程度。本文在分析现有的可测性建模方法优缺点的基础上,提出电子系统的层次化的可测性建模方法,能够分别从系统的角度和基本元器件故障的角度出发,建立层次化的可测性建模分析体系,从而为可测性设计提供指导。
针对传统的测试优化算法易陷入局部最优的缺点,引入测试重要度函数,选择故障信息量大的测试,依据测试代价原则,提出基于测试重要度的Petri网的测试序列全局优化搜索算法。同时在测试信号与故障单元相关性模型的基础上,针对故障诊断问题,提出故障推理策略和推理规则,从而定位故障,达到故障诊断的目的。
最后,设计并开发基于内建自测试的典型电子系统。通过该系统验证本文所提出的内建自测试的理论和方法。实验研究结果证实了本文提出的内建自测试可测性设计的有效性和实用性,对电子系统内建自测试及其故障诊断策略具有借鉴意义。
In recent years, with the development of DSP, FPGA and other VLSI, they have been applied on national economics and national defense equipments extensively, which greatly increases the performance of electronic systems. However, at the same time they also brought a new question of testing and fault diagnosis. Traditional electronic system testing technology is plagued with many problems. The procedures are too complex, the test time is too long, the cost of testing is too high, and fault detection rate is too low. So it can not adapt to these devices as the core of electronic system test. The new theories and methods of test must be studied.
Based on the study of testable design and testable design theory, this paper has been proposed electronic system BIST (Built-in Self Test, BIST) solutions. The program generates and loads test vectors, extracts the fault features to complete the test by its own electronic system resources. Research work of the automatic test pattern generation method, fault feature extraction, test sequence optimization and other aspects were carried out in this paper to solve the long test time, low fault detection rate, high cost of testing problems.The results of this paper can be widely used in areas that require fast fault location, such as national defense military and industrial field and so on. Overall, the main research works of this paper are as follows:
First, the D-Tent(Digital Tent,D-Tent) and D-PL(Digital Piecewise Linear,D-PL) Chaotic model ATPG(Automatic Test Pattern Generation, ATPG) were proposed to solve the shortcomings of fault detection rate of BIST. After parameter optimization and characteristics analysis of chaos, the chaotic models were used in experimental research of standard test circuit. This mothod was compared with othe ATPG of BIST to get the results and conclusions.On this basis, chaotic time series testing vectors were applied to the BIST of analog circuit. Finally, we use the value of the correlation between input chaotic time series and output time series as a fault signature, the simulation results show the feasibility of the method.
A mothod was propose to solve the problem of analog circuit test pattern generation complexity of BIST, and overcome the shortcomings of the additional DAC circuits which increase the hardware area and the introduce testing error. This mothod uses square-wave as test pattern, which generated by its own. At the same time, the output response analysis of multi-dimensional fault feature extraction optimization was used. The mothod is introduced in analog BIST fault diction to prove the practicality and effectiveness.
In order to evaluate the testability improvement degree of electronic systems, uniform evaluation system and indicators are required. On the basis of analysis advantages and disadvantages of existing testability modeling mothd in this paper, the testability modeling method which suit to electronic systems hierarchical was studied. This mothod can establish a systematic testability and analysis modeling respectively from the system and the basic component failures to guide design for test.
To overcome the traditional test optimization easy to fall into local optimum, test critical function was introduced in the importance based Petri net global optimization test sequence search method. This mothod select the large amount of test information, according to the principles of testing costs. At the same time, based on correlation model, fault reasoning strategy and reasoning rules were studied to locate the fault and achieve the purpose of fault diagnosis.
At last, a typical electronic system platform based on BIST was developed, which combine with previous research and presentation of research results. The proposed theory and methodology on the BIST were verified through this platform. The experimental results confirmed that BIST testability design is feasible and practical. The design is a practical reference to electronic systems BIST and fault diagnosis strategy.
本文在研究电子系统可测试性设计和可测性理论的基础上,针对包含大规模集成电路的电子系统,提出内建自测试(Built-in Self Test,BIST)的解决方案。该方案通过电子系统自身资源生成测试矢量、加载测试激励、进行故障特征提取与优化,从而完成测试工作。本文从电子系统内建自测试的自动测试矢量生成、故障特征提取与优化、可测性建模和测试序列优化等方面开展研究工作,克服传统测试方法的不足,其研究成果可广泛应用于国防军事和工业现场的电子系统快速故障定位。
首先,针对目前电子系统内建自测试测试矢量生成方法存在故障检测率低的缺点,提出D-Tent(Digital Tent,D-Tent)和D-PL(Digital Piecewise Linear,D-PL)两种混沌自动测试矢量生成模型。将这两种模型经过参数优化选择和混沌特性分析后应用于标准测试电路进行实验研究,结果表明本文提出的自动测试矢量生成方法比其它方法的故障检测率更高。在此基础上,将混沌模型产生的时间序列测试矢量应用到模拟电路的内建自测试,利用输入混沌时间序列和输出时间序列的相关性作为故障特征,通过实验验证该方法的可行性。
为了降低电子系统内建自测试中模拟电路自动测试矢量生成的复杂性,并克服经过数模转换器而增加硬件电路面积和引入误差的缺点,提出一种利用电子系统中内建自测试控制器自身产生的方波作为模拟电路的测试矢量,并针对其输出响应进行分析的多维故障特征提取优化算法。通过模拟电路内建自测试故障字典法验证所提出方法的实用性和有效性。
电子系统经过内建自测试可测性设计之后,必需采取有效的可测性建模方法来评估其可测性改善的程度。本文在分析现有的可测性建模方法优缺点的基础上,提出电子系统的层次化的可测性建模方法,能够分别从系统的角度和基本元器件故障的角度出发,建立层次化的可测性建模分析体系,从而为可测性设计提供指导。
针对传统的测试优化算法易陷入局部最优的缺点,引入测试重要度函数,选择故障信息量大的测试,依据测试代价原则,提出基于测试重要度的Petri网的测试序列全局优化搜索算法。同时在测试信号与故障单元相关性模型的基础上,针对故障诊断问题,提出故障推理策略和推理规则,从而定位故障,达到故障诊断的目的。
最后,设计并开发基于内建自测试的典型电子系统。通过该系统验证本文所提出的内建自测试的理论和方法。实验研究结果证实了本文提出的内建自测试可测性设计的有效性和实用性,对电子系统内建自测试及其故障诊断策略具有借鉴意义。
In recent years, with the development of DSP, FPGA and other VLSI, they have been applied on national economics and national defense equipments extensively, which greatly increases the performance of electronic systems. However, at the same time they also brought a new question of testing and fault diagnosis. Traditional electronic system testing technology is plagued with many problems. The procedures are too complex, the test time is too long, the cost of testing is too high, and fault detection rate is too low. So it can not adapt to these devices as the core of electronic system test. The new theories and methods of test must be studied.
Based on the study of testable design and testable design theory, this paper has been proposed electronic system BIST (Built-in Self Test, BIST) solutions. The program generates and loads test vectors, extracts the fault features to complete the test by its own electronic system resources. Research work of the automatic test pattern generation method, fault feature extraction, test sequence optimization and other aspects were carried out in this paper to solve the long test time, low fault detection rate, high cost of testing problems.The results of this paper can be widely used in areas that require fast fault location, such as national defense military and industrial field and so on. Overall, the main research works of this paper are as follows:
First, the D-Tent(Digital Tent,D-Tent) and D-PL(Digital Piecewise Linear,D-PL) Chaotic model ATPG(Automatic Test Pattern Generation, ATPG) were proposed to solve the shortcomings of fault detection rate of BIST. After parameter optimization and characteristics analysis of chaos, the chaotic models were used in experimental research of standard test circuit. This mothod was compared with othe ATPG of BIST to get the results and conclusions.On this basis, chaotic time series testing vectors were applied to the BIST of analog circuit. Finally, we use the value of the correlation between input chaotic time series and output time series as a fault signature, the simulation results show the feasibility of the method.
A mothod was propose to solve the problem of analog circuit test pattern generation complexity of BIST, and overcome the shortcomings of the additional DAC circuits which increase the hardware area and the introduce testing error. This mothod uses square-wave as test pattern, which generated by its own. At the same time, the output response analysis of multi-dimensional fault feature extraction optimization was used. The mothod is introduced in analog BIST fault diction to prove the practicality and effectiveness.
In order to evaluate the testability improvement degree of electronic systems, uniform evaluation system and indicators are required. On the basis of analysis advantages and disadvantages of existing testability modeling mothd in this paper, the testability modeling method which suit to electronic systems hierarchical was studied. This mothod can establish a systematic testability and analysis modeling respectively from the system and the basic component failures to guide design for test.
To overcome the traditional test optimization easy to fall into local optimum, test critical function was introduced in the importance based Petri net global optimization test sequence search method. This mothod select the large amount of test information, according to the principles of testing costs. At the same time, based on correlation model, fault reasoning strategy and reasoning rules were studied to locate the fault and achieve the purpose of fault diagnosis.
At last, a typical electronic system platform based on BIST was developed, which combine with previous research and presentation of research results. The proposed theory and methodology on the BIST were verified through this platform. The experimental results confirmed that BIST testability design is feasible and practical. The design is a practical reference to electronic systems BIST and fault diagnosis strategy.
引文
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71 Li Lijuan, Wang Kang, An Zhiyong, et al. The Research on Fault Diagnosis Technique of Aerocamera Exposure Board. IEEE International Conference on Grey Systems and Intelligent Services, Najing: IEEE CONFERENCES 2007:1502-1504
72 Wang Dong, Chen Shengjian, Zhang Yan. An Optimized Algorithm Based on Information Entropy for System-Level Fault Isolation Strategy. The 8th International Conference on Electronic Measurement and Instruments, Xi'an: ICEMI, 2007:2325-2329
73 Simpson W R, Sheppard J W. Fault Isolation in an Integrated Diagnostic Environment. IEEE Circuits and Systems Society, 1993,10(1):52-66
74 Fang Tu, Pattipati K.R. Rollout Strategies for Sequential Fault Diagnosis Systems. IEEE Systems, Man, and Cybernetics Society, 2003,33(1):86-99
75 Kundakcioglu O E, Unluyurt T. Bottom-Up Construction of Minimum-Cost and/ or Trees for Sequential Fault Diagnosis. IEEE Transactions on Systems, Man and Cybernetics, Part A: Systems and Humans, 2007,37(5):621-629
76 Li Ty, Yorke J A. Period Three Implies Chaos. Amer Math.Monthly, 1975, 82(10):985-992
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78 Ruelle D. Ergodic Theory of Chaos and Strange Attractor. Rew. Math. Monthly, 1975, 82:985-992
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82 Stojanovski T, Kocarev. Chaos-Based Random Number Generators-Part I: Analysis. IEEE Transaction on circuits and systems-I:Fundamental theory and applications, 2001,48(3):281-288
83 Stojanovski T, Pihl J, Kocarev L. Chaos-Based Random Number Generators-Part II: Practical Realization. IEEE Transaction on circuits and systems-I: Fundamental theory and applications, 2001,48(3):382-385
84 Ozdemir K, Kilinc S, Ozoguz S. Random Number Generator Design Using Continuous-time Chaos. IEEE 16th Signal Processing, Communication and Applications Conference, Aydin: SIU, 2008:1-4
85 Katz O, Ramon D A, Wanger I A. A Robust Random Number Generator Based on a Differential Current-Mode Chaos. IEEE Transactions on very large scale integration (VLSI) systems, 2008,16(12):1677-1686
86 Buls J. Construction of Pseudo-random Sequences from Chaos. Control of Oscillations and Chaos, 2002 Proceedings. 2000 2nd International Conference, Petersburg:Univ. of Latvia, 2000(3):558-560
87 Jessa M. Combined Pseudochaotic Psudorandom Generator. International conference on signals and electronic systems, Krakow: ICSES, 2008:257-260
88 Tsubone T, SAITO T. On Basic Piecewise-Constant Systems. Proceedings of IEEE International Symposium on Circuits and Systems, Geneva: ISCAS, 2000(1):248-251
89杨华千,张伟,韦鹏程.基于分段线性映射与代数运算的混沌密码算法.电子学报. 2008,36(8):1490-1494
90 Addabbo T, Alioto M, Fort A, et, al. A Feedback Strategy to Improve the Entropy of a Chaso-Based Random Bit Generator. IEEE Transaction on circuits and Systems-I: Regular Papers, 2006, 53(2):326-337
91 Beiranmi A, Nejati H, Massoud Y. A Performance Metric for Discrete-time Chao-based truly Random Number Generators. 51th Midwest Symposium on Circuits and Systems, Knoxville: MWSCAS, 2008:133-136
92 Nitin Y, Vishwani D A. Sequential Circuit BIST Synthesis using Spetrum and Noise from ATPG Patterns. 17th Asian Test Symposium, 2008, 69-74
93 Chenyang P, Cheng K. Pseudorandom Testing for Mixed-Signal Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1997,16(10):1173-1185
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96吴樟福.基于信号量特征的模拟电路故障字典法研究.华中科技大学. 2008:10-19
97 Haini Q, Weisheng X, Youling Y. Design of Neural Network Output Layer in Fault Diagnosis of Analog Circuit. The 8th Interational Conference on Electronic Mearsurement and Instruments. 2007:3639-3642
98 Mehran A, Farzan A. A Modular Fault-Diagnostic System for Analog Elecronic Circuits Using Neural Networks With Wavelet Transform as a Preprocessor. IEEE Transactions on Instrumentation and Measurement, 2007, 56(5):1546-1554
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101 Dash P K, Samantaray S R, Panda G. Fault Classification and Section Identification of an Advance Serial-Compensated Transmission Line Using Support Vetctor Machine. IEEE Transaction on Power Delivery, 2007, 22(1):67-73
102 Anna W, Junfang L, Wenjin Y, et al. Algorithms Comparation of Feature Extraction and Multi-classification for Fault Diagnosis of Analog Circuit. Proceeding of the 2007 International Conference on Wavelte Analysis and Pattern Recognition, 2007: 566-572
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70 An Youlin, Huang Kaoli, Yang Suochang. Research of the Strategy for System Level Optimal Diagnosis Test Based on the Minimal Cut Sets of Fault Tree. The 8th International Conference on Electronic Measurement and Instruments, Xi'an: ICEMI, 2007:3339-3342
71 Li Lijuan, Wang Kang, An Zhiyong, et al. The Research on Fault Diagnosis Technique of Aerocamera Exposure Board. IEEE International Conference on Grey Systems and Intelligent Services, Najing: IEEE CONFERENCES 2007:1502-1504
72 Wang Dong, Chen Shengjian, Zhang Yan. An Optimized Algorithm Based on Information Entropy for System-Level Fault Isolation Strategy. The 8th International Conference on Electronic Measurement and Instruments, Xi'an: ICEMI, 2007:2325-2329
73 Simpson W R, Sheppard J W. Fault Isolation in an Integrated Diagnostic Environment. IEEE Circuits and Systems Society, 1993,10(1):52-66
74 Fang Tu, Pattipati K.R. Rollout Strategies for Sequential Fault Diagnosis Systems. IEEE Systems, Man, and Cybernetics Society, 2003,33(1):86-99
75 Kundakcioglu O E, Unluyurt T. Bottom-Up Construction of Minimum-Cost and/ or Trees for Sequential Fault Diagnosis. IEEE Transactions on Systems, Man and Cybernetics, Part A: Systems and Humans, 2007,37(5):621-629
76 Li Ty, Yorke J A. Period Three Implies Chaos. Amer Math.Monthly, 1975, 82(10):985-992
77陈敏,叶晓舟.混沌时间序列的判定方法研究.信息技术. 2008,32(6):23-25
78 Ruelle D. Ergodic Theory of Chaos and Strange Attractor. Rew. Math. Monthly, 1975, 82:985-992
79鄂加强,王春华,彭雨等.混沌特性时间序列线性变换理论方法及其应用.湖南大学学报(自然科学版). 2009,36(2):36-42
80 Pecora L M, Carroli T L. Synchronization in Chaotic Systems. Physical Review Letters, 1990,64(8): 821-824
81 Jessa M. The Period of Sequences Generated by Tent-Like Maps. IEEE Transactions on Circuits and Systems-I: Fundamental Theory and Applications, 2002,49(1):84-89
82 Stojanovski T, Kocarev. Chaos-Based Random Number Generators-Part I: Analysis. IEEE Transaction on circuits and systems-I:Fundamental theory and applications, 2001,48(3):281-288
83 Stojanovski T, Pihl J, Kocarev L. Chaos-Based Random Number Generators-Part II: Practical Realization. IEEE Transaction on circuits and systems-I: Fundamental theory and applications, 2001,48(3):382-385
84 Ozdemir K, Kilinc S, Ozoguz S. Random Number Generator Design Using Continuous-time Chaos. IEEE 16th Signal Processing, Communication and Applications Conference, Aydin: SIU, 2008:1-4
85 Katz O, Ramon D A, Wanger I A. A Robust Random Number Generator Based on a Differential Current-Mode Chaos. IEEE Transactions on very large scale integration (VLSI) systems, 2008,16(12):1677-1686
86 Buls J. Construction of Pseudo-random Sequences from Chaos. Control of Oscillations and Chaos, 2002 Proceedings. 2000 2nd International Conference, Petersburg:Univ. of Latvia, 2000(3):558-560
87 Jessa M. Combined Pseudochaotic Psudorandom Generator. International conference on signals and electronic systems, Krakow: ICSES, 2008:257-260
88 Tsubone T, SAITO T. On Basic Piecewise-Constant Systems. Proceedings of IEEE International Symposium on Circuits and Systems, Geneva: ISCAS, 2000(1):248-251
89杨华千,张伟,韦鹏程.基于分段线性映射与代数运算的混沌密码算法.电子学报. 2008,36(8):1490-1494
90 Addabbo T, Alioto M, Fort A, et, al. A Feedback Strategy to Improve the Entropy of a Chaso-Based Random Bit Generator. IEEE Transaction on circuits and Systems-I: Regular Papers, 2006, 53(2):326-337
91 Beiranmi A, Nejati H, Massoud Y. A Performance Metric for Discrete-time Chao-based truly Random Number Generators. 51th Midwest Symposium on Circuits and Systems, Knoxville: MWSCAS, 2008:133-136
92 Nitin Y, Vishwani D A. Sequential Circuit BIST Synthesis using Spetrum and Noise from ATPG Patterns. 17th Asian Test Symposium, 2008, 69-74
93 Chenyang P, Cheng K. Pseudorandom Testing for Mixed-Signal Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1997,16(10):1173-1185
94刘丹.模拟电路故障诊断中故障字典应用研究.华中科技大学. 2006:24-43
95王宏.模拟电路故障诊断故障字典法研究.西安电子科技大学. 2007:5-16
96吴樟福.基于信号量特征的模拟电路故障字典法研究.华中科技大学. 2008:10-19
97 Haini Q, Weisheng X, Youling Y. Design of Neural Network Output Layer in Fault Diagnosis of Analog Circuit. The 8th Interational Conference on Electronic Mearsurement and Instruments. 2007:3639-3642
98 Mehran A, Farzan A. A Modular Fault-Diagnostic System for Analog Elecronic Circuits Using Neural Networks With Wavelet Transform as a Preprocessor. IEEE Transactions on Instrumentation and Measurement, 2007, 56(5):1546-1554
99 Haiying Y, Guangju C, Sanbao S, et al. Research on Fault Diagnosis in Analog Circuit Based on Wavelet-Neural Network. Proceedings of the 6th Word Congress on Intelligent Control and Automation, Dalian, 2006:2659-2662
100 Mehran A, Farzan, A. Neural-Network Based Analog-Circuit Fault Diagnosis Using Wavelet Transform as Preprocessor. IEEE Transaction on Circuits and Systems—II:Analog and Digital Signal Processing, 2000, 47(2):151-156
101 Dash P K, Samantaray S R, Panda G. Fault Classification and Section Identification of an Advance Serial-Compensated Transmission Line Using Support Vetctor Machine. IEEE Transaction on Power Delivery, 2007, 22(1):67-73
102 Anna W, Junfang L, Wenjin Y, et al. Algorithms Comparation of Feature Extraction and Multi-classification for Fault Diagnosis of Analog Circuit. Proceeding of the 2007 International Conference on Wavelte Analysis and Pattern Recognition, 2007: 566-572
103 Deb S, Pattipati K R, Raghavan V, et al. Muti-Signal Flow Graphs: A Novel Approach for System Testability Analysis and Gault Diagnosis. IEEE AES Systems Magazine, 1995,10(5):14-25
104 Feng Lin, Markee J, Rado B. Design and Test of Mixed Sgnal Circuits: A Discrete-Event Approach. Proceddings of the 32nd Conference on Decision and Control, San Antonio: CDC, 1993:217-222
105 Feng Lin, Lin T W. Diagnosability of Discrete Event Systems and Its Applications to Circuit Testing. Proceedings of the 36th Midwest Symposium on Circuits and Systems, Detroit: MWSCAS, 1993,1(8):344-347
106李夏.基于Petri网的故障诊断技术研究及其在液压系统中的应用.上海:同济大学.2006:18-27
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