神经元MOS及其应用电路的研究
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摘要
随着集成电路的发展及其集成度的提高，传统的基于单一晶体管功能的硅集成电路，出现了很多困难的、急待解决的问题，而神经元MOS晶体管(Neuron MOSFET，简写为neuMOS或vMOS)作为一种具有强大功能的单元晶体管，为解决集成电路中晶体管数目及互连线增多带来的问题提供了一种有效的途径。本文在对器件的特性进行分析的基础上，建立了较精确的器件HSPICE模型，并对器件的应用电路进行了深入研究。
对神经元MOS的特性进行了较系统的分析，提出了浮栅增益因子存在饱和值的观点，分析出浮栅增益因子受场寄生电容的影响从而解释了浮栅增益因子出现饱和值的现象；从电路速度和功耗上对神经元MOS电路和普通CMOS电路进行了比较，讨论了器件输入端子数主要受电路的计算精度、电路速度和电源电压等因素的限制，为神经元MOS电路的设计提供了理论指导。
建立了神经元MOS的HSPICE模型，在对浮栅电势建模时考虑了场寄生电容对浮栅电势的影响，并对模型进行了验证，为神经元MOS电路的设计提供了更精确的模拟手段。
用神经元MOS实现了奇偶校验码系统。设计了8个数据位的奇校验码编码和校验电路；并对所设计的电路进行了HSPICE仿真，结果表明所设计的电路功能正确，跟传统的CMOS电路相比晶体管数目从近五百个减少到
西安理工大学博士学位论文
三十几个。
开拓了神经元MOS在数字PwM发生器中的应用，大幅度减少了电路
中器件的数目，并深入分析了神经元MOS源极跟随器的输出特性，对MOS
管的阂值从电压偏差和静态功耗两方面进行了优化设计，得出C一MOS源
极跟随器中PMOS和NMOS应取微耗尽型的结论，为C一vMOS源极跟随器
在模拟电路中的应用提供了理论指导。
提出了基于神经元MOS的CDMA数模混合型匹配滤波器结构，使得
匹配滤波器的结构得到简化，并制作了它的测试电路芯片，在匹配单元电路
设计过程中，提出了提高电路运算精度的闺值取消单元电路，实现了电路的
高精度运算。
关键词:神经元MOS，集成电路，SPICE模型，PWM发生器，匹配滤波器
With the development of the integrated circuit (IC) and the improvement of its integration density, many problems have occurred for the conventional silicon IC based on single transistor function. As a functional transistor, neuron-MOS provides us an effective way to settle the problems resulted from the increase of transistor number and the interactive wires. In this paper, based on analysis of the device's characteristics, the accurate SPICE model for this device is presented and the application circuits are thoroughly researched.The characteristics of neuron-MOS are analyzed systemically which provide the theoretic guide for the design of neuron-MOS circuit. The viewpoint that because of the field parasitical capacitance between the floating gate and the bulk the floating gate gain factor v exists a maximum value is presented. The compare of the speed and power loss performances between the neuron-MOS and ordinary CMOS is carried out. The factors that limit the number of neuron-MOS input gates are discussed from the calculation precision, circuit speed and the power voltage.The SPICE model for neuron-MOS is presented which provides a more accurate method to simulate neuron-MOS circuit. When modeling the floating gate potential, the effect of the parasitical field capacitance to the floating gate potential is considered, and the model is verified by the simulation results and the measured results.Parity check system based on neuron-MOS is designed. A 8-bit odd coding circuit and verification circuit are designed and simulated. The results show that neuron-MOS circuits decrease the number of transistors from 500 transistors to 38 transistors.The application of neuron-MOS in digital PWM generator is developed.
The number of transistors is decreased dramatically. The output characteristics of the C-neuMOS source follower are analyzed thoroughly, and the threshold of neuron-MOS is optimized between the output voltage offset and the power loss, which provide theoretic guide for the design of neuron-MOS analog circuit.A novel CDMA matched filter structure is presented. Compared to the conventional structure, the number of circuit elements is decreased greatly for the same function. The test chip was fabricated and the measurement result shows that the system structure is feasible and effective. In the design of the matched cell, a novel neuMOS source follower circuit with high precision is presented to eliminate the threshold loss of source follower.
对神经元MOS的特性进行了较系统的分析，提出了浮栅增益因子存在饱和值的观点，分析出浮栅增益因子受场寄生电容的影响从而解释了浮栅增益因子出现饱和值的现象；从电路速度和功耗上对神经元MOS电路和普通CMOS电路进行了比较，讨论了器件输入端子数主要受电路的计算精度、电路速度和电源电压等因素的限制，为神经元MOS电路的设计提供了理论指导。
建立了神经元MOS的HSPICE模型，在对浮栅电势建模时考虑了场寄生电容对浮栅电势的影响，并对模型进行了验证，为神经元MOS电路的设计提供了更精确的模拟手段。
用神经元MOS实现了奇偶校验码系统。设计了8个数据位的奇校验码编码和校验电路；并对所设计的电路进行了HSPICE仿真，结果表明所设计的电路功能正确，跟传统的CMOS电路相比晶体管数目从近五百个减少到
西安理工大学博士学位论文
三十几个。
开拓了神经元MOS在数字PwM发生器中的应用，大幅度减少了电路
中器件的数目，并深入分析了神经元MOS源极跟随器的输出特性，对MOS
管的阂值从电压偏差和静态功耗两方面进行了优化设计，得出C一MOS源
极跟随器中PMOS和NMOS应取微耗尽型的结论，为C一vMOS源极跟随器
在模拟电路中的应用提供了理论指导。
提出了基于神经元MOS的CDMA数模混合型匹配滤波器结构，使得
匹配滤波器的结构得到简化，并制作了它的测试电路芯片，在匹配单元电路
设计过程中，提出了提高电路运算精度的闺值取消单元电路，实现了电路的
高精度运算。
关键词:神经元MOS，集成电路，SPICE模型，PWM发生器，匹配滤波器
With the development of the integrated circuit (IC) and the improvement of its integration density, many problems have occurred for the conventional silicon IC based on single transistor function. As a functional transistor, neuron-MOS provides us an effective way to settle the problems resulted from the increase of transistor number and the interactive wires. In this paper, based on analysis of the device's characteristics, the accurate SPICE model for this device is presented and the application circuits are thoroughly researched.The characteristics of neuron-MOS are analyzed systemically which provide the theoretic guide for the design of neuron-MOS circuit. The viewpoint that because of the field parasitical capacitance between the floating gate and the bulk the floating gate gain factor v exists a maximum value is presented. The compare of the speed and power loss performances between the neuron-MOS and ordinary CMOS is carried out. The factors that limit the number of neuron-MOS input gates are discussed from the calculation precision, circuit speed and the power voltage.The SPICE model for neuron-MOS is presented which provides a more accurate method to simulate neuron-MOS circuit. When modeling the floating gate potential, the effect of the parasitical field capacitance to the floating gate potential is considered, and the model is verified by the simulation results and the measured results.Parity check system based on neuron-MOS is designed. A 8-bit odd coding circuit and verification circuit are designed and simulated. The results show that neuron-MOS circuits decrease the number of transistors from 500 transistors to 38 transistors.The application of neuron-MOS in digital PWM generator is developed.
The number of transistors is decreased dramatically. The output characteristics of the C-neuMOS source follower are analyzed thoroughly, and the threshold of neuron-MOS is optimized between the output voltage offset and the power loss, which provide theoretic guide for the design of neuron-MOS analog circuit.A novel CDMA matched filter structure is presented. Compared to the conventional structure, the number of circuit elements is decreased greatly for the same function. The test chip was fabricated and the measurement result shows that the system structure is feasible and effective. In the design of the matched cell, a novel neuMOS source follower circuit with high precision is presented to eliminate the threshold loss of source follower.
引文
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