神经元MOS管在神经网络中的应用研究
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摘要
本文主要介绍了神经元MOS管电路和人工神经网络的研究现状,结合人工神经网络的发展方向,探讨了神经元MOS在神经元网络中的应用可能性及其一些特有的优点。
分析了神经元MOS管的原理、结构以及Hspice仿真模型,并介绍和仿真了神经元MOS反相器和源极跟随器两种基本电路,它们是构成其它复杂电路的基础。
介绍了人工神经网络的发展进程,比较了用软件实现和硬件实现人工神经网络两种方法,分析了用硬件实现的必要性。
重点介绍了感知器、Hopfield神经网络以及Hamming神经网络。并将神经元MOS应用到了感知器电路中,利用单层感知器原理设计了与门和或门电路,利用多层感知器原理设计了异或门电路。将神经元MOS管应用到Hopfield神经网络A/D转换器电路中和联想记忆网络中,所设计的电路,结构简单,仿真正确。并根据Hopfield神经网络A/D转换器和感知器的原理,用神经元MOS管设计了二四值编译码器电路。将神经元MOS应用在Hamming神经网络电路中,设计了模板匹配电路和竞争全胜电路,并将系统应用在了数字字符识别中。
本文的研究工作,探讨了神经元MOS管在神经网络中的应用前景。从本文的研究内容和仿真结果看,神经元MOS管的结构与神经网络有着很多相似之处。而且具有结构简单,功耗低等特点,非常适合在神经网络电路中应用。
This paper analyzes the status and trends of the development of neuron-MOS circuits and Artificial Neural Network. The possibility and some unique advantages of the neuron-MOS in the network application are discussed,which meet the Artificial Neural Network's development.
The principle、structure and the Hspice simulation model are also analyzed.The paper also introduces the neuron-MOS inverter and source follower circuit.They are the basic circuits.which the other complex circuits based on.And a simulation on Hspice is made.
The paper also introduces the development of Artificial Neural Network,compares the ways of realizing the neural network,one is by software,and the other is by hardware. And analyzes the necessity for hardware implementation.
The paper mainly introduces the Perceptron、Hopfield Neural Network and Hamming Neural Network.The neuron-MOS is applied to the Perceptron circuit. And the AND gate circuit and OR gate circuit is designed by the principle of the single layer Perceptron,which the Exclusive OR gate is designed by the principle of multilayer Perceptron.The neuron-MOS is applied to the Hopfield Neural Network A/D converter circuit and Associative Memory Network circuit.The structure of the designed circuits is simple,and the simulation is right.And by the principle above,four-two value decoder circuit and two-four value encoder circuit are designed with neuron-MOS.In the last,the neuron-MOS is applied in the Hamming Neural Network circuit.The Template Matching circuit and WTA circuit are designed,which are applied in the digital character recognition.
This paper discusses the application prospect of neuron-MOS in the Artificial Neural Network.From the research content and the result of simulation,the neuron-MOS and Neural Network have many similarities.But also has the advantages of simple structure,low power consumption,is very suitable for using in the Artificial Neural Network circuit.
分析了神经元MOS管的原理、结构以及Hspice仿真模型,并介绍和仿真了神经元MOS反相器和源极跟随器两种基本电路,它们是构成其它复杂电路的基础。
介绍了人工神经网络的发展进程,比较了用软件实现和硬件实现人工神经网络两种方法,分析了用硬件实现的必要性。
重点介绍了感知器、Hopfield神经网络以及Hamming神经网络。并将神经元MOS应用到了感知器电路中,利用单层感知器原理设计了与门和或门电路,利用多层感知器原理设计了异或门电路。将神经元MOS管应用到Hopfield神经网络A/D转换器电路中和联想记忆网络中,所设计的电路,结构简单,仿真正确。并根据Hopfield神经网络A/D转换器和感知器的原理,用神经元MOS管设计了二四值编译码器电路。将神经元MOS应用在Hamming神经网络电路中,设计了模板匹配电路和竞争全胜电路,并将系统应用在了数字字符识别中。
本文的研究工作,探讨了神经元MOS管在神经网络中的应用前景。从本文的研究内容和仿真结果看,神经元MOS管的结构与神经网络有着很多相似之处。而且具有结构简单,功耗低等特点,非常适合在神经网络电路中应用。
This paper analyzes the status and trends of the development of neuron-MOS circuits and Artificial Neural Network. The possibility and some unique advantages of the neuron-MOS in the network application are discussed,which meet the Artificial Neural Network's development.
The principle、structure and the Hspice simulation model are also analyzed.The paper also introduces the neuron-MOS inverter and source follower circuit.They are the basic circuits.which the other complex circuits based on.And a simulation on Hspice is made.
The paper also introduces the development of Artificial Neural Network,compares the ways of realizing the neural network,one is by software,and the other is by hardware. And analyzes the necessity for hardware implementation.
The paper mainly introduces the Perceptron、Hopfield Neural Network and Hamming Neural Network.The neuron-MOS is applied to the Perceptron circuit. And the AND gate circuit and OR gate circuit is designed by the principle of the single layer Perceptron,which the Exclusive OR gate is designed by the principle of multilayer Perceptron.The neuron-MOS is applied to the Hopfield Neural Network A/D converter circuit and Associative Memory Network circuit.The structure of the designed circuits is simple,and the simulation is right.And by the principle above,four-two value decoder circuit and two-four value encoder circuit are designed with neuron-MOS.In the last,the neuron-MOS is applied in the Hamming Neural Network circuit.The Template Matching circuit and WTA circuit are designed,which are applied in the digital character recognition.
This paper discusses the application prospect of neuron-MOS in the Artificial Neural Network.From the research content and the result of simulation,the neuron-MOS and Neural Network have many similarities.But also has the advantages of simple structure,low power consumption,is very suitable for using in the Artificial Neural Network circuit.
引文
[1]Shibata T, Ohmi T. A functional MOS transistor featuring gate-level weighted sum and threshold operations[J]. IEEE Transactions on Electron Devices,1992.39(6):1444-1455.
[2]Ishikawa Y, Fukai S. A neuron MOS variable logic circuit with the simplified circuit structure[C]. Proceedings of IEEE Asia-Pacific Confernce on Advanced System Integrated Circuits,2004:436-437.
[3]Ishii H, Shibata T, Kosaka H. Hardware-backpropagation learning of neuron MOS neural nerworks[C]. International Electron Devices Meeting,1992:435-438.
[4]Shibata T, Kosaka H,Ishii H. A neuron-MOS neural network using self-learning-compatible synapse circuits[J]. IEEE Journal of Solid-State Circuits,1995,30(8):913-922.
[5]Kosaka H,Shibata T,Ishii H. An excellent weight-updating-linearity synapse memory cell for self-learning neuron MOS neural networks[C]. International Electron Devices Meeting.Washington,DC,1993:623-626.
[6]Shibata T.Ohmi T. Neuron MOS binary-logic integrated circuits.Ⅰ.Design fundamentals and soft-hardware-logic circuit implementation[J]. IEEE Transactions on Electron Devices,1993,40(3):570-576.
[7]Shibata T,Ohmi T. Neuron MOS binary-logic integrated circuits.Ⅱ.Simplifying techniques of circuit configuration and their practical applications [J] IEEE Transactions on Electron Devices,1993,40(3):570-576.
[8]Au R, Yamashita T,Shibata T. Neuron-MOS multiple-valued memory technology for intelligent data processing[C]. Proceedings of International Solid-State Circuits Conference,San Francisco,1994:270-271.
[9]Fukuhara M,Yoshida M. Proposal of Hamming distance search CAM using neuron MOS transistors[C]. Proceedings of International Symposium on intelligent Signal Processing and Communication Systems,2004:740-745.
[10]Fukuhara M,Yoshida M. Power consumption of a Hamming distance search CAM using neuron MOS transistors[C]. Proceedings of International Symposium on Circuits and Systems,2006:4-8.
[11]Ning-Mei Yu,Shibata T,Ohmi T. A real-time center-of-mass tracker circuit implemented by neuron MOS technology [J]. IEEE Transactions on Circuits and Systems II:Analog and Digital Signal Processing,1998,45(4):495-503.
[12]Yamasaki T,Nakayama T,Shibata T. A low-power and compact CDMA matched filter based on switched-current technology[J]. IEEE Journal of Solid-State Circuits,2005,40(4):926-932.
[13]Yamasaki T,Shibata T. A low-power Floating-Gate-Mos-Based CDMA matched filter featuring coupling capacitor disconnection[J]. IEEE Journal of Solid-State Circuits,2007,42(2):422-430.
[14]Okada A,Shibata T. A neuron-MOS parallel associator for high-speed CDMA matched filter[C]. Processings of International Symposium on Circuit and Systems,1999:382-395.
[15]Shibata T,Konda M,Yamashita Y. Neuron-MOS-based association hardware for real-time event recognition[C]. Proceedings of Fifth International Conference on Microelectronics for Neural Networks,Lausanne,1996:94-101.
[16]Yamashita T,Shibata T,Ohmi T. Neuron MOS winner-take-all circuit and its application to associative memory. Proceedings of International Solid-State Circuits Conference,San Francisco,1993:236-237,294.
[17]Weber W,Prange S,Thewes R. A neuron MOS transistor-based multiplier cell[C]. International Electron Devices Meeting,Washington,1995:555-558.
[18]Weber W,Prange S,Thewes P. On the application of the Neuron MOS transistor Principle for modern VLSI design[J]. IEEE Transactions on Electron Devices,1996,43(10):1700-1708.
[19]Sung Il Han,Young Hee Choi,Heung Soo Kim. A 4 digit CMOS quaternary to analog converter with current switch and neuron MOS down-literal circuit[C]. Proceedings of 31st IEEE International Symposium on Multiple-Valued Logic, Warsaw,2001:67-71.
[20]Soo Jin Peak,Byoung Hee Yoon,Kwang Sub Yoon. Design of quaternary logic gate using double pass-trasistor logic with neuron MOS down literal circuit[C]. Proceedings of 34th International Symposium on Multiple-Valued Logic,2004:198-203.
[21]Dong-Chual Kang, Chang-Il Kim,Han-Kil Park. Design of an 8-bit neuron MOSFET A-D converter using subranging method[C]. Proceedings of International Conference on VLSI and CAD,Seoul,1999:533-536.
[22]Rantala A,Franssila S,Kaski K. Improved neuron MOS-transistor structures for integrated neural network circuits[J]. IEEE Proceedings Circuits,Devices and Systems,2001,148(1):25-34.
[23]Rantala A.Kuivalainen P,Aberg M. An 8-bit and a 10-bit low power high-speed neuron MOS digital-to-analog converter in 0.04mm2[C]. Proceedings of the 25th European Solid-State Circuits Conference,1999:310-313.
[24]Berg Y,Lande T.S,Naess O. Ultra-low-voltage floating-gate transconductance amplifiers[J]. IEEE Transactions on Circuits and Systems:Analog and Digital Signal Processing,2001,48(1):37-44.
[25]Jensen R, Berg Y. Serial semi floating gate MOS D/A converter with configurable resolution [C]. Proceedings of 10th Conference on Convergent Technologies for the Asia Pacific Region,2004:254-257.
[26]Berg Y, Wisland D.T, Lande T.S. Ultra low-voltage/low-power digital floating-gate circuits[J]. IEEE Transactions on Circuits and Systems:Analog and Digital Signal Processing,1999,46(7):930-936.
[27]Lomsdalen J.G, Jensen R, Berg Y. Multiple valued counter[C]. Design and Diagnostics of Electronic Circuits and systems,2006:245-247.
[28]杨媛,高勇,余宁梅.神经元MOS的特性分析[J].西安理工大学学报,2004,20(1)：49-53.
[29]杨媛,高勇,余宁梅,张如亮,胡挺.钟控神经元MOS晶体管的改进HSPICE宏模型[J].固体电子学研究与进展,2007,3(27)：301-304.
[30]谭诤,高勇,杨媛.一种基于神经元MOS的直扩匹配滤波器新结构[J].电子器件,2005,28(2)：362-365.
[31]陈静瑾,马文龙,余宁梅.新型神经元MOS多数表决电路的研究[J].电子器件,2004,27(2)：217-219.
[32]杨媛,高勇,余宁梅,刘梦新.一种新型的高精度神经元MOS源极跟随单元电路[J].半导体学报,2004,25(9)：1074-1078.
[33]王明宇,汤玉生,管慧.电阻耦合型神经MOS晶体管及其差分四象限模拟乘法器[J].固体学电子学研究与进展,2002,22(2)：158-163.
[34]曹亚明,汤玉生.一种新型的开关共点耦合神经MOS晶体管[J].固体电子学研究与进展,2003,23(1)：23-26.
[35]曹亚明,汤玉生.钟控神经MOS晶体管的建模及其电路仿真[J].固体电子学研究与进展,2003,23(1)：89-95.
[36]杭国强.基于多值逻辑方法的二值神经元MOS电路设计技术[J].半导体学 报,2006,27(7)：1316-1320.
[37]杭国强,聂莹莹,金心宇.采用多输入浮栅MOS四值编译码电路设计[J].固体电子学研究与进展,2007,27(3)：421-426.
[38]戴静,陆金刚,汪鹏君.基于神经元MOS管的多值D/A、A/D转换器设计[J].科技通报,2007,23(5)：693-697.
[39]周伟雄,勒东明,李志坚.模拟神经元电路实现研究现状与进展[J].固体电子学研究与进展,2002,22(3)：269-279.
[40]任勇涌,庞维珍.BP神经网络的硬件实现[J].山东工程学院学报,1996,10(4)：34-39.
[41]刘祖润,张志飞,邹阿金.Chebyshev神经网络设计[J].湘潭大学自然科学学报,2000：32-34.
[42]Talaska T, Wojtyna R, Dbugosz R, Iniewskt K. Implementation of the conscience mechanism for kohonen's neural network in CMOS 0.18um technology[C]. Proceedings of International conference on Mixed design of integrated Circuits and Systems,2006:310-315.
[43]Al-Zeftawi N,Abd El-Fattah M. CMOS Mixed Digital analog reconfigurable Neural Network with gaussian synapses[C]. Proceedings of 10th Mediterranean Electrotechnical Conference,2000:1198-1201.
[44]Wells B,Anindya B. Forgetful logic circuits for Pulse-Mode Neural Nerworks[C].Proceedings of international Joint Conference on Neural Networks,2005:616-621.
[45]Abo El-soud A, AbdelRassoul A. Low-Power CMOS circuits for analog VLSI programmable Neural Networks[C]. IEEE Transactions on Electronic and Communications,2002:14-17.
[46]Hopfield J.J. Neurons with graded response have collective computational like those of two-state neurons[C]. Proceedings of Natl.Acc.Sci.USA,1984:3088-3092.
[47]Tank D.W., Hopfield J.J. Simple neural optimization nerwork:an A/D converter signal decision circuit and a linear programming circuit[J]. IEEE Transactions on Circuits and Systems,May.1986:33-38.
[48]Chang P.R,Wang B.C, Gong H.M. A triangular connection hopfield neural network approach to Analog-to-Digital conversion[J]. IEEE Transactions on Instrumentation and Measurement,1994:882-888.
[49]Thoidis IM,Sounris D,Karafyllidis I. The design of low-power multiple-valued logic encoder and decoder circuits [C]. Proceedings of the IEEE International Conference on Electronics,Circuits and Systems,1999:1623-1626.
[50]Philippe JM,Pillement S,Sentieys O. A low-power and high-speed quaternary interconnection link using efficient converter[C]. Proceedings of the IEEE International Symposium on Circuits and Systems,2005:4689-4692.
[51]Shanbhag NR,Nagchoudhuri D,Siferd R.E. Quaternary logic circuits in 2-um CMOS technology[J]. IEEE Journal of Solid-state Circuits,1990:790-799.
[52]李斌桥,李志坚,石秉学.一种模拟集成电路Hamming神经网络及其应用.半导体学报,1996.03.
[53]姚立真.通用电路模拟技术及软件应用SPICE和PSPICE电子工业出版社,1994.
[54]高隽.人工神经网络原理及仿真实例.机械工业出版社,2003.
[55]闻新,周露,王丹力,熊晓英.MATLAB神经网络应用设计.科学出版社,2001.
[2]Ishikawa Y, Fukai S. A neuron MOS variable logic circuit with the simplified circuit structure[C]. Proceedings of IEEE Asia-Pacific Confernce on Advanced System Integrated Circuits,2004:436-437.
[3]Ishii H, Shibata T, Kosaka H. Hardware-backpropagation learning of neuron MOS neural nerworks[C]. International Electron Devices Meeting,1992:435-438.
[4]Shibata T, Kosaka H,Ishii H. A neuron-MOS neural network using self-learning-compatible synapse circuits[J]. IEEE Journal of Solid-State Circuits,1995,30(8):913-922.
[5]Kosaka H,Shibata T,Ishii H. An excellent weight-updating-linearity synapse memory cell for self-learning neuron MOS neural networks[C]. International Electron Devices Meeting.Washington,DC,1993:623-626.
[6]Shibata T.Ohmi T. Neuron MOS binary-logic integrated circuits.Ⅰ.Design fundamentals and soft-hardware-logic circuit implementation[J]. IEEE Transactions on Electron Devices,1993,40(3):570-576.
[7]Shibata T,Ohmi T. Neuron MOS binary-logic integrated circuits.Ⅱ.Simplifying techniques of circuit configuration and their practical applications [J] IEEE Transactions on Electron Devices,1993,40(3):570-576.
[8]Au R, Yamashita T,Shibata T. Neuron-MOS multiple-valued memory technology for intelligent data processing[C]. Proceedings of International Solid-State Circuits Conference,San Francisco,1994:270-271.
[9]Fukuhara M,Yoshida M. Proposal of Hamming distance search CAM using neuron MOS transistors[C]. Proceedings of International Symposium on intelligent Signal Processing and Communication Systems,2004:740-745.
[10]Fukuhara M,Yoshida M. Power consumption of a Hamming distance search CAM using neuron MOS transistors[C]. Proceedings of International Symposium on Circuits and Systems,2006:4-8.
[11]Ning-Mei Yu,Shibata T,Ohmi T. A real-time center-of-mass tracker circuit implemented by neuron MOS technology [J]. IEEE Transactions on Circuits and Systems II:Analog and Digital Signal Processing,1998,45(4):495-503.
[12]Yamasaki T,Nakayama T,Shibata T. A low-power and compact CDMA matched filter based on switched-current technology[J]. IEEE Journal of Solid-State Circuits,2005,40(4):926-932.
[13]Yamasaki T,Shibata T. A low-power Floating-Gate-Mos-Based CDMA matched filter featuring coupling capacitor disconnection[J]. IEEE Journal of Solid-State Circuits,2007,42(2):422-430.
[14]Okada A,Shibata T. A neuron-MOS parallel associator for high-speed CDMA matched filter[C]. Processings of International Symposium on Circuit and Systems,1999:382-395.
[15]Shibata T,Konda M,Yamashita Y. Neuron-MOS-based association hardware for real-time event recognition[C]. Proceedings of Fifth International Conference on Microelectronics for Neural Networks,Lausanne,1996:94-101.
[16]Yamashita T,Shibata T,Ohmi T. Neuron MOS winner-take-all circuit and its application to associative memory. Proceedings of International Solid-State Circuits Conference,San Francisco,1993:236-237,294.
[17]Weber W,Prange S,Thewes R. A neuron MOS transistor-based multiplier cell[C]. International Electron Devices Meeting,Washington,1995:555-558.
[18]Weber W,Prange S,Thewes P. On the application of the Neuron MOS transistor Principle for modern VLSI design[J]. IEEE Transactions on Electron Devices,1996,43(10):1700-1708.
[19]Sung Il Han,Young Hee Choi,Heung Soo Kim. A 4 digit CMOS quaternary to analog converter with current switch and neuron MOS down-literal circuit[C]. Proceedings of 31st IEEE International Symposium on Multiple-Valued Logic, Warsaw,2001:67-71.
[20]Soo Jin Peak,Byoung Hee Yoon,Kwang Sub Yoon. Design of quaternary logic gate using double pass-trasistor logic with neuron MOS down literal circuit[C]. Proceedings of 34th International Symposium on Multiple-Valued Logic,2004:198-203.
[21]Dong-Chual Kang, Chang-Il Kim,Han-Kil Park. Design of an 8-bit neuron MOSFET A-D converter using subranging method[C]. Proceedings of International Conference on VLSI and CAD,Seoul,1999:533-536.
[22]Rantala A,Franssila S,Kaski K. Improved neuron MOS-transistor structures for integrated neural network circuits[J]. IEEE Proceedings Circuits,Devices and Systems,2001,148(1):25-34.
[23]Rantala A.Kuivalainen P,Aberg M. An 8-bit and a 10-bit low power high-speed neuron MOS digital-to-analog converter in 0.04mm2[C]. Proceedings of the 25th European Solid-State Circuits Conference,1999:310-313.
[24]Berg Y,Lande T.S,Naess O. Ultra-low-voltage floating-gate transconductance amplifiers[J]. IEEE Transactions on Circuits and Systems:Analog and Digital Signal Processing,2001,48(1):37-44.
[25]Jensen R, Berg Y. Serial semi floating gate MOS D/A converter with configurable resolution [C]. Proceedings of 10th Conference on Convergent Technologies for the Asia Pacific Region,2004:254-257.
[26]Berg Y, Wisland D.T, Lande T.S. Ultra low-voltage/low-power digital floating-gate circuits[J]. IEEE Transactions on Circuits and Systems:Analog and Digital Signal Processing,1999,46(7):930-936.
[27]Lomsdalen J.G, Jensen R, Berg Y. Multiple valued counter[C]. Design and Diagnostics of Electronic Circuits and systems,2006:245-247.
[28]杨媛,高勇,余宁梅.神经元MOS的特性分析[J].西安理工大学学报,2004,20(1)：49-53.
[29]杨媛,高勇,余宁梅,张如亮,胡挺.钟控神经元MOS晶体管的改进HSPICE宏模型[J].固体电子学研究与进展,2007,3(27)：301-304.
[30]谭诤,高勇,杨媛.一种基于神经元MOS的直扩匹配滤波器新结构[J].电子器件,2005,28(2)：362-365.
[31]陈静瑾,马文龙,余宁梅.新型神经元MOS多数表决电路的研究[J].电子器件,2004,27(2)：217-219.
[32]杨媛,高勇,余宁梅,刘梦新.一种新型的高精度神经元MOS源极跟随单元电路[J].半导体学报,2004,25(9)：1074-1078.
[33]王明宇,汤玉生,管慧.电阻耦合型神经MOS晶体管及其差分四象限模拟乘法器[J].固体学电子学研究与进展,2002,22(2)：158-163.
[34]曹亚明,汤玉生.一种新型的开关共点耦合神经MOS晶体管[J].固体电子学研究与进展,2003,23(1)：23-26.
[35]曹亚明,汤玉生.钟控神经MOS晶体管的建模及其电路仿真[J].固体电子学研究与进展,2003,23(1)：89-95.
[36]杭国强.基于多值逻辑方法的二值神经元MOS电路设计技术[J].半导体学 报,2006,27(7)：1316-1320.
[37]杭国强,聂莹莹,金心宇.采用多输入浮栅MOS四值编译码电路设计[J].固体电子学研究与进展,2007,27(3)：421-426.
[38]戴静,陆金刚,汪鹏君.基于神经元MOS管的多值D/A、A/D转换器设计[J].科技通报,2007,23(5)：693-697.
[39]周伟雄,勒东明,李志坚.模拟神经元电路实现研究现状与进展[J].固体电子学研究与进展,2002,22(3)：269-279.
[40]任勇涌,庞维珍.BP神经网络的硬件实现[J].山东工程学院学报,1996,10(4)：34-39.
[41]刘祖润,张志飞,邹阿金.Chebyshev神经网络设计[J].湘潭大学自然科学学报,2000：32-34.
[42]Talaska T, Wojtyna R, Dbugosz R, Iniewskt K. Implementation of the conscience mechanism for kohonen's neural network in CMOS 0.18um technology[C]. Proceedings of International conference on Mixed design of integrated Circuits and Systems,2006:310-315.
[43]Al-Zeftawi N,Abd El-Fattah M. CMOS Mixed Digital analog reconfigurable Neural Network with gaussian synapses[C]. Proceedings of 10th Mediterranean Electrotechnical Conference,2000:1198-1201.
[44]Wells B,Anindya B. Forgetful logic circuits for Pulse-Mode Neural Nerworks[C].Proceedings of international Joint Conference on Neural Networks,2005:616-621.
[45]Abo El-soud A, AbdelRassoul A. Low-Power CMOS circuits for analog VLSI programmable Neural Networks[C]. IEEE Transactions on Electronic and Communications,2002:14-17.
[46]Hopfield J.J. Neurons with graded response have collective computational like those of two-state neurons[C]. Proceedings of Natl.Acc.Sci.USA,1984:3088-3092.
[47]Tank D.W., Hopfield J.J. Simple neural optimization nerwork:an A/D converter signal decision circuit and a linear programming circuit[J]. IEEE Transactions on Circuits and Systems,May.1986:33-38.
[48]Chang P.R,Wang B.C, Gong H.M. A triangular connection hopfield neural network approach to Analog-to-Digital conversion[J]. IEEE Transactions on Instrumentation and Measurement,1994:882-888.
[49]Thoidis IM,Sounris D,Karafyllidis I. The design of low-power multiple-valued logic encoder and decoder circuits [C]. Proceedings of the IEEE International Conference on Electronics,Circuits and Systems,1999:1623-1626.
[50]Philippe JM,Pillement S,Sentieys O. A low-power and high-speed quaternary interconnection link using efficient converter[C]. Proceedings of the IEEE International Symposium on Circuits and Systems,2005:4689-4692.
[51]Shanbhag NR,Nagchoudhuri D,Siferd R.E. Quaternary logic circuits in 2-um CMOS technology[J]. IEEE Journal of Solid-state Circuits,1990:790-799.
[52]李斌桥,李志坚,石秉学.一种模拟集成电路Hamming神经网络及其应用.半导体学报,1996.03.
[53]姚立真.通用电路模拟技术及软件应用SPICE和PSPICE电子工业出版社,1994.
[54]高隽.人工神经网络原理及仿真实例.机械工业出版社,2003.
[55]闻新,周露,王丹力,熊晓英.MATLAB神经网络应用设计.科学出版社,2001.