神经元MOS电路在通信系统中的应用研究
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摘要
本文介绍了当前神经元MOS管电路研究的现状,结合当前集成电路的发展方向及要求,探讨了在通信系统中,神经元MOS电路的应用可能性及其特有的优点。
分析了神经元MOS管及其改良结构的特点,并提出了新的钟控神经元MOS管的SPICE模型,新的模型适用范围更大,使电路仿真更方便。
从WCDMA主同步码的构造方法出发,分析了主同步码的特点,并介绍了WCDMA小区搜索中同步的过程。
介绍了电路系统中采样保持单元的几种传统的实现方法,以及已有的利用浮栅MOS管来实现的方法,并提出了一种基于钟控神经元MOS管的新型采样保持电路,此电路具有精度高、结构简单、功耗低等特点,然后采用HSPICE对电路进行了仿真,并和以前的方案做了比较。
分析了传统匹配滤波器的优缺点,提出了一种基于神经元MOS管的WCDMA主同步匹配滤波器结构,采用这个结构的匹配滤波器直接处理模拟信号,省掉了高速A/D转换器,降低了电路功耗,并大大简化了匹配滤波器的电路实现。随后采用MATLAB对此结构进行了验证。
用一种与主同步码性能相仿的简化码,设计了一个匹配滤波器,并且用HSPICE对组成匹配滤波器的主要电路单元进行了电路仿真,分析了仿真的结果,以此来验证WCDMA主同步匹配滤波器电路结构的正确性,随后分析了用神经元MOS电路实现WCDMA主同步匹配滤波器时在性能及结构上的改良。
本文的研究工作,探讨了钟控神经元MOS管在通信系统中的应用潜能。从本文的研究内容可以看出,钟控神经元MOS管电路具有结构简单,功耗低等特点,非常适合于低功耗的应用场合,并且可以简化电路结构,特别适合于便携设备的电路设计。
This paper analyzes the status and trends of the neuron-MOS circuits development.The possibility and advantages of the neuron-MOS transistor circuits in the communication system are discussed,which meet the requirements of the integrated circuit developing.
The characteristics of the neuron-MOS transistor structure and the improved structure are analyzed.A new SPICE simulation model is proposed,which is more suitable to the different applications,and makes the simulation more convenient.
Base on the construction of the WCDMA PSC,the characteristics of the PSC are analyzed,and the process of the cell searching in WCDMA is presented.
Several traditional ways and ways that base on the floating-gate MOS to implement the S/H circuit are presented,and then a new method,which base on the clock-controlled neuron-MOS transistor,is proposed.The S/H circuit based on this new method has the advantages of simplification,high accuracy and low power consumption.A simulation on HSPICE is made,and a compare between the new method and the traditional ways is given.
The advantages and disadvantages of the traditional matched filter are analyzed, and a WCDMA PSC matched filter base on the neuron-MOS circuits is proposed. This matched filter processes the analog signals,so it can save a lot of circuit cells.A simulation of the matched filter structure using MATLAB has been given.
This paper uses a simplified code that has the similar characteristics of the PSC to design a matched filter,and makes a simulation of the cell circuits of the matched filter using HSPICE.The results of the simulation are analyzed,to verify the correctness of the matched filter,and to illustrate the advantages of the implement using neuron-MOS circuits.
The researches of this paper show the potential of the neuron-MOS circuits in the communication system.The circuits base on the clock-controlled neuron-MOS transistor have the characteristics of simple structure,low power consumption and so on,so they are very suitable to the low power and simplified structure applications, especially to the handle equipments.
分析了神经元MOS管及其改良结构的特点,并提出了新的钟控神经元MOS管的SPICE模型,新的模型适用范围更大,使电路仿真更方便。
从WCDMA主同步码的构造方法出发,分析了主同步码的特点,并介绍了WCDMA小区搜索中同步的过程。
介绍了电路系统中采样保持单元的几种传统的实现方法,以及已有的利用浮栅MOS管来实现的方法,并提出了一种基于钟控神经元MOS管的新型采样保持电路,此电路具有精度高、结构简单、功耗低等特点,然后采用HSPICE对电路进行了仿真,并和以前的方案做了比较。
分析了传统匹配滤波器的优缺点,提出了一种基于神经元MOS管的WCDMA主同步匹配滤波器结构,采用这个结构的匹配滤波器直接处理模拟信号,省掉了高速A/D转换器,降低了电路功耗,并大大简化了匹配滤波器的电路实现。随后采用MATLAB对此结构进行了验证。
用一种与主同步码性能相仿的简化码,设计了一个匹配滤波器,并且用HSPICE对组成匹配滤波器的主要电路单元进行了电路仿真,分析了仿真的结果,以此来验证WCDMA主同步匹配滤波器电路结构的正确性,随后分析了用神经元MOS电路实现WCDMA主同步匹配滤波器时在性能及结构上的改良。
本文的研究工作,探讨了钟控神经元MOS管在通信系统中的应用潜能。从本文的研究内容可以看出,钟控神经元MOS管电路具有结构简单,功耗低等特点,非常适合于低功耗的应用场合,并且可以简化电路结构,特别适合于便携设备的电路设计。
This paper analyzes the status and trends of the neuron-MOS circuits development.The possibility and advantages of the neuron-MOS transistor circuits in the communication system are discussed,which meet the requirements of the integrated circuit developing.
The characteristics of the neuron-MOS transistor structure and the improved structure are analyzed.A new SPICE simulation model is proposed,which is more suitable to the different applications,and makes the simulation more convenient.
Base on the construction of the WCDMA PSC,the characteristics of the PSC are analyzed,and the process of the cell searching in WCDMA is presented.
Several traditional ways and ways that base on the floating-gate MOS to implement the S/H circuit are presented,and then a new method,which base on the clock-controlled neuron-MOS transistor,is proposed.The S/H circuit based on this new method has the advantages of simplification,high accuracy and low power consumption.A simulation on HSPICE is made,and a compare between the new method and the traditional ways is given.
The advantages and disadvantages of the traditional matched filter are analyzed, and a WCDMA PSC matched filter base on the neuron-MOS circuits is proposed. This matched filter processes the analog signals,so it can save a lot of circuit cells.A simulation of the matched filter structure using MATLAB has been given.
This paper uses a simplified code that has the similar characteristics of the PSC to design a matched filter,and makes a simulation of the cell circuits of the matched filter using HSPICE.The results of the simulation are analyzed,to verify the correctness of the matched filter,and to illustrate the advantages of the implement using neuron-MOS circuits.
The researches of this paper show the potential of the neuron-MOS circuits in the communication system.The circuits base on the clock-controlled neuron-MOS transistor have the characteristics of simple structure,low power consumption and so on,so they are very suitable to the low power and simplified structure applications, especially to the handle equipments.
引文
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[3]ISHII H;SHIBATA T;KOSAKA H;et al.Hardware-backpropagation learning of neuron MOS neural networks[C]//International Electron Devices Meeting.San Francisco:[s.n.],1992:435-438.
[4]SHIBATA T;KOSAKA H;ISHII H.;et al.A neuron-MOS neural network using self-learning-compatible synapse circuits[J],IEEE Journal of Solid-State Circuits,1995,30(8):913-922
[5]KOSAKA H;SHIBATA T;ISHII H;et al.An excellent weight-updating-linearity synapse memory cell for self-learning neuron MOS neural networks[C]// International Electron Devices Meeting.Washington,DC:[s.n.],1993:623-626
[6]AU R.;YAMASHITA T.;SHIBATA T;et al.Neuron-MOS multiple-valued memory technology for intelligent data processing[C]// International Solid-State Circuits Conference.San Francisco:[s.n.],1994:270-271.
[7]ISHIKAWA Y;FUKAI S.A neuron MOS variable logic circuit with the simplified circuit structure[C]// Proceedings of IEEE Asia-Pacific Conference on Advanced System Integrated Circuits.[S.l.]:[s.n.],2004:436-437.
[8]SHIBATA T;OHMI T.Neuron MOS binary-logic integrated circuits.Ⅰ.Design fundamentals and soft-hardware-logic circuit implementation[J],IEEE Transactions on Electron Devices,1993,40(3):570-576.
[9]SHIBATA T;OHMI T.Neuron MOS binary-logic integrated circuits.Ⅱ.Simplifying techniques of circuit configuration and their practical applications[J],IEEE Transactions on Electron Devices,1993,40(5):974-979
[10]YU NING-MEI;SHIBATA T;OHMI T.A real-time center-of-mass tracker circuit implemented by neuron MOS technology[J],IEEE Transactions on Circuits and Systems Ⅱ:Analog and Digital Signal Processing,1998,45(4):495-503
[11]YAMASAKI T;NAKAYAMA T;SHIBATA T.A low-power and compact CDMA matched filter based on switched-current technology[J],IEEE Journal of Solid-State Circuits,2005,40(4):926-932
[12]YAMASAKI T;SHIBATA T.A Low-Power Floating-Gate-MOS-Based CDMA Matched Filter Featuring Coupling Capacitor Disconnection[J],IEEE Journal of Solid-State Circuits,2007,42(2):422-430
[13]OKADA A;SHIBATA T.A neuron-MOS parallel associator for high-speed CDMA matched filter[C]// Proceedings of International Symposium on Circuits and Systems.Orlando:[s.n.],1999:392-395 vol.2
[14]YAMASHITA T;SHIBATA T;OHMI T.Neuron MOS winner-take-all circuit and its application to associative memory[C]//International Solid-State Circuits Conference.San Francisco:[s.n.],1993:236-237,294.
[15]SHIBATA T;KONDA M;YAMASHITA Y;et al.Neuron-MOS-based association hardware for real-time event recognition[C]// Proceedings of Fifth International Conference on Microelectronics for Neural Networks. Lausanne : [s. n.], 1996: 94-101.
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