HDL代码质量评估方法关键技术研究与电路性能优化
|
摘要
HDL源代码的质量度量和质量控制是加速SoC/ASIC芯片设计进度、提高SoC/ASIC芯片质量的重要环节，已经成为限制SoC/ASIC芯片质量和可靠性的瓶颈，为了加速SoC/ASIC设计过程，保证源代码研发质量，并尽早发现芯片设计阶段存在的缺陷，迫切需要提出HDL源代码质量评估的方法。本文对HDL源代码质量评估关键技术——HDL源代码抽象技术和组合逻辑环转化技术进行了研究。同时，研究成果在参与的三个芯片设计项目中得到了验证。主要成果有：
1、鉴于现有主流源代码工具只能根据定制的规则进行静态形式检查，对于一些与规则无关的代码缺陷则无法进行审核。故提出了一种以复杂度为导向的HDL源代码抽象方法，该方法着眼于可综合HDL源代码层面，将源代码抽象为一个两层有向网络。该网络以高复杂度节点为网络源端，边权值反映HDL源代码的描述复杂度。采用了经典的Dijkstra算法作为高复杂度代码搜索算法，将其应用于定位HDL源代码中复杂度较高的部分。其中，被作为实验对象的实例有：处理器类设计PE、总线结构类设计XD_BUS、算法实现类设计MQ编码器、通用外设类IP核MMC/SD/TF卡控制器。实验结果说明，该方法能够有效地提取代码中设计复杂度较高的代码，使得这部分设计较为复杂、易出现质量问题的源代码得到重点审核，弥补现有源代码检查工具只能进行静态规则审查的缺陷，并给电路设计提出指导性意见。
2、提出一种组合逻辑环转化方法，以解决RTL以及高级语言逻辑综合阶段所面临的拆分组合逻辑环的问题。相比现有文献，引入了SAT引擎对电路进行了表征，并使用静态逻辑蕴涵完成了电路的逻辑推理，同时，在求解过程中，根据实际应用需求对蕴涵规则进行了定制，使得在计算过程中，能够不断地对冗余向量和目标函数进行优化。以选定实例的源代码和开源代码为实验对象，评估了所提出的组合逻辑环识别和拆分算法的性能。实验结果表明，转化时间和转化后非环电路的规模都小于现有文献。
3、应用所提出的高复杂度HDL源代码搜索方法，对XD_BUS的源代码进行了质量评估，并依据得出的评估结果，给XD_BUS的优化和重新设计提出了相应的指导意见。结合该指导意见，对XD_BUS进行了优化和重新设计，该优化方案采用了多个设备队列，降低了片上总线与设备之间的耦合度；同时，将数据接收通道和数据发送通道分离，并在数据接收通道和数据发送通道中设置了多条子数据通道，提高了数据传输的并发性。采用了SMIC0.18μm标准单元工艺库完成了该总线的逻辑综合，其最高工作频率为232MHz。同时，完成了XD_BUS的性能评估，其总线吞吐率为5.4Gbps@100MHz，远大于规格要求的3.2Gbps@100MHz。
4、应用所提出的高复杂度HDL源代码搜索方法，对MQ编码器的源代码进行了质量评估，并依据得出的评估结果，给MQ编码器的优化和重新设计提出了相应的指导意见。结合该指导意见，提出了一种串行MQ编码器VLSI结构和并行多上下文MQ编码器VLSI结构。相比现有文献，创新点在于：（1）分析了编码过程中上下文保持次数、索引值保持次数等，并将其分离，最终针对不同的事件设计了不同的硬件结构，使得各种事件都能被更好地处理；（2）提出了一种索引值预测方法，可并行处理多个连续相同的上下文CXD；（3）提出了一种前导零电路检测VLSI结构，并通过一次性移位的方法，避免了重归一化过程的循环迭代；（4）优化了索引表，将其中的启动态和非暂态分离并进行了独立的分析，降低了硬件传播延时。基于TSMC0.18μm标准单元工艺库的综合结果表明，提出的并行多上下文MQ编码器能够工作在286.80MHz，吞吐率为573.60Msymbols/sec，提出的串行MQ编码器最高工作频率为547MHz，其面积为79012.84μm2，其吞吐量为547Msymbols/sec。这两个MQ编码器硬件结构的吞吐量都高于现有文献中的设计。
5、提出了一种外设类IP核的可配置设计方法，该方法将IP核功能点抽象为指令集，并建立了粗粒度单元和细粒度单元的单元库文件，通过不同的指令调度方案，完成对IP核功能的设计。以应用于雷达信号处理器中的外设类IP核MMC/SD/TF卡控制器为实验对象，对其所对应的各种IP核结构进行了分析，利用这些IP核结构较为规则的特点，将SD/TF卡Master控制器IP核作为设计对象，最终生成了需要的IP核硬件电路。该方法可弥补人工RTL代码设计IP核的方法的缺陷，如源代码可扩展性、可配置性、一致性较差等。
As an important part in SoC/ASIC chip quality assurance system, the criteria andcontrol of HDL source code quality has become a key factor to the quality andcredibility control of SoC/ASIC chip. In order to address the challenges facing us in thepresent SoC/ASIC design, it is urgent to propose a novel method to evaluate the HDLsource code quality to realize the targets, such as finishing the development ofhigh-quality HDL source code in a rapid and highly efficient manner and detectingflaws at an early stage of the chip design. In this paper, two critical techniques of theHDL source code evaluation are studied, which are the abstraction method of the HDLcode and the method of transforming cyclic circuits into acyclic equivalents.Furthermore, these methods are applied in the design of three VLSI designs which areXD_BUS, MQ-encoder and MMC/SD/TF card controller. The main studies andconclusive results are as follows.
1. Since HDL source code is checked by fairness policy by available EDA toolsaccording to some specified rules, some rules independent defects cannot be laid specialstress on. In view of this fact, the paper proposed a complexity oriented abstractionmethod of the HDL code. Using this method, the HDL code is defined as a two-levelnetwork. And in this network, the weight of edges is used to describe the complexity ofnodes; and high complexity nodes have been chosen as the source-point of the network.Furthermore, based on this network, the Dijkstra method is introduced to search thehighest complexity parts of the source codes. It should be noted that four types of VLSIdesigns are selected in order to prove the universality of the proposed method, such asthe PE (a RISC CPU of XDNP), the XD_BUS (bus of XDNP,) MQ-encoder, andMMC/SD/TF card controller. Experiments show that this method is able to effectivelylocate the most complex part of HDL source codes. With the help of this method, thecode qualities of the proposed VLSI designs are improved. Moreover, some advices arepresented according to the analyses of these experimental results.
2. Cyclic circuit is able to reduce the area and power consumption, but it is difficultto analyze by tools such as static timing analyzers. Furthermore, simulation and DFT forthe cyclic circuit are more expensive and complicated. Thus, in order to remove theunwanted cycles in the high-level synthesis process, a method for transforming cycliccircuits into acyclic equivalents based on the SAT is presented in this paper. Differentfrom the available researches, this paper uses the SAT and static logic implicationtechnique to represent the circuits. Meanwhile, by analyzing the structure and mechanism of the cyclic circuits, some novel rules are proposed to obtain the acyclicequivalents more precisely and effectively. Experiments were performed on theproposed VLSI designs and the IP cores which come from Opencore. Compared withthe available papers, the transforming time and the area of results are decreased,.
3. In accordance with the quality evaluation results of the source codes and therequirements of the XDNP(Xidian network processor), this paper proposed a loosecoupling and split transaction On-Chip Bus which is called XD_BUS. Compared withthe common bus, each device is separated from the XD_BUS by introducingbuffer-devices, which leads that the devices connected with the bus can workindependently. Thus, this method decreases the coupling degree between the masterdevices and slave devices. Furthermore, split transaction mechanism is adopted in thedesign of the data-bus as follows: first, the data-receive channel and the data-transformchannel are separated; second, in each channel, every device has its own data-bus. As aresult, this scheme improves the concurrency ability of the XD_BUS. The proposedarchitecture is synthesized with SMIC0.18μm technology library. The implementationresult shows that the frequency of the proposed architecture is232MHz. Meanwhile, thethroughput of the XD_BUS is5.4Gbps@100MHz which is larger than the requirementsof the XDNP.
4. Based on the quality evaluation results of the source codes, this paper hasproposed two VLSI designs for MQ-encoder, that is, Sequential MQ-encoder which iscapable of encoding one symbol per clock, and Two-context MQ-encoder which iscapable of encoding two symbols in parallel. Compared with available designs, thenovelties of these two architectures are as follows:(1) The correlations between thesequential pairs of context and its decision are analyzed. Moreover, the burst number ofCX and the burst number of the index value are studied. Due to these analyses, aconclusion is drawn in order to prevent the AE from stalling when the burst number ofthe context is larger than one.(2)The probabilities of different adjusting manners for theinterval register A and code register C before renormalization are given. On the basis ofthese data, a detector of leading-zero is proposed to simplify the renormalizationprocedure.(3) An improved mechanism has been proposed to acquire indexes byseparating the "start-up" states and remaining states. The proposed architectures aresynthesized with TSMC0.18μm HS technology library of ARM Company. Synthesisresult shows that the processing speed of the Two-context MQ-coder could reach ashigh as286.80MHz with a throughput of573.60Msymbols/sec. And the implementationresult shows that the throughput of the Sequential MQ-encoder is547Msymbols/sec with an area of79012.84μm2. Compared with the available designs, the throughput hasbeen increased.
5. Generally, the method of hand-written RTL code has large number of defects,such as the inflexibility and low configurability. To remedy these defects, this paperproposed a reconfigurable design approach which can be used in the design of IP cores.By this method, the functions of IP cores are analyzed and then abstracted as theinstruction set. Meanwhile, the paper establishes a cell library which includescoarse-grained cells and fine-grained cells. Based on these files, we can complete thedesign of IP cores by scheduling different instructions. Finally, the MMC/SD/TF cardcontroller IP cores which are used in a radar digital signal processor are selected as theexperimental subjects. In this experiment, the characteristics of different card controllerIP cores are analyzed. And then, the conclusion is pointed out that the hardwarearchitectures of these IP cores are regular and similar. Based on this conclusion, usingthe proposed scheme, the design of the MMC/SD/TF card master controller IP core isrealized.
1、鉴于现有主流源代码工具只能根据定制的规则进行静态形式检查，对于一些与规则无关的代码缺陷则无法进行审核。故提出了一种以复杂度为导向的HDL源代码抽象方法，该方法着眼于可综合HDL源代码层面，将源代码抽象为一个两层有向网络。该网络以高复杂度节点为网络源端，边权值反映HDL源代码的描述复杂度。采用了经典的Dijkstra算法作为高复杂度代码搜索算法，将其应用于定位HDL源代码中复杂度较高的部分。其中，被作为实验对象的实例有：处理器类设计PE、总线结构类设计XD_BUS、算法实现类设计MQ编码器、通用外设类IP核MMC/SD/TF卡控制器。实验结果说明，该方法能够有效地提取代码中设计复杂度较高的代码，使得这部分设计较为复杂、易出现质量问题的源代码得到重点审核，弥补现有源代码检查工具只能进行静态规则审查的缺陷，并给电路设计提出指导性意见。
2、提出一种组合逻辑环转化方法，以解决RTL以及高级语言逻辑综合阶段所面临的拆分组合逻辑环的问题。相比现有文献，引入了SAT引擎对电路进行了表征，并使用静态逻辑蕴涵完成了电路的逻辑推理，同时，在求解过程中，根据实际应用需求对蕴涵规则进行了定制，使得在计算过程中，能够不断地对冗余向量和目标函数进行优化。以选定实例的源代码和开源代码为实验对象，评估了所提出的组合逻辑环识别和拆分算法的性能。实验结果表明，转化时间和转化后非环电路的规模都小于现有文献。
3、应用所提出的高复杂度HDL源代码搜索方法，对XD_BUS的源代码进行了质量评估，并依据得出的评估结果，给XD_BUS的优化和重新设计提出了相应的指导意见。结合该指导意见，对XD_BUS进行了优化和重新设计，该优化方案采用了多个设备队列，降低了片上总线与设备之间的耦合度；同时，将数据接收通道和数据发送通道分离，并在数据接收通道和数据发送通道中设置了多条子数据通道，提高了数据传输的并发性。采用了SMIC0.18μm标准单元工艺库完成了该总线的逻辑综合，其最高工作频率为232MHz。同时，完成了XD_BUS的性能评估，其总线吞吐率为5.4Gbps@100MHz，远大于规格要求的3.2Gbps@100MHz。
4、应用所提出的高复杂度HDL源代码搜索方法，对MQ编码器的源代码进行了质量评估，并依据得出的评估结果，给MQ编码器的优化和重新设计提出了相应的指导意见。结合该指导意见，提出了一种串行MQ编码器VLSI结构和并行多上下文MQ编码器VLSI结构。相比现有文献，创新点在于：（1）分析了编码过程中上下文保持次数、索引值保持次数等，并将其分离，最终针对不同的事件设计了不同的硬件结构，使得各种事件都能被更好地处理；（2）提出了一种索引值预测方法，可并行处理多个连续相同的上下文CXD；（3）提出了一种前导零电路检测VLSI结构，并通过一次性移位的方法，避免了重归一化过程的循环迭代；（4）优化了索引表，将其中的启动态和非暂态分离并进行了独立的分析，降低了硬件传播延时。基于TSMC0.18μm标准单元工艺库的综合结果表明，提出的并行多上下文MQ编码器能够工作在286.80MHz，吞吐率为573.60Msymbols/sec，提出的串行MQ编码器最高工作频率为547MHz，其面积为79012.84μm2，其吞吐量为547Msymbols/sec。这两个MQ编码器硬件结构的吞吐量都高于现有文献中的设计。
5、提出了一种外设类IP核的可配置设计方法，该方法将IP核功能点抽象为指令集，并建立了粗粒度单元和细粒度单元的单元库文件，通过不同的指令调度方案，完成对IP核功能的设计。以应用于雷达信号处理器中的外设类IP核MMC/SD/TF卡控制器为实验对象，对其所对应的各种IP核结构进行了分析，利用这些IP核结构较为规则的特点，将SD/TF卡Master控制器IP核作为设计对象，最终生成了需要的IP核硬件电路。该方法可弥补人工RTL代码设计IP核的方法的缺陷，如源代码可扩展性、可配置性、一致性较差等。
As an important part in SoC/ASIC chip quality assurance system, the criteria andcontrol of HDL source code quality has become a key factor to the quality andcredibility control of SoC/ASIC chip. In order to address the challenges facing us in thepresent SoC/ASIC design, it is urgent to propose a novel method to evaluate the HDLsource code quality to realize the targets, such as finishing the development ofhigh-quality HDL source code in a rapid and highly efficient manner and detectingflaws at an early stage of the chip design. In this paper, two critical techniques of theHDL source code evaluation are studied, which are the abstraction method of the HDLcode and the method of transforming cyclic circuits into acyclic equivalents.Furthermore, these methods are applied in the design of three VLSI designs which areXD_BUS, MQ-encoder and MMC/SD/TF card controller. The main studies andconclusive results are as follows.
1. Since HDL source code is checked by fairness policy by available EDA toolsaccording to some specified rules, some rules independent defects cannot be laid specialstress on. In view of this fact, the paper proposed a complexity oriented abstractionmethod of the HDL code. Using this method, the HDL code is defined as a two-levelnetwork. And in this network, the weight of edges is used to describe the complexity ofnodes; and high complexity nodes have been chosen as the source-point of the network.Furthermore, based on this network, the Dijkstra method is introduced to search thehighest complexity parts of the source codes. It should be noted that four types of VLSIdesigns are selected in order to prove the universality of the proposed method, such asthe PE (a RISC CPU of XDNP), the XD_BUS (bus of XDNP,) MQ-encoder, andMMC/SD/TF card controller. Experiments show that this method is able to effectivelylocate the most complex part of HDL source codes. With the help of this method, thecode qualities of the proposed VLSI designs are improved. Moreover, some advices arepresented according to the analyses of these experimental results.
2. Cyclic circuit is able to reduce the area and power consumption, but it is difficultto analyze by tools such as static timing analyzers. Furthermore, simulation and DFT forthe cyclic circuit are more expensive and complicated. Thus, in order to remove theunwanted cycles in the high-level synthesis process, a method for transforming cycliccircuits into acyclic equivalents based on the SAT is presented in this paper. Differentfrom the available researches, this paper uses the SAT and static logic implicationtechnique to represent the circuits. Meanwhile, by analyzing the structure and mechanism of the cyclic circuits, some novel rules are proposed to obtain the acyclicequivalents more precisely and effectively. Experiments were performed on theproposed VLSI designs and the IP cores which come from Opencore. Compared withthe available papers, the transforming time and the area of results are decreased,.
3. In accordance with the quality evaluation results of the source codes and therequirements of the XDNP(Xidian network processor), this paper proposed a loosecoupling and split transaction On-Chip Bus which is called XD_BUS. Compared withthe common bus, each device is separated from the XD_BUS by introducingbuffer-devices, which leads that the devices connected with the bus can workindependently. Thus, this method decreases the coupling degree between the masterdevices and slave devices. Furthermore, split transaction mechanism is adopted in thedesign of the data-bus as follows: first, the data-receive channel and the data-transformchannel are separated; second, in each channel, every device has its own data-bus. As aresult, this scheme improves the concurrency ability of the XD_BUS. The proposedarchitecture is synthesized with SMIC0.18μm technology library. The implementationresult shows that the frequency of the proposed architecture is232MHz. Meanwhile, thethroughput of the XD_BUS is5.4Gbps@100MHz which is larger than the requirementsof the XDNP.
4. Based on the quality evaluation results of the source codes, this paper hasproposed two VLSI designs for MQ-encoder, that is, Sequential MQ-encoder which iscapable of encoding one symbol per clock, and Two-context MQ-encoder which iscapable of encoding two symbols in parallel. Compared with available designs, thenovelties of these two architectures are as follows:(1) The correlations between thesequential pairs of context and its decision are analyzed. Moreover, the burst number ofCX and the burst number of the index value are studied. Due to these analyses, aconclusion is drawn in order to prevent the AE from stalling when the burst number ofthe context is larger than one.(2)The probabilities of different adjusting manners for theinterval register A and code register C before renormalization are given. On the basis ofthese data, a detector of leading-zero is proposed to simplify the renormalizationprocedure.(3) An improved mechanism has been proposed to acquire indexes byseparating the "start-up" states and remaining states. The proposed architectures aresynthesized with TSMC0.18μm HS technology library of ARM Company. Synthesisresult shows that the processing speed of the Two-context MQ-coder could reach ashigh as286.80MHz with a throughput of573.60Msymbols/sec. And the implementationresult shows that the throughput of the Sequential MQ-encoder is547Msymbols/sec with an area of79012.84μm2. Compared with the available designs, the throughput hasbeen increased.
5. Generally, the method of hand-written RTL code has large number of defects,such as the inflexibility and low configurability. To remedy these defects, this paperproposed a reconfigurable design approach which can be used in the design of IP cores.By this method, the functions of IP cores are analyzed and then abstracted as theinstruction set. Meanwhile, the paper establishes a cell library which includescoarse-grained cells and fine-grained cells. Based on these files, we can complete thedesign of IP cores by scheduling different instructions. Finally, the MMC/SD/TF cardcontroller IP cores which are used in a radar digital signal processor are selected as theexperimental subjects. In this experiment, the characteristics of different card controllerIP cores are analyzed. And then, the conclusion is pointed out that the hardwarearchitectures of these IP cores are regular and similar. Based on this conclusion, usingthe proposed scheme, the design of the MMC/SD/TF card master controller IP core isrealized.
引文
[1]顾平,李良荣. EDA之价值.贵州大学学报(自然科学版).2004,21(1):86-89.
[2]张繁,刘笃仁. SOC设计面对的技术挑战.今日电子.2004,12:85-87.
[3]潘杰.聚芯SoC高性能访存技术研究.硕士论文,中国科学院研究生院(计算技术研究所),2006.
[4] Frank Rogin, Rolf Drechsler. Debugging at the Electronic System Level.Springer Netherlands.2010.
[5] J. D. Morison, A. S. Clarke. Ella2000: A Language for Electronic SystemDesign. McGraw-Hill, Inc. New York, NY, USA.2000.
[6] Synopsys LEDA User Guide. Version D-2010.03. March2010.
[7] Synopsys Design Compiler User Guide. Version D-2010.03-SP2, June2010.
[8] Cadence Encounter RTL Compiler Ultra User Guide. Product Version7.1.2.September2007.
[9] IEEE Standard Verilog Hardware Description Language. IEEE Std1364-2001.28September2001.
[10] IEEE Standard VHDL Language Reference Manual. IEEE Std.1076-1993.
[11]李晓维,吕涛,李华伟,李光辉.数字集成电路设计验证—量化评估、激励生成、形式化验证.科学出版社.2010.
[12] McCabe T. A complexity measure. IEEE Transactions on Software Engineering.vol.12(4),1976.
[13] Halstead M. Elements of Software Science. Elsevier North Holland, New York.1997.
[14] Shepperd. An evaluation of software product metrics. Information and softwaretechnology.1988,30(3):177-88.
[15] Myers G. An extension to the cyctomalic measure of Program complexity.SIGPLAN Notices.1977,12(10):77-79.
[16]朱云峰.代码复杂度度量与质量控制在日立项目中的应用.硕士论文,长春理工大学,2004年.
[17]冯欣.代码质量控制与复杂度测量在大型软件项目中的研究及应用.硕士论文,东北师范大学,2006年.
[18] M. Ljpow. Number of faults per line of code. IEEE Transactions on SoftwareEngineering.1982, SE-8(4):.437-9.
[19]李暾,屈婉霞,郭阳,刘功杰,李思昆.基于符号模拟和约束逻辑变成的RTL级Verilog谓词抽象方法.计算机学报.2007,30(7):1138-1144.
[20] Jaffar J, Maher M J. Constraint logic programming：A survey. The Journal ofLogic Programming.1994,14(19-20):503-582.
[21] Ubar R. Test synthesis with alternative graphs. IEEE Design&Test of Computers.1996,13(1):48-57.
[22] Waseem Muhammad, Sophie Coudert, Rabea Ameur-Boulifa, Renaud Pacalet.Separating Control and Data Processing in RT level Virtual IP Components.Proceedings of the2007Ph.D Research in Microelectronics and Electronicsconference, PRIME2007.2007:273-276.
[23] Yin Z G, Min Y H, Li X W.A novel RT-level behavioral description based ATPGmethod. Journal of Computer Science and Technology.2003,18(3):308-317.
[24]尹志刚,李华伟,李晓维.一种面向测试的RTL行为抽象与蕴涵方法.同济大学学报(自然科学版).2002,30(10):1199-1203.
[25]鲁巍,吕涛,杨修涛,李晓维. RTL可观测性语句覆盖评估方法.计算机辅助设计与图形学学报.2006,18(1):62-68.
[26] Mukherjee Biswarup, Dandapat Anup Kumar. Design of Combinational Circuitsby Cyclic Combinational Method for Low Power VLSI.2010InternationalSymposium on Electronic System Design. Bhubaneswar, India: IEEE.2010:107-112.
[27] Chan Terence. A robust multithreaded HDL/ESL simulator for deep submicronintegrated circuit designs.2012IEEE Asia Pacific Conference on Circuits andSystems, APCCAS2012. Kaohsiung, Taiwan: IEEE,2012:416-419.
[28] Huang Hsu-Yao, Huang Chi-Yuan, Chen Chung-Ho. Tile-based GPUoptimizations through ESL full system simulation.[C]//ISCAS2012-2012IEEE International Symposium on Circuits and Systems. Seoul, Korea: IEEE,2012:1327-1330.
[29] Chen Weiwei, D mer Rainer. An optimizing compiler for out-of-order parallelESL simulation exploiting instance isolation.17th Asia and South Pacific DesignAutomation Conference, ASP-DAC2012. Sydney, NSW, Australia: IEEE,2012:461-466.
[30] Yoshikawa Y. A binding algorithm in high-level synthesis for path delaytestability.201318th Asia and South Pacific Design Automation Conference(ASP-DAC2013). Yokohama, Japan: IEEE,2013:546-51.
[31] Neiroukh Osama, Edwards, Stephen A., Song Xiaoyu. An Efficient Algorithmfor the Analysis of Cyclic Circuits. Proceedings of the2006Emerging VLSITechnologies and Architectures. Klarlsruhe, Germany: IEEE,2006:303-308.
[32] Mentor Graphics Corporation CDC Compiler User Guide. Release2.3PartNumber224246May10,2005.
[33] T. Kapschitz, R. Ginosar. Formal Verification of Synchronizers. Conference ofCorrect Hardware Design and Verification Methods,2005.
[34] Bing Li, Chris Ka-Kei Kwok. Automatic Formal Verification of Clock DomainCrossing Signals. Proceedings of the Asia and South Pacific Design AutomationConference, ASP-DAC.2009:654-659.
[35]冯毅,易江芳,刘丹,佟冬,程旭.面向SoC系统芯片中跨时钟域设计的模型检验方法.电子学报.2008,36(5):886-892.
[36]冯毅,许经纬,易江芳,佟冬,程旭.面向模型检验的跨时钟域设计电路特性生成方法.电子学报.2009,37(2):258-265.
[37] Feng Yi, Zhou Zheng, Tong Dong, Cheng Xu. Clock domain crossing faultmodel and coverage metrics for validation of SoC design. Design, Automation&Test in Europe Conference&Exhibition. San Jose: EDA Consortium.2007:1385-1390.
[38] A. Chowdhary, S. Kale, et al. Extraction of Functional Regularity in DatapathCircuits. IEEE Trans. on Computer-Aided Design.1999,18(9):1279-1296.
[39] Angelo P.E. Rosiello, F. Ferrandi, D. Pandini, D. Sciuto. A Hash-based Approachfor Functional Regularity Extraction During Logic Synthesis. IEEE ComputerSocietyAnnual Symposium on VLSI. New York, IEEE.2007:92-97
[40]李长青,汪雪林等.辐射路匹配:从门级到功能模块级的子电路提取算法.计算机辅助设计与图形学学报,2006,18(9):1377-1382.
[41]潘伟涛,谢元斌,郝跃,史江一.二同构扩展数字集成电路规律性提取算法.西安电子科技大学学报(自然科学版).2009,36(3):452-462.
[42]潘伟涛,谢元斌,郝跃,史江一.基于扇形模板的数字集成电路规律性提取算法.电子学报. Vol.38, No.1. Jan.2010:199-203.
[43]潘伟涛,谢元斌,郝跃,史江义.基于启发式链搜索的频繁子电路提取算法.吉林大学学报(工学版).2011,41(6):1748-1753.
[44]潘伟涛,郝跃,谢元斌,史江义.小规模频繁子电路的规律性预提取算法.计算机辅助设计与图形学学报.2010,22(2):226-233,
[45] PAN Weitao,XIE Yuanbin,HAO Yue. An Algorithm for Chain-like FrequentSubcircuits Extraction in Digital Integrated Circuits. CHINESE JOURNAL OFCOMPUTATIONAL PHYSICS.2011,28(1):138-144.
[46] Synopsys Formality User Guide Version D-2010.03, March2010.
[47] Mentor Graphics FormalPro Datasheet.
[48] Hughes R B. Formal verification of equivalence in DSM designs usingformalProTM.
[49] Burch J R, Singhal V. Tight integration of combinational verification methods.Proceeding of IEEE/ACM International Conference on Computer-Aided Design,San Jose, CA, USA.1998:570-576.
[50] Anastasakis D, Damiano R, Ma H K T. A practical and efficient method forcompare-point matching. Proceeding of IEEE/ACM39th Design AutomationConference, New orleans, USA.2001:305-310.
[51] Shih-Chieh Wu, Chun-Yao Wang, and Yung-Chih Chen. Novel ProbabilisticCombinational Equivalence Checking. IEEE TRANSACTIONS ON VERYLARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL.16, NO.4, APRIL2008.365-375.
[52] Disch S, Schollm C. Combinational equivalence checking using incrementalSAT solving, output ordering, and resets. Proceeding of Asia and South PacificDesign Autonation Conference. Yokohama, Japan,2007:938-943.
[53] Mishchenko A, Chatterjee S, Brayton R. Improvements to combinationalequivalence checking. Proceeding of IEEE/ACM International Conference onComputer-Aided Design. San Jose, CA, USA,2006:836-843.
[54]翁延玲,葛海通,严晓浪,郑飞君.结合半加图的算术电路等价性验证技术.浙江大学学报(工学版).2008,42(8):1345-1349.
[55]翁延玲,葛海通,严晓浪.等价性验证中的自动算符排序.浙江大学学报(工学版).2007,41(6):886-889.
[56] Mukherjee R, Jain J, Pradhan D K. Functional learning: a new approach tolearning in digital circuits. Proceeding of IEEE VLSI Test Symposium. CherryHill, NJ, USA.1994:6-13.
[57] Kunz W, Menon P. Multi-level logic optimization by implication analysis.Proceeding of International Conference on Computer-Aided Design. San Jose,CA, USA.1994:6-13.
[58]何科.网络处理器高性能数据交换接口设计研究.硕士论文,西安电子科技大学,2011.
[59]谢元斌.异构多核网络安全处理器硬件优化技术研究.博士学位论文,西安电子科技大学,2011.
[60]我国自主开发的多核网络安全处理器填补国内该领域空白.[Online]:new.xinhuanet.com.2009.
[61]“清华天行”网络处理器鉴定.[Online]:www.sist.tsinghua.edu.cn.2006
[62]宋乾暾. JPEG2000中EBCOT编码的研究与实现.硕士学位论文,西安电子科技大学,2006.
[63]周正道.远程图像监控系统的研究和实现.硕士学位论文,西安电子科技大学,2003.
[64]朱珂.基于JPEG2000的静态图像压缩算法及VLSI实现的结构研究.博士论文,复旦大学,2004.
[65]刘海林.静止图像压缩研究-JPEG2000标准的分析与应用.硕士论文,成都理工大学,2002.
[66]郭杰.静止图像压缩结构设计与VLSI实现研究.博士论文,西安电子科技大学,2010.
[67]曲波. JPEG2000编码器中的高可靠码流组织VLSI设计.硕士论文,西安电子科技大学,2012.
[68]周宇. JPEG2000中EBCOT编码器的VLSI实现.硕士论文,西安电子科技大学,2009.
[69]万登峰.基于JPEG2000遥感图像压缩的应用研究.硕士论文,上海交通大学,2005年.
[70]李金佳. JPEG2000编码器中的高可靠码流组织VLSI设计.硕士论文,西安电子科技大学,2012.
[71]刘雷波. JPEG2000静止图像压缩关键技术研究及VLSI实现.博士论文,清华大学工学,2004.
[72]房琼. JPEG2000芯片设计及仿真方法研究.硕士论文,西安电子科技大学,2010.
[73]刘春风.基于ADV212的图像压缩编码系统设计.硕士论文,国防科学技术大学,2010.
[74] A.N. Skodras, C.A. Christopoulos, T. Ebrahimi. JPEG2000: The upcoming stillimage compression standard. Pattern Recognition Letters,2001,22(12):1337-1345.
[75]刘雷波,王学进,孟鸿鹰,王志华,陈弘毅,夏宇闻. JPEG2000小波变换器的VLSI结构设计.电子学报.2002,30(11):1609-1612.
[76]朱悦心,付昀,吴宗泽,郑南宁.基于多级查询表的JPEG2000位平面扫描优化方法.电子学报.2004,32(5):810-813.
[77]刘文松,朱恩,王健,徐龙涛,林叶. JPEG2000算术编码器的算法优化和VLSI设计.电子学报.2011,39(11):2486-2491.
[78] M.D. Adams and F. Kossentini.Jasper: a software-based JPEG-2000codecimplementation.Proc. IEEE Int. Conf. Image Processing, Sep.2004.2004,2:53-56.
[79] http://www.eepw.com.cn/article/86573.htm.
[80]江琳.兼容ARC指令集的RISC IP核的开发.硕士论文,哈尔滨工业大学,2007.
[81]郑伟,陈基禄.可配置、可扩展的处理器Xtens.微机发展.2002(2):88-91.
[82] Bill Pontikakis, Francois-R. Boyer, Yvon SavariaPerformance. Improvement ofConfigurable Processor Architectures Using a Variable Clock Period.Proceedings of the Fifth International Workshop on System-on-Chip forReal-Time Applications (IWSOC'05), Washington,2005. IEEE ComputerSociety,2005:454-458.
[83] http://www.eefocus.com/consumer-electronics/180634.
[84]毕萍萍.时钟控制单元代码自动生成技术的实现及验证.硕士论文,西安电子科技大学,2013.
[85]李凤伟.基于嵌入式系统的便携式学习电脑的应用开发.硕士论文,大连理工大学,2009.
[86]郑亮. SD/MMC控制器的设计与实现.硕士论文,厦门大学,2008.
[87]陈海生.基于STM32的TransFlash卡读写技术研究.硕士论文,哈尔滨工业大学,2009.
[88] Technical Committee SD Association. SD Host Controller SimplifiedSpecification Version1.00.2000.
[89] Technical Committee SD Association. SD Host Controller SimplifiedSpecification Version2.00.2006.
[90] Technical Committee SD Association. SD Host Controller SimplifiedSpecification Version3.00.2009.
[91]胡美群,夏银水,王伦耀.基于分支限界的关键路径求解算法.宁波大学学报(理工版).2011,24(2):37-41.
[92] Yaun-chung Hsu, Shangzhi Sun, David H.C. Finding The Longest Simple Path inCyclic Combinational Circuits. IEEE International Conference on ComputerDesign: VLSI in Computers and Processors. Austin, TX, USA.1998:530-535.
[93] Khaled R. Heloue, Sari Onaissi, Farid N. Najm. Efficient Block-BasedParameterized Timing Analysis Covering All Potentially Critical Paths. IEEETRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATEDCIRCUITS AND SYSTEMS.2012,31(4):472-484.
[94] Sharad Sinha, Udit Dhawan, Siew Kei Lam, et al. A Novel Binding Algorithm toReduce Critical Path Delay During High Level Synthesis.2011IEEE ComputerSocietyAnnual Symposium on VLSI. Chennai, India,2011:278-283.
[95] Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, et al. Path CriticalityComputation in Parameterized Statistical Timing Analysis Using a NovelOperator. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OFINTEGRATED CIRCUITS AND SYSTEMS.2012,31(4):497-508.
[96]郑四发,曹剑东,连小珉.复杂路网下多客户间最短路径的扇面Dijkstra算法.清华大学学报(自然科学版).2009,49(11):1834-1837.
[97] Osama Neiroukh, Stephen A. Edwards, Xiaoyu Song. Transforming CyclicCircuits Into Acyclic Equivalents. IEEE transaction on computer-aided design ofintegrated circuit and systems.2008,27(10):1775-1787.
[98] Riedel Marc D., Bruck Jehoshua. Cyclic Boolean circuits.Discrete AppliedMathematics.2012,160(13-14):1877-1900.
[99] Backes John D., Riedel Marc D.. The synthesis of cyclic dependencies withboolean satisfiability. ACM Transactions on Design Automation of ElectronicSystems.2012,17(4):1-24.
[100] Rivest, R.L.. The necessity of feedback in minimal monotone combinationalcircuits[J]. IEEE Transactions on Computers.1977,26(6):606–607.
[101] M. D. Riedel and J. Bruck. The synthesis of cyclic combinational circuits. Proc.40th Des. Autom. Conf.. Anaheim, CA.2003:163–168.
[102] Peter M. Maurer, Yun Sik Lee. Compiled unit-delay simulation for cyclic circuits.Proc. the IEEE SOUTHEASTCON '92. Birmingham, AL, USA.1992:184-188.
[103] Anand Raghunathan, Pranav Ashar, Sharad Malik. Test Generation for CyclicCombinational Circuits. IEEE Transactions on Computer-Aided Design ofIntegrated Circuits and Systems.1995,14(11):1408-1414.
[104] DeBenedictis E., Ghosh S., Yu M.-L. A novel algorithm for discrete-eventsimulation: asynchronous distributed discrete-event simulation algorithm forcyclic circuits using a dataflow network. Computer.1991,24(6):21-33.
[105] G. Berry. The foundations of Esterel. in Proof, Language, and Interac-tion:Essays in Honour of Robin Milner. Cambridge, MA: MIT Press.2000.
[106] Agarwal, Vineet, et al. An efficient combinationality check technique for thesynthesis of cyclic combinational circuits. in Proc. the Asia and South PacificDesign Automation Conference, ASP-DAC, Shanghai, China.2005,1:212-215.
[107] Chang Joon Lee, et al. A robust method for searching the smallest set of smallestrings with a path-included distance matrix. in Proc. the National Academy ofSciences of the United States ofAmerica.2009,106(41):17355-8,13.
[108] Edwards, S.A.. Making cyclic circuits acyclic. in Proc. Design AutomationConference. Anaheim, CA, USA.2003:159-62.
[109] S. Malik. Analysis of cyclic combinational circuits. IEEE Transactions onComputer-Aided Design of Integrated Circuits and Systems.1994,13(7):950-956.
[110] Malik Sharad. Analysis of cyclic combinational circuits. in Proc. the1993IEEE/ACM International Conference on Computer-Aided Design.1993:618-625.
[111] Srinivasan Arvind, Malik Sharad. Practical analysis of cyclic combinationalcircuits. in the Proc. the Custom Integrated Circuits Conference. San Diego, CA,USA.1996:381-384.
[112] E. B. Eichelberger. Hazard detection in combinational and sequential switchingcircuits. IBM J. Res. Develop.1965,9(2):90-99.
[113] T. R. Shiple. Formal analysis of synchronous circuits. Ph.D. dissertation, Univ.California, Berkeley, CA,1996.
[114] Shiple Thomas R., Berry Gerard, Touati Herve. Constructive analysis of cycliccircuits. in Proc. European Design and Test Conference. Paris, Fr..1996:328-333.
[115] L. Stok. False loops through resource sharing. in Proc. IEEE/ACM ICCAD, SanJose, CA.1992:345-348.
[116] A. Gupta, C. Selvidge. Acyclic modeling of combinational loops. in Proc.IEEE/ACM ICCAD. San Jose, CA.2005:343-347.
[117] Horton, J.D.. A polynomial-time algorithm to find the shortest cycle basis of agraph. SIAM Journal on Computing.1987,16(2):358-66.
[118] C. McCaw. Loops in directed combinational switching networks. Ph.D. Thesis,Stanford University,1963.
[119] Opencore. Available: http://opencores.org/.
[120]李瑞,张春元,罗莉.三种常用SoC片上总线的分析与比较.单片机与嵌入式系统应用,2004(2):5-8.
[121]邓崇亮,章焕昌. SoC片上五种总线标准的分析比较.百色学院学报.2008(3):50-55.
[122] A.Rincon, W.Lee, M.Slatery. The Changing Landscape of System-on-ChipDesign. Custom Integrated Circuits1999, Proceedings of the IEEE1999,5(3):83-90.
[123] ARM Corp．TheAMBA Specification Rev2.0.1999.
[124] Steve Furber. ARM System-on-Chip Architecture second edition[M].USA:Addison-Wesley Professional,2000.
[125] Patrick Pelgrims. Tom Tierens,Dries Driessens． Overview AMBA AvalonCoreConneet Wishbone.2003:2-6.
[126] IBM Corp．The CoreConnect Bus Architecture.1999.
[127]王庆成.面向IP包处理的硬件多线程处理器研究与设计2010-
[128]赵彦尚.网络处理器微引擎的设计、验证与实现.硕士论文,西安电子科技大学,2013.
[129]陈四强.基于Intel IXA的千兆以太路由器设计.硕士论文,电子科技大学,2003.
[130]董杰.多核网络处理器中定制控制处理器关键技术研究.硕士论文,西安电子科技大学,2011.
[131]关娜.网络处理器系统中SDR AM控制器电路设计与仲裁优化研究.硕士论文,西安电子科技大学,2010.
[132]安爱女.多核共享的高效存储控制模块研究与设计.硕士论文,西安电子科技大学,2011.
[133]余广明.基于片上多核系统高速数据交换接口的关键技术研究.硕士论文,西安电子科技大学,2013.
[134]孙杰. XDNP网络处理器快速总线接口FBI设计与实现.硕士论文,西安电子科技大学,2013.
[135]徐懿,杜高明,李丽,蒋召宇,张冰,高明伦.基于总线的片上多处理器SOC仲裁算法研究.仪器仪表学报2006,26(7):2415-2418.
[136]杨盛光,李丽,徐懿,张宇昂,娄孝祥,高明伦.基于拥塞预测的NoC自适应仲裁方法.计算机应用研究.2009,26(2):652-659.
[137]李耀荣,王兴军,梁利平. SoC总线仲裁算法的研究.片上系统SoC.2007,23(6-2):113-115.
[138]陈敬洋.基于多核包处理器的高速数据交换总线设计研究.硕士论文,西安电子科技大学,2011.
[139] Acharya, T., Tsai, P. S.. JPEG2000standard for image compression concepts,algorithms and VLSI architectures. Hoboken: John Wiley and Sons.2005.
[140] JPEG2000(2002) Part1020719(Final Publication Draft), ISO/IECJTC1/SC29/WG1N1636R, July2002.
[141] M. Rabbani, R. Joshi. An overview of the JPEG2000still image compressionstandard. Signal Processing: Image Communication,2002,17(1):3-48.
[142] A. Gupta, S. Nooshabadi, D. Taubman, M. Dyer. Realizing low-costhigh-throughput general-purpose block encoder for JPEG2000. IEEETransactions on Circuits and Systems for Video Technology.2006,16(7):843-858.
[143]雷磊. JPEG2000MQ编码器的高速VLSI设计与实现.硕士论文,中南大学,2010.
[144] Taubman D. S., Marcellin, M. W. JPEG2000: Image compression fundamenetals,standard and practice. Boston:Kluwer.2002.
[145] Minsoo Rhu, In-Cheol Park. Optimization of Arithmetic Coding for JPEG2000.IEEE Transactions on Circuits and Systems for Video Technology.2010,20(3):446-451.
[146]16Kishor Sarawadekar,Swapna Banerjee. VLSI design of memory-ef f cient,high-speed base line MQ coder for JPEG2000. Integration, the VLSI Journal.2012,45:1–8.
[147]17K. Liu, Y. Zhou, Y. Song Li, J.F. Ma. A high performance MQ encoderarchitecture in JPEG2000. Integration, the VLSI Journal.2010,43(3):305-317.
[148] Liu Wensong, Zhu En, Lin Ye, Sun Lei, Liu Jun. Design of JPEG2000ArithmeticCoder using Optimized Renormalization Procedure.2011InternationalConference on Multimedia and Signal Processing.2011,1:41-45.
[149] Nandini Ramesh Kumar, Wei Xiang, Yafeng Wang. Two-Symbol FPGAArchitecture for Fast Arithmetic Encoding in JPEG2000. Journal of SignalProcessing Systems.2012,69(2):213-224.
[150] M. Dyer, D. Taubman, S. Nooshabadi, A. Gupta. Concurrency techniques forarithmetic coding in JPEG2000. IEEE Transactions on Circuits and Systems.2006,53(6):1203–1213.
[151] N. Noikaew, O. Chitsobhuk.(2008). Dual symbol processing for MQ arithmeticcoder in JPEG2000. Congress on Image and Signal Processing CISP’08.2008,1:521–524.
[152] PENG Zhou, ZHAO Bao-jun. High-throughput Hardware Architecture of MQArithmetic Coder[C]. ICSP2010Proceedings,2010.2010:430-433.
[153] Minsoo Rhu, In-Cheol Park. Architecture Design of a High-PerformanceDual-Symbol Binary Arithmetic Coder for JPEG2000.2009IEEE InternationalConference on Image Processing.2009:2665-2668.
[154] Sarawadekar Kishor, Banerjee Swapna. Low-cost, high-performance VLSIdesign of an MQ coder for JPEG2000. ICSP2010Proceedings,2010:397-400.
[155] Wael M. El-Sharkasy, Mohamed E. Ragab.Hardware Modelling of JPEG2000MQ-Encoder.20124th International Conference on Intelli gent and AdvancedSystems (ICIA S2012).2012:707-712.
[156] MDyer, D Taubman, S Nooshabadi. Improved throughput arithmetic coder forJPEG2000. Proceedings of IEEE International Conference on Image Processing.USA: IEEE Press,2004,4:2817-2820.
[157] CYXiong, J HHou, et al. Efficient fast algorithmfor MQ arithmetic coder.Proceedings of IEEE Conference on Multimedia and Expo. USA:IEEE Press.2007:759-762.
[158] BMin, SYoon, J Ra, DSPark. Enhanced renormalization algorithm in MQ-coderof JPEG2000. Proceedings of International Symposium on InformationTechnology Convergence.USA: IEEE Press.2007:213-216.
[159] M. Dyer, S. Nooshabadi, D. Taubman. Design and analysis of system on a chipencoder for JPEG2000. IEEE Transactions on Circuits and Systems for VideoTechnology.2009,19(2):215–225.
[160] Y.Z. Zhang, C. Xu, W.T. Wang, L.B. Chen.(2007). Performance analysis andarchitec-ture design for parallel EBCOT encoder of JPEG2000. IEEETransactions on Circuits and Systems for Video Technology.2007,17(10):1336–1347.
[161]赵建飞.基于Simulink与AVR单片机的多接口音频系统的仿真与构建.硕士论文,青海师范大学,2010.
[162]金晶.SD安全数字卡电路的设计与验证.硕士论文,东南大学,2008.
[163]朱晓冬,王世明. MMC/SD卡控制器和仿真模型.电子测量技术,2005(5):67-68.
[164]唐磊,洪传荣,朱广信,徐红,常丽萍.基于FPGA的SD卡控制器设计.器件与电路.2011(3):29-31.
[2]张繁,刘笃仁. SOC设计面对的技术挑战.今日电子.2004,12:85-87.
[3]潘杰.聚芯SoC高性能访存技术研究.硕士论文,中国科学院研究生院(计算技术研究所),2006.
[4] Frank Rogin, Rolf Drechsler. Debugging at the Electronic System Level.Springer Netherlands.2010.
[5] J. D. Morison, A. S. Clarke. Ella2000: A Language for Electronic SystemDesign. McGraw-Hill, Inc. New York, NY, USA.2000.
[6] Synopsys LEDA User Guide. Version D-2010.03. March2010.
[7] Synopsys Design Compiler User Guide. Version D-2010.03-SP2, June2010.
[8] Cadence Encounter RTL Compiler Ultra User Guide. Product Version7.1.2.September2007.
[9] IEEE Standard Verilog Hardware Description Language. IEEE Std1364-2001.28September2001.
[10] IEEE Standard VHDL Language Reference Manual. IEEE Std.1076-1993.
[11]李晓维,吕涛,李华伟,李光辉.数字集成电路设计验证—量化评估、激励生成、形式化验证.科学出版社.2010.
[12] McCabe T. A complexity measure. IEEE Transactions on Software Engineering.vol.12(4),1976.
[13] Halstead M. Elements of Software Science. Elsevier North Holland, New York.1997.
[14] Shepperd. An evaluation of software product metrics. Information and softwaretechnology.1988,30(3):177-88.
[15] Myers G. An extension to the cyctomalic measure of Program complexity.SIGPLAN Notices.1977,12(10):77-79.
[16]朱云峰.代码复杂度度量与质量控制在日立项目中的应用.硕士论文,长春理工大学,2004年.
[17]冯欣.代码质量控制与复杂度测量在大型软件项目中的研究及应用.硕士论文,东北师范大学,2006年.
[18] M. Ljpow. Number of faults per line of code. IEEE Transactions on SoftwareEngineering.1982, SE-8(4):.437-9.
[19]李暾,屈婉霞,郭阳,刘功杰,李思昆.基于符号模拟和约束逻辑变成的RTL级Verilog谓词抽象方法.计算机学报.2007,30(7):1138-1144.
[20] Jaffar J, Maher M J. Constraint logic programming：A survey. The Journal ofLogic Programming.1994,14(19-20):503-582.
[21] Ubar R. Test synthesis with alternative graphs. IEEE Design&Test of Computers.1996,13(1):48-57.
[22] Waseem Muhammad, Sophie Coudert, Rabea Ameur-Boulifa, Renaud Pacalet.Separating Control and Data Processing in RT level Virtual IP Components.Proceedings of the2007Ph.D Research in Microelectronics and Electronicsconference, PRIME2007.2007:273-276.
[23] Yin Z G, Min Y H, Li X W.A novel RT-level behavioral description based ATPGmethod. Journal of Computer Science and Technology.2003,18(3):308-317.
[24]尹志刚,李华伟,李晓维.一种面向测试的RTL行为抽象与蕴涵方法.同济大学学报(自然科学版).2002,30(10):1199-1203.
[25]鲁巍,吕涛,杨修涛,李晓维. RTL可观测性语句覆盖评估方法.计算机辅助设计与图形学学报.2006,18(1):62-68.
[26] Mukherjee Biswarup, Dandapat Anup Kumar. Design of Combinational Circuitsby Cyclic Combinational Method for Low Power VLSI.2010InternationalSymposium on Electronic System Design. Bhubaneswar, India: IEEE.2010:107-112.
[27] Chan Terence. A robust multithreaded HDL/ESL simulator for deep submicronintegrated circuit designs.2012IEEE Asia Pacific Conference on Circuits andSystems, APCCAS2012. Kaohsiung, Taiwan: IEEE,2012:416-419.
[28] Huang Hsu-Yao, Huang Chi-Yuan, Chen Chung-Ho. Tile-based GPUoptimizations through ESL full system simulation.[C]//ISCAS2012-2012IEEE International Symposium on Circuits and Systems. Seoul, Korea: IEEE,2012:1327-1330.
[29] Chen Weiwei, D mer Rainer. An optimizing compiler for out-of-order parallelESL simulation exploiting instance isolation.17th Asia and South Pacific DesignAutomation Conference, ASP-DAC2012. Sydney, NSW, Australia: IEEE,2012:461-466.
[30] Yoshikawa Y. A binding algorithm in high-level synthesis for path delaytestability.201318th Asia and South Pacific Design Automation Conference(ASP-DAC2013). Yokohama, Japan: IEEE,2013:546-51.
[31] Neiroukh Osama, Edwards, Stephen A., Song Xiaoyu. An Efficient Algorithmfor the Analysis of Cyclic Circuits. Proceedings of the2006Emerging VLSITechnologies and Architectures. Klarlsruhe, Germany: IEEE,2006:303-308.
[32] Mentor Graphics Corporation CDC Compiler User Guide. Release2.3PartNumber224246May10,2005.
[33] T. Kapschitz, R. Ginosar. Formal Verification of Synchronizers. Conference ofCorrect Hardware Design and Verification Methods,2005.
[34] Bing Li, Chris Ka-Kei Kwok. Automatic Formal Verification of Clock DomainCrossing Signals. Proceedings of the Asia and South Pacific Design AutomationConference, ASP-DAC.2009:654-659.
[35]冯毅,易江芳,刘丹,佟冬,程旭.面向SoC系统芯片中跨时钟域设计的模型检验方法.电子学报.2008,36(5):886-892.
[36]冯毅,许经纬,易江芳,佟冬,程旭.面向模型检验的跨时钟域设计电路特性生成方法.电子学报.2009,37(2):258-265.
[37] Feng Yi, Zhou Zheng, Tong Dong, Cheng Xu. Clock domain crossing faultmodel and coverage metrics for validation of SoC design. Design, Automation&Test in Europe Conference&Exhibition. San Jose: EDA Consortium.2007:1385-1390.
[38] A. Chowdhary, S. Kale, et al. Extraction of Functional Regularity in DatapathCircuits. IEEE Trans. on Computer-Aided Design.1999,18(9):1279-1296.
[39] Angelo P.E. Rosiello, F. Ferrandi, D. Pandini, D. Sciuto. A Hash-based Approachfor Functional Regularity Extraction During Logic Synthesis. IEEE ComputerSocietyAnnual Symposium on VLSI. New York, IEEE.2007:92-97
[40]李长青,汪雪林等.辐射路匹配:从门级到功能模块级的子电路提取算法.计算机辅助设计与图形学学报,2006,18(9):1377-1382.
[41]潘伟涛,谢元斌,郝跃,史江一.二同构扩展数字集成电路规律性提取算法.西安电子科技大学学报(自然科学版).2009,36(3):452-462.
[42]潘伟涛,谢元斌,郝跃,史江一.基于扇形模板的数字集成电路规律性提取算法.电子学报. Vol.38, No.1. Jan.2010:199-203.
[43]潘伟涛,谢元斌,郝跃,史江义.基于启发式链搜索的频繁子电路提取算法.吉林大学学报(工学版).2011,41(6):1748-1753.
[44]潘伟涛,郝跃,谢元斌,史江义.小规模频繁子电路的规律性预提取算法.计算机辅助设计与图形学学报.2010,22(2):226-233,
[45] PAN Weitao,XIE Yuanbin,HAO Yue. An Algorithm for Chain-like FrequentSubcircuits Extraction in Digital Integrated Circuits. CHINESE JOURNAL OFCOMPUTATIONAL PHYSICS.2011,28(1):138-144.
[46] Synopsys Formality User Guide Version D-2010.03, March2010.
[47] Mentor Graphics FormalPro Datasheet.
[48] Hughes R B. Formal verification of equivalence in DSM designs usingformalProTM.
[49] Burch J R, Singhal V. Tight integration of combinational verification methods.Proceeding of IEEE/ACM International Conference on Computer-Aided Design,San Jose, CA, USA.1998:570-576.
[50] Anastasakis D, Damiano R, Ma H K T. A practical and efficient method forcompare-point matching. Proceeding of IEEE/ACM39th Design AutomationConference, New orleans, USA.2001:305-310.
[51] Shih-Chieh Wu, Chun-Yao Wang, and Yung-Chih Chen. Novel ProbabilisticCombinational Equivalence Checking. IEEE TRANSACTIONS ON VERYLARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL.16, NO.4, APRIL2008.365-375.
[52] Disch S, Schollm C. Combinational equivalence checking using incrementalSAT solving, output ordering, and resets. Proceeding of Asia and South PacificDesign Autonation Conference. Yokohama, Japan,2007:938-943.
[53] Mishchenko A, Chatterjee S, Brayton R. Improvements to combinationalequivalence checking. Proceeding of IEEE/ACM International Conference onComputer-Aided Design. San Jose, CA, USA,2006:836-843.
[54]翁延玲,葛海通,严晓浪,郑飞君.结合半加图的算术电路等价性验证技术.浙江大学学报(工学版).2008,42(8):1345-1349.
[55]翁延玲,葛海通,严晓浪.等价性验证中的自动算符排序.浙江大学学报(工学版).2007,41(6):886-889.
[56] Mukherjee R, Jain J, Pradhan D K. Functional learning: a new approach tolearning in digital circuits. Proceeding of IEEE VLSI Test Symposium. CherryHill, NJ, USA.1994:6-13.
[57] Kunz W, Menon P. Multi-level logic optimization by implication analysis.Proceeding of International Conference on Computer-Aided Design. San Jose,CA, USA.1994:6-13.
[58]何科.网络处理器高性能数据交换接口设计研究.硕士论文,西安电子科技大学,2011.
[59]谢元斌.异构多核网络安全处理器硬件优化技术研究.博士学位论文,西安电子科技大学,2011.
[60]我国自主开发的多核网络安全处理器填补国内该领域空白.[Online]:new.xinhuanet.com.2009.
[61]“清华天行”网络处理器鉴定.[Online]:www.sist.tsinghua.edu.cn.2006
[62]宋乾暾. JPEG2000中EBCOT编码的研究与实现.硕士学位论文,西安电子科技大学,2006.
[63]周正道.远程图像监控系统的研究和实现.硕士学位论文,西安电子科技大学,2003.
[64]朱珂.基于JPEG2000的静态图像压缩算法及VLSI实现的结构研究.博士论文,复旦大学,2004.
[65]刘海林.静止图像压缩研究-JPEG2000标准的分析与应用.硕士论文,成都理工大学,2002.
[66]郭杰.静止图像压缩结构设计与VLSI实现研究.博士论文,西安电子科技大学,2010.
[67]曲波. JPEG2000编码器中的高可靠码流组织VLSI设计.硕士论文,西安电子科技大学,2012.
[68]周宇. JPEG2000中EBCOT编码器的VLSI实现.硕士论文,西安电子科技大学,2009.
[69]万登峰.基于JPEG2000遥感图像压缩的应用研究.硕士论文,上海交通大学,2005年.
[70]李金佳. JPEG2000编码器中的高可靠码流组织VLSI设计.硕士论文,西安电子科技大学,2012.
[71]刘雷波. JPEG2000静止图像压缩关键技术研究及VLSI实现.博士论文,清华大学工学,2004.
[72]房琼. JPEG2000芯片设计及仿真方法研究.硕士论文,西安电子科技大学,2010.
[73]刘春风.基于ADV212的图像压缩编码系统设计.硕士论文,国防科学技术大学,2010.
[74] A.N. Skodras, C.A. Christopoulos, T. Ebrahimi. JPEG2000: The upcoming stillimage compression standard. Pattern Recognition Letters,2001,22(12):1337-1345.
[75]刘雷波,王学进,孟鸿鹰,王志华,陈弘毅,夏宇闻. JPEG2000小波变换器的VLSI结构设计.电子学报.2002,30(11):1609-1612.
[76]朱悦心,付昀,吴宗泽,郑南宁.基于多级查询表的JPEG2000位平面扫描优化方法.电子学报.2004,32(5):810-813.
[77]刘文松,朱恩,王健,徐龙涛,林叶. JPEG2000算术编码器的算法优化和VLSI设计.电子学报.2011,39(11):2486-2491.
[78] M.D. Adams and F. Kossentini.Jasper: a software-based JPEG-2000codecimplementation.Proc. IEEE Int. Conf. Image Processing, Sep.2004.2004,2:53-56.
[79] http://www.eepw.com.cn/article/86573.htm.
[80]江琳.兼容ARC指令集的RISC IP核的开发.硕士论文,哈尔滨工业大学,2007.
[81]郑伟,陈基禄.可配置、可扩展的处理器Xtens.微机发展.2002(2):88-91.
[82] Bill Pontikakis, Francois-R. Boyer, Yvon SavariaPerformance. Improvement ofConfigurable Processor Architectures Using a Variable Clock Period.Proceedings of the Fifth International Workshop on System-on-Chip forReal-Time Applications (IWSOC'05), Washington,2005. IEEE ComputerSociety,2005:454-458.
[83] http://www.eefocus.com/consumer-electronics/180634.
[84]毕萍萍.时钟控制单元代码自动生成技术的实现及验证.硕士论文,西安电子科技大学,2013.
[85]李凤伟.基于嵌入式系统的便携式学习电脑的应用开发.硕士论文,大连理工大学,2009.
[86]郑亮. SD/MMC控制器的设计与实现.硕士论文,厦门大学,2008.
[87]陈海生.基于STM32的TransFlash卡读写技术研究.硕士论文,哈尔滨工业大学,2009.
[88] Technical Committee SD Association. SD Host Controller SimplifiedSpecification Version1.00.2000.
[89] Technical Committee SD Association. SD Host Controller SimplifiedSpecification Version2.00.2006.
[90] Technical Committee SD Association. SD Host Controller SimplifiedSpecification Version3.00.2009.
[91]胡美群,夏银水,王伦耀.基于分支限界的关键路径求解算法.宁波大学学报(理工版).2011,24(2):37-41.
[92] Yaun-chung Hsu, Shangzhi Sun, David H.C. Finding The Longest Simple Path inCyclic Combinational Circuits. IEEE International Conference on ComputerDesign: VLSI in Computers and Processors. Austin, TX, USA.1998:530-535.
[93] Khaled R. Heloue, Sari Onaissi, Farid N. Najm. Efficient Block-BasedParameterized Timing Analysis Covering All Potentially Critical Paths. IEEETRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATEDCIRCUITS AND SYSTEMS.2012,31(4):472-484.
[94] Sharad Sinha, Udit Dhawan, Siew Kei Lam, et al. A Novel Binding Algorithm toReduce Critical Path Delay During High Level Synthesis.2011IEEE ComputerSocietyAnnual Symposium on VLSI. Chennai, India,2011:278-283.
[95] Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, et al. Path CriticalityComputation in Parameterized Statistical Timing Analysis Using a NovelOperator. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OFINTEGRATED CIRCUITS AND SYSTEMS.2012,31(4):497-508.
[96]郑四发,曹剑东,连小珉.复杂路网下多客户间最短路径的扇面Dijkstra算法.清华大学学报(自然科学版).2009,49(11):1834-1837.
[97] Osama Neiroukh, Stephen A. Edwards, Xiaoyu Song. Transforming CyclicCircuits Into Acyclic Equivalents. IEEE transaction on computer-aided design ofintegrated circuit and systems.2008,27(10):1775-1787.
[98] Riedel Marc D., Bruck Jehoshua. Cyclic Boolean circuits.Discrete AppliedMathematics.2012,160(13-14):1877-1900.
[99] Backes John D., Riedel Marc D.. The synthesis of cyclic dependencies withboolean satisfiability. ACM Transactions on Design Automation of ElectronicSystems.2012,17(4):1-24.
[100] Rivest, R.L.. The necessity of feedback in minimal monotone combinationalcircuits[J]. IEEE Transactions on Computers.1977,26(6):606–607.
[101] M. D. Riedel and J. Bruck. The synthesis of cyclic combinational circuits. Proc.40th Des. Autom. Conf.. Anaheim, CA.2003:163–168.
[102] Peter M. Maurer, Yun Sik Lee. Compiled unit-delay simulation for cyclic circuits.Proc. the IEEE SOUTHEASTCON '92. Birmingham, AL, USA.1992:184-188.
[103] Anand Raghunathan, Pranav Ashar, Sharad Malik. Test Generation for CyclicCombinational Circuits. IEEE Transactions on Computer-Aided Design ofIntegrated Circuits and Systems.1995,14(11):1408-1414.
[104] DeBenedictis E., Ghosh S., Yu M.-L. A novel algorithm for discrete-eventsimulation: asynchronous distributed discrete-event simulation algorithm forcyclic circuits using a dataflow network. Computer.1991,24(6):21-33.
[105] G. Berry. The foundations of Esterel. in Proof, Language, and Interac-tion:Essays in Honour of Robin Milner. Cambridge, MA: MIT Press.2000.
[106] Agarwal, Vineet, et al. An efficient combinationality check technique for thesynthesis of cyclic combinational circuits. in Proc. the Asia and South PacificDesign Automation Conference, ASP-DAC, Shanghai, China.2005,1:212-215.
[107] Chang Joon Lee, et al. A robust method for searching the smallest set of smallestrings with a path-included distance matrix. in Proc. the National Academy ofSciences of the United States ofAmerica.2009,106(41):17355-8,13.
[108] Edwards, S.A.. Making cyclic circuits acyclic. in Proc. Design AutomationConference. Anaheim, CA, USA.2003:159-62.
[109] S. Malik. Analysis of cyclic combinational circuits. IEEE Transactions onComputer-Aided Design of Integrated Circuits and Systems.1994,13(7):950-956.
[110] Malik Sharad. Analysis of cyclic combinational circuits. in Proc. the1993IEEE/ACM International Conference on Computer-Aided Design.1993:618-625.
[111] Srinivasan Arvind, Malik Sharad. Practical analysis of cyclic combinationalcircuits. in the Proc. the Custom Integrated Circuits Conference. San Diego, CA,USA.1996:381-384.
[112] E. B. Eichelberger. Hazard detection in combinational and sequential switchingcircuits. IBM J. Res. Develop.1965,9(2):90-99.
[113] T. R. Shiple. Formal analysis of synchronous circuits. Ph.D. dissertation, Univ.California, Berkeley, CA,1996.
[114] Shiple Thomas R., Berry Gerard, Touati Herve. Constructive analysis of cycliccircuits. in Proc. European Design and Test Conference. Paris, Fr..1996:328-333.
[115] L. Stok. False loops through resource sharing. in Proc. IEEE/ACM ICCAD, SanJose, CA.1992:345-348.
[116] A. Gupta, C. Selvidge. Acyclic modeling of combinational loops. in Proc.IEEE/ACM ICCAD. San Jose, CA.2005:343-347.
[117] Horton, J.D.. A polynomial-time algorithm to find the shortest cycle basis of agraph. SIAM Journal on Computing.1987,16(2):358-66.
[118] C. McCaw. Loops in directed combinational switching networks. Ph.D. Thesis,Stanford University,1963.
[119] Opencore. Available: http://opencores.org/.
[120]李瑞,张春元,罗莉.三种常用SoC片上总线的分析与比较.单片机与嵌入式系统应用,2004(2):5-8.
[121]邓崇亮,章焕昌. SoC片上五种总线标准的分析比较.百色学院学报.2008(3):50-55.
[122] A.Rincon, W.Lee, M.Slatery. The Changing Landscape of System-on-ChipDesign. Custom Integrated Circuits1999, Proceedings of the IEEE1999,5(3):83-90.
[123] ARM Corp．TheAMBA Specification Rev2.0.1999.
[124] Steve Furber. ARM System-on-Chip Architecture second edition[M].USA:Addison-Wesley Professional,2000.
[125] Patrick Pelgrims. Tom Tierens,Dries Driessens． Overview AMBA AvalonCoreConneet Wishbone.2003:2-6.
[126] IBM Corp．The CoreConnect Bus Architecture.1999.
[127]王庆成.面向IP包处理的硬件多线程处理器研究与设计2010-
[128]赵彦尚.网络处理器微引擎的设计、验证与实现.硕士论文,西安电子科技大学,2013.
[129]陈四强.基于Intel IXA的千兆以太路由器设计.硕士论文,电子科技大学,2003.
[130]董杰.多核网络处理器中定制控制处理器关键技术研究.硕士论文,西安电子科技大学,2011.
[131]关娜.网络处理器系统中SDR AM控制器电路设计与仲裁优化研究.硕士论文,西安电子科技大学,2010.
[132]安爱女.多核共享的高效存储控制模块研究与设计.硕士论文,西安电子科技大学,2011.
[133]余广明.基于片上多核系统高速数据交换接口的关键技术研究.硕士论文,西安电子科技大学,2013.
[134]孙杰. XDNP网络处理器快速总线接口FBI设计与实现.硕士论文,西安电子科技大学,2013.
[135]徐懿,杜高明,李丽,蒋召宇,张冰,高明伦.基于总线的片上多处理器SOC仲裁算法研究.仪器仪表学报2006,26(7):2415-2418.
[136]杨盛光,李丽,徐懿,张宇昂,娄孝祥,高明伦.基于拥塞预测的NoC自适应仲裁方法.计算机应用研究.2009,26(2):652-659.
[137]李耀荣,王兴军,梁利平. SoC总线仲裁算法的研究.片上系统SoC.2007,23(6-2):113-115.
[138]陈敬洋.基于多核包处理器的高速数据交换总线设计研究.硕士论文,西安电子科技大学,2011.
[139] Acharya, T., Tsai, P. S.. JPEG2000standard for image compression concepts,algorithms and VLSI architectures. Hoboken: John Wiley and Sons.2005.
[140] JPEG2000(2002) Part1020719(Final Publication Draft), ISO/IECJTC1/SC29/WG1N1636R, July2002.
[141] M. Rabbani, R. Joshi. An overview of the JPEG2000still image compressionstandard. Signal Processing: Image Communication,2002,17(1):3-48.
[142] A. Gupta, S. Nooshabadi, D. Taubman, M. Dyer. Realizing low-costhigh-throughput general-purpose block encoder for JPEG2000. IEEETransactions on Circuits and Systems for Video Technology.2006,16(7):843-858.
[143]雷磊. JPEG2000MQ编码器的高速VLSI设计与实现.硕士论文,中南大学,2010.
[144] Taubman D. S., Marcellin, M. W. JPEG2000: Image compression fundamenetals,standard and practice. Boston:Kluwer.2002.
[145] Minsoo Rhu, In-Cheol Park. Optimization of Arithmetic Coding for JPEG2000.IEEE Transactions on Circuits and Systems for Video Technology.2010,20(3):446-451.
[146]16Kishor Sarawadekar,Swapna Banerjee. VLSI design of memory-ef f cient,high-speed base line MQ coder for JPEG2000. Integration, the VLSI Journal.2012,45:1–8.
[147]17K. Liu, Y. Zhou, Y. Song Li, J.F. Ma. A high performance MQ encoderarchitecture in JPEG2000. Integration, the VLSI Journal.2010,43(3):305-317.
[148] Liu Wensong, Zhu En, Lin Ye, Sun Lei, Liu Jun. Design of JPEG2000ArithmeticCoder using Optimized Renormalization Procedure.2011InternationalConference on Multimedia and Signal Processing.2011,1:41-45.
[149] Nandini Ramesh Kumar, Wei Xiang, Yafeng Wang. Two-Symbol FPGAArchitecture for Fast Arithmetic Encoding in JPEG2000. Journal of SignalProcessing Systems.2012,69(2):213-224.
[150] M. Dyer, D. Taubman, S. Nooshabadi, A. Gupta. Concurrency techniques forarithmetic coding in JPEG2000. IEEE Transactions on Circuits and Systems.2006,53(6):1203–1213.
[151] N. Noikaew, O. Chitsobhuk.(2008). Dual symbol processing for MQ arithmeticcoder in JPEG2000. Congress on Image and Signal Processing CISP’08.2008,1:521–524.
[152] PENG Zhou, ZHAO Bao-jun. High-throughput Hardware Architecture of MQArithmetic Coder[C]. ICSP2010Proceedings,2010.2010:430-433.
[153] Minsoo Rhu, In-Cheol Park. Architecture Design of a High-PerformanceDual-Symbol Binary Arithmetic Coder for JPEG2000.2009IEEE InternationalConference on Image Processing.2009:2665-2668.
[154] Sarawadekar Kishor, Banerjee Swapna. Low-cost, high-performance VLSIdesign of an MQ coder for JPEG2000. ICSP2010Proceedings,2010:397-400.
[155] Wael M. El-Sharkasy, Mohamed E. Ragab.Hardware Modelling of JPEG2000MQ-Encoder.20124th International Conference on Intelli gent and AdvancedSystems (ICIA S2012).2012:707-712.
[156] MDyer, D Taubman, S Nooshabadi. Improved throughput arithmetic coder forJPEG2000. Proceedings of IEEE International Conference on Image Processing.USA: IEEE Press,2004,4:2817-2820.
[157] CYXiong, J HHou, et al. Efficient fast algorithmfor MQ arithmetic coder.Proceedings of IEEE Conference on Multimedia and Expo. USA:IEEE Press.2007:759-762.
[158] BMin, SYoon, J Ra, DSPark. Enhanced renormalization algorithm in MQ-coderof JPEG2000. Proceedings of International Symposium on InformationTechnology Convergence.USA: IEEE Press.2007:213-216.
[159] M. Dyer, S. Nooshabadi, D. Taubman. Design and analysis of system on a chipencoder for JPEG2000. IEEE Transactions on Circuits and Systems for VideoTechnology.2009,19(2):215–225.
[160] Y.Z. Zhang, C. Xu, W.T. Wang, L.B. Chen.(2007). Performance analysis andarchitec-ture design for parallel EBCOT encoder of JPEG2000. IEEETransactions on Circuits and Systems for Video Technology.2007,17(10):1336–1347.
[161]赵建飞.基于Simulink与AVR单片机的多接口音频系统的仿真与构建.硕士论文,青海师范大学,2010.
[162]金晶.SD安全数字卡电路的设计与验证.硕士论文,东南大学,2008.
[163]朱晓冬,王世明. MMC/SD卡控制器和仿真模型.电子测量技术,2005(5):67-68.
[164]唐磊,洪传荣,朱广信,徐红,常丽萍.基于FPGA的SD卡控制器设计.器件与电路.2011(3):29-31.