低功耗抗串扰总线编码研究与设计
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摘要
深亚微米片上总线的串扰延迟、功耗和噪声已成为限制总线性能和可靠性的关键因素。通过低功耗编码、串扰抑制编码和检错/纠错编码可有效解决这些问题,从而提高总线的性能和可靠性并降低总线动态功耗。
本文在研究国内外总线编码最新进展的基础上,归纳总结了总线编码的一般概念和研究方法。根据深亚微米总线模型和统一的总线编码框架,提出了一种低功耗抗串扰自适应时空总线编码方法以降低深亚微米总线的串扰延迟和功耗。采用SPEC标准数据源对算法进行了评估,该方法在消除恶性串扰的同时使总线数据吞吐率提高了62.59%~81.62%,功耗比同类方法降低14.63%~54.67%,对于32位数据总线,仅需7根冗余线,在动态功耗、布线资源和性能方面获得了有效的优化。此外,采用IP设计技术将该算法映射成可重用的硬宏模块,并对其时序、面积和功耗等关键特性进行版图精准的评估,同时还建立了其整体验证环境,从物理实现的层次验证该算法的可行性及有效性,初步探讨了总线编解码算法的物理实现、验证与应用。
Crosstalk induced delay, power consumption, and noise in deep submicron on-chip buses are the main facts restricting the performance and reliability of the buses. Through low power coding, crosstalk avoidance coding, and error detecting (or correcting) coding, these issues can be solved effectively. Consequently, the performance and reliability of buses are improved considerably while dynamic power consumed in buses is reduced.
Based on the recent trend of the bus coding researches both at home and abroad, the general concepts and researching methods of bus coding are summarized. By employing deep submicron bus model and the unified bus coding framework, a low power adaptive spatio-temporal bus coding scheme for crosstalk avoidance is proposed to reduce crosstalk induced delay and power consumption in deep submicron buses. The proposed scheme is evaluated using the SPEC benchmarks. The results show that the proposed scheme improves the throughput by 62.59% to 81.62% over the un-coded approach and reduces the power consumption by 14.63% to 54.67% compared to the other similar schemes while eliminating the worst case crosstalk with only 7 wires overhead for a 32 bit bus. The scheme achieves a good enhancement in dynamic power, wiring overhead, and performance. Furthermore, the proposed scheme is mapped into a reusable hard macro block by using IP design technology. A layout-accurate analysis is performed for the critical character, timing, area, and power of the macro. Meanwhile, a whole verification environment, including encoder and decoder, was established for evaluating the flexibility and effectiveness of the proposed scheme from a physical implementation level. Preliminary studies were completed on the physical implementation, verification, and application of bus coding schemes.
本文在研究国内外总线编码最新进展的基础上,归纳总结了总线编码的一般概念和研究方法。根据深亚微米总线模型和统一的总线编码框架,提出了一种低功耗抗串扰自适应时空总线编码方法以降低深亚微米总线的串扰延迟和功耗。采用SPEC标准数据源对算法进行了评估,该方法在消除恶性串扰的同时使总线数据吞吐率提高了62.59%~81.62%,功耗比同类方法降低14.63%~54.67%,对于32位数据总线,仅需7根冗余线,在动态功耗、布线资源和性能方面获得了有效的优化。此外,采用IP设计技术将该算法映射成可重用的硬宏模块,并对其时序、面积和功耗等关键特性进行版图精准的评估,同时还建立了其整体验证环境,从物理实现的层次验证该算法的可行性及有效性,初步探讨了总线编解码算法的物理实现、验证与应用。
Crosstalk induced delay, power consumption, and noise in deep submicron on-chip buses are the main facts restricting the performance and reliability of the buses. Through low power coding, crosstalk avoidance coding, and error detecting (or correcting) coding, these issues can be solved effectively. Consequently, the performance and reliability of buses are improved considerably while dynamic power consumed in buses is reduced.
Based on the recent trend of the bus coding researches both at home and abroad, the general concepts and researching methods of bus coding are summarized. By employing deep submicron bus model and the unified bus coding framework, a low power adaptive spatio-temporal bus coding scheme for crosstalk avoidance is proposed to reduce crosstalk induced delay and power consumption in deep submicron buses. The proposed scheme is evaluated using the SPEC benchmarks. The results show that the proposed scheme improves the throughput by 62.59% to 81.62% over the un-coded approach and reduces the power consumption by 14.63% to 54.67% compared to the other similar schemes while eliminating the worst case crosstalk with only 7 wires overhead for a 32 bit bus. The scheme achieves a good enhancement in dynamic power, wiring overhead, and performance. Furthermore, the proposed scheme is mapped into a reusable hard macro block by using IP design technology. A layout-accurate analysis is performed for the critical character, timing, area, and power of the macro. Meanwhile, a whole verification environment, including encoder and decoder, was established for evaluating the flexibility and effectiveness of the proposed scheme from a physical implementation level. Preliminary studies were completed on the physical implementation, verification, and application of bus coding schemes.
引文
[1] Sridhara S R, Shanbhag N R. Coding for system-on-chip networks: A unified framework[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2005, 13(6): 655-667.
[2] International Technology Roadmap for Semiconductors (ITRS). Interconnect. http://www.itrs.net/Links/2005ITRS/, 2006, 12.
[3] Hui G, Parameswaran S. Shifted gray encoding to reduce instruction memory address bus switching for low-power embedded systems[J]. Journal of Systems Architecture. 2010, 56(4-6): 180-190.
[4] Ji G, Hui G. A segmental bus-invert coding method for instruction memory data bus power efficiency[C]. Taipei, Taiwan: Institute of Electrical and Electronics Engineers Inc., 2009: 137-140.
[5] Zhang Y, Lach J, Skadron K, et al. Odd/even bus invert with two-phase transfer for buses with coupling[C]. Monterey, CA, United states: Institute of Electrical and Electronics Engineers Inc., 2002: 80-83.
[6] Sainarayanan K S, Ravindra J V R, Srinivas M B. A novel, coupling driven, low power bus coding technique for minimizing capacitive crosstalk in VLSI interconnects[C]. Piscataway, NJ, USA: IEEE, 2006: 4155-4158.
[7] Cheng K C, Jou J Y. Crosstalk-avoidance coding for low-power on-chip bus[C]. St. Julian's, Malta: Inst. of Elec. and Elec. Eng. Computer Society, 2008: 1051-1054.
[8] Sotiriadis P P, Chandrakasan A. Reducing bus delay in submicron technology using coding[C]. Piscataway, NJ, USA: IEEE, 2001: 109-114.
[9] Mehendale M, Sherlekar S D, Venkatesh G. Extensions to programmable DSP architectures for reduced power dissipation[C]. Los Alamitos, CA, USA: IEEE Comput. Soc, 1997: 37-42.
[10] Benini L, De Micheli G, Macii E, et al. Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems[C]. Los Alamitos, CA, USA: IEEE Comput. Soc. Press, 1997: 77-82.
[11] Aghaghiri Y, Fallah F, Pedram M. Irredundant address bus encoding for low power[C]. Huntington Beach, CA, United states: Institute of Electrical and Electronics Engineers Inc., 2001: 182-187.
[12] Aghaghiri Y, Fallah F, Pedram M. ALBORZ: Address Level Bus PowerOptimization[C]. Los Alamitos, CA, USA: IEEE Comput. Soc, 2002: 470-475.
[13] Stan M R, Burleson W P. Bus-invert coding for low-power I/O[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 1995, 3(1): 49-58.
[14] Komatsu S, Ikeda M, Asada K. Low power chip interface based on bus data encoding with adaptive code-book method[C]. Los Alamitos, CA, USA: IEEE Comput. Soc, 1999: 368-371.
[15] Victor B, Keutzer K. Bus encoding to prevent crosstalk delay[C]. San Jose, CA, United states: Institute of Electrical and Electronics Engineers Computer Society, 2001: 57-63.
[16] Lyuh C G, Kim T. Low-power bus encoding with crosstalk delay elimination[J]. IEE Proceedings-Computers and Digital Techniques. 2006, 153(2): 93-100.
[17] Philippe J M, Pillement S, Sentieys O. Area efficient temporal coding schemes for reducing crosstalk effects[C]. Los Alamitos, CA, USA: IEEE Computer Society, 2006: 334-339.
[18] Shen J S, Hsiungt P A, Chang K C. A novel spatio-temporal adaptive bus encoding for reducing crosstalk interferences with trade-offs between performance and reliability[C]. Hsinchu, Taiwan: Inst. of Elec. and Elec. Eng. Computer Society, 2008: 1-8.
[19] Kornaros G. Temporal coding schemes for energy efficient data transmission in systems-on-chip[C]. Ancona, Italy: IEEE Computer Society, 2009: 111-118.
[20] Li L, Vijaykrishnan N, Kandemir M, et al. A crosstalk aware interconnect with variable cycle transmission[C]. Paris, France: Institute of Electrical and Electronics Engineers Computer Society, 2004: 102-107.
[21] Sainarayanan K S, Raghunandan C, Srinivas M B. Delay and power minimization in VLSI interconnects with spatio-temporal bus-encoding scheme[C]. Porto Alegre, Brazil: Inst. of Elec. and Elec. Eng. Computer Society, 2007: 401-406.
[22] Hegde R, Shanbhag N R. Toward achieving energy efficiency in the presence of deep submicron noise[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2000, 8(4): 379-391.
[23] Rossi D, Metra C, Nieuwland A K, et al. Exploiting ECC redundancy to minimize crosstalk impact[J]. IEEE Design & Test of Computers. 2005, 22(1): 59-70.
[24] Patel K N, Markov I L. Error-correction and crosstalk avoidance in DSM busses[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2004, 12(10): 1076-1080.
[25] Rossi D, Nieuwland A K, Katoch A, et al. New ECC for crosstalk impactminimization[J]. IEEE Design and Test of Computers. 2005, 22(4): 340-348.
[26] Murali S, Theocharides T, Vijaykrishnan N, et al. Analysis of error recovery schemes for networks on chips[J]. IEEE Design and Test of Computers. 2005, 22(5): 434-442.
[27] Rossi D, Angelini P, Metra C. Configurable error control scheme for NoC signal integrity[C]. Piscataway, NJ, USA: IEEE, 2007: 31-36.
[28] Ganguly A, Pande P P, Belzer B. Crosstalk-aware channel coding schemes for energy efficient and reliable NOC interconnects[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2009, 17(11): 1626-1639.
[29]梁宇,韩奇,魏同立,等.一种基于聚类的Bus-Invert低功耗编码方法[J].固体电子学研究与进展. 2001, (02): 176-181.
[30]孙海珺,邵志标, Haijun S, et al.基于自适应重排的低功耗地址总线编码[J].西安交通大学学报. 2006, 40(4): 394-397.
[31]胡国兴,沈海斌.低翻转率的SoC总线组合编码算法[J].电子器件. 2006, (04): 1239-1241.
[32]刘毅,王乃迪,杨银堂.基于短循环程序特征的多模式低功耗编码算法[J].微电子学与计算机. 2008, (02): 104-106.
[33]秦骅,傅宇卓,赵峰.一种深亚微米工艺下的总线低功耗编码方案[J].信息技术. 2008, (06): 62-64.
[34]彭永克,毛志刚.改进的BI低功耗总线编码[J].微处理机. 2010, (01): 27-29.
[35] Sotiriadis P P, Chandrakasan A P. A bus energy model for deep submicron technology[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2002, 10(3): 341-350.
[36] Sotiriadis P P, Chandrakasan A. Reducing bus delay in submicron technology using coding[C]. Piscataway, NJ, USA: IEEE, 2001: 109-114.
[37] Fornaciari W, Polentarutti M, Sciuto D, et al. Power optimization of system-level address buses based on software profiling[C]. New York, NY, USA: ACM, 2000: 29-33.
[38] Arunachalam R, Acar E, Nassif S R. Optimal shielding/spacing metrics for low power design[C]. Los Alamitos, CA, USA: IEEE Comput. Soc, 2003: 167-172.
[39] Pande P P, Ganguly A, Zhu H, et al. Energy reduction through crosstalk avoidance coding in networks on chip[J]. Journal of Systems Architecture. 2008, 54(3-4): 441-451.
[40] Duan C, Cordero C V, Khatri S P. Efficient on-chip crosstalk avoidance CODEC design[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems.2009, 17(4): 551-560.
[41] Pillement S, Sentieys O, Philippe J M. Spatio-temporal coding to improve speed and noise tolerance of on-chip interconnect[J]. Microelectronics Journal. 2010, 41(8): 480-486.
[42] Halak B, Yakovlev A. Throughput optimization for area-constrained links with crosstalk avoidance methods[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2010, 18(6): 1016-1019.
[43] Singh H, Rao R, Agarwal K, et al. Dynamically pulsed MTCMOS with bus encoding for reduction of total power and crosstalk noise[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2010, 18(1): 166-170.
[44]刘毅,杨银堂,梅伟锋,等.一种NoC路由器间互连线的自适应驱动方法[J].西安电子科技大学学报. 2010, 37(01): 28-32.
[45] Nanoscale Integration and Modeling (NIMO) Group. Predictive Technology Model. http://ptm.asu.edu/, 2010, 3.
[46] SPEC. SPEC CPU2000 Benchmark. http://www.spec.org/, 2010, 3.
[47] Sotiriadis P P, Chandrakasan A P. Bus Energy Reduction by Transition Pattern Coding Using a Detailed Deep Submicrometer Bus Model[J]. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications. 2003, 50(10): 1280-1295.
[48]柴远波,张兴明.现代SoC设计技术[M].北京:电子工业出版社, 2009: 168-169.
[49]牛风举,刘元成,朱明程.基于IP复用的数字IC设计技术[M].北京:电子工业出版社, 2003: 180-185.
[50]陈春章,艾霞,王国雄.数字集成电路物理设计[M].北京:科学出版社, 2008: 56-59.
[51] Maliniak D. The truth about design for manufacturing[J]. Electronic Design. 2005, 53(21): 47-52.
[52] Bhasker J, Chadha R. Static Timing Analysis for Nanometer Designs[M]. New York: Springer, 2009: 120-121.
[53] Synopsys Inc. Astro Interactive Ultra User Guide. http://www.synopsys.com, 2007, 5.
[2] International Technology Roadmap for Semiconductors (ITRS). Interconnect. http://www.itrs.net/Links/2005ITRS/, 2006, 12.
[3] Hui G, Parameswaran S. Shifted gray encoding to reduce instruction memory address bus switching for low-power embedded systems[J]. Journal of Systems Architecture. 2010, 56(4-6): 180-190.
[4] Ji G, Hui G. A segmental bus-invert coding method for instruction memory data bus power efficiency[C]. Taipei, Taiwan: Institute of Electrical and Electronics Engineers Inc., 2009: 137-140.
[5] Zhang Y, Lach J, Skadron K, et al. Odd/even bus invert with two-phase transfer for buses with coupling[C]. Monterey, CA, United states: Institute of Electrical and Electronics Engineers Inc., 2002: 80-83.
[6] Sainarayanan K S, Ravindra J V R, Srinivas M B. A novel, coupling driven, low power bus coding technique for minimizing capacitive crosstalk in VLSI interconnects[C]. Piscataway, NJ, USA: IEEE, 2006: 4155-4158.
[7] Cheng K C, Jou J Y. Crosstalk-avoidance coding for low-power on-chip bus[C]. St. Julian's, Malta: Inst. of Elec. and Elec. Eng. Computer Society, 2008: 1051-1054.
[8] Sotiriadis P P, Chandrakasan A. Reducing bus delay in submicron technology using coding[C]. Piscataway, NJ, USA: IEEE, 2001: 109-114.
[9] Mehendale M, Sherlekar S D, Venkatesh G. Extensions to programmable DSP architectures for reduced power dissipation[C]. Los Alamitos, CA, USA: IEEE Comput. Soc, 1997: 37-42.
[10] Benini L, De Micheli G, Macii E, et al. Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems[C]. Los Alamitos, CA, USA: IEEE Comput. Soc. Press, 1997: 77-82.
[11] Aghaghiri Y, Fallah F, Pedram M. Irredundant address bus encoding for low power[C]. Huntington Beach, CA, United states: Institute of Electrical and Electronics Engineers Inc., 2001: 182-187.
[12] Aghaghiri Y, Fallah F, Pedram M. ALBORZ: Address Level Bus PowerOptimization[C]. Los Alamitos, CA, USA: IEEE Comput. Soc, 2002: 470-475.
[13] Stan M R, Burleson W P. Bus-invert coding for low-power I/O[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 1995, 3(1): 49-58.
[14] Komatsu S, Ikeda M, Asada K. Low power chip interface based on bus data encoding with adaptive code-book method[C]. Los Alamitos, CA, USA: IEEE Comput. Soc, 1999: 368-371.
[15] Victor B, Keutzer K. Bus encoding to prevent crosstalk delay[C]. San Jose, CA, United states: Institute of Electrical and Electronics Engineers Computer Society, 2001: 57-63.
[16] Lyuh C G, Kim T. Low-power bus encoding with crosstalk delay elimination[J]. IEE Proceedings-Computers and Digital Techniques. 2006, 153(2): 93-100.
[17] Philippe J M, Pillement S, Sentieys O. Area efficient temporal coding schemes for reducing crosstalk effects[C]. Los Alamitos, CA, USA: IEEE Computer Society, 2006: 334-339.
[18] Shen J S, Hsiungt P A, Chang K C. A novel spatio-temporal adaptive bus encoding for reducing crosstalk interferences with trade-offs between performance and reliability[C]. Hsinchu, Taiwan: Inst. of Elec. and Elec. Eng. Computer Society, 2008: 1-8.
[19] Kornaros G. Temporal coding schemes for energy efficient data transmission in systems-on-chip[C]. Ancona, Italy: IEEE Computer Society, 2009: 111-118.
[20] Li L, Vijaykrishnan N, Kandemir M, et al. A crosstalk aware interconnect with variable cycle transmission[C]. Paris, France: Institute of Electrical and Electronics Engineers Computer Society, 2004: 102-107.
[21] Sainarayanan K S, Raghunandan C, Srinivas M B. Delay and power minimization in VLSI interconnects with spatio-temporal bus-encoding scheme[C]. Porto Alegre, Brazil: Inst. of Elec. and Elec. Eng. Computer Society, 2007: 401-406.
[22] Hegde R, Shanbhag N R. Toward achieving energy efficiency in the presence of deep submicron noise[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2000, 8(4): 379-391.
[23] Rossi D, Metra C, Nieuwland A K, et al. Exploiting ECC redundancy to minimize crosstalk impact[J]. IEEE Design & Test of Computers. 2005, 22(1): 59-70.
[24] Patel K N, Markov I L. Error-correction and crosstalk avoidance in DSM busses[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2004, 12(10): 1076-1080.
[25] Rossi D, Nieuwland A K, Katoch A, et al. New ECC for crosstalk impactminimization[J]. IEEE Design and Test of Computers. 2005, 22(4): 340-348.
[26] Murali S, Theocharides T, Vijaykrishnan N, et al. Analysis of error recovery schemes for networks on chips[J]. IEEE Design and Test of Computers. 2005, 22(5): 434-442.
[27] Rossi D, Angelini P, Metra C. Configurable error control scheme for NoC signal integrity[C]. Piscataway, NJ, USA: IEEE, 2007: 31-36.
[28] Ganguly A, Pande P P, Belzer B. Crosstalk-aware channel coding schemes for energy efficient and reliable NOC interconnects[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2009, 17(11): 1626-1639.
[29]梁宇,韩奇,魏同立,等.一种基于聚类的Bus-Invert低功耗编码方法[J].固体电子学研究与进展. 2001, (02): 176-181.
[30]孙海珺,邵志标, Haijun S, et al.基于自适应重排的低功耗地址总线编码[J].西安交通大学学报. 2006, 40(4): 394-397.
[31]胡国兴,沈海斌.低翻转率的SoC总线组合编码算法[J].电子器件. 2006, (04): 1239-1241.
[32]刘毅,王乃迪,杨银堂.基于短循环程序特征的多模式低功耗编码算法[J].微电子学与计算机. 2008, (02): 104-106.
[33]秦骅,傅宇卓,赵峰.一种深亚微米工艺下的总线低功耗编码方案[J].信息技术. 2008, (06): 62-64.
[34]彭永克,毛志刚.改进的BI低功耗总线编码[J].微处理机. 2010, (01): 27-29.
[35] Sotiriadis P P, Chandrakasan A P. A bus energy model for deep submicron technology[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2002, 10(3): 341-350.
[36] Sotiriadis P P, Chandrakasan A. Reducing bus delay in submicron technology using coding[C]. Piscataway, NJ, USA: IEEE, 2001: 109-114.
[37] Fornaciari W, Polentarutti M, Sciuto D, et al. Power optimization of system-level address buses based on software profiling[C]. New York, NY, USA: ACM, 2000: 29-33.
[38] Arunachalam R, Acar E, Nassif S R. Optimal shielding/spacing metrics for low power design[C]. Los Alamitos, CA, USA: IEEE Comput. Soc, 2003: 167-172.
[39] Pande P P, Ganguly A, Zhu H, et al. Energy reduction through crosstalk avoidance coding in networks on chip[J]. Journal of Systems Architecture. 2008, 54(3-4): 441-451.
[40] Duan C, Cordero C V, Khatri S P. Efficient on-chip crosstalk avoidance CODEC design[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems.2009, 17(4): 551-560.
[41] Pillement S, Sentieys O, Philippe J M. Spatio-temporal coding to improve speed and noise tolerance of on-chip interconnect[J]. Microelectronics Journal. 2010, 41(8): 480-486.
[42] Halak B, Yakovlev A. Throughput optimization for area-constrained links with crosstalk avoidance methods[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2010, 18(6): 1016-1019.
[43] Singh H, Rao R, Agarwal K, et al. Dynamically pulsed MTCMOS with bus encoding for reduction of total power and crosstalk noise[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2010, 18(1): 166-170.
[44]刘毅,杨银堂,梅伟锋,等.一种NoC路由器间互连线的自适应驱动方法[J].西安电子科技大学学报. 2010, 37(01): 28-32.
[45] Nanoscale Integration and Modeling (NIMO) Group. Predictive Technology Model. http://ptm.asu.edu/, 2010, 3.
[46] SPEC. SPEC CPU2000 Benchmark. http://www.spec.org/, 2010, 3.
[47] Sotiriadis P P, Chandrakasan A P. Bus Energy Reduction by Transition Pattern Coding Using a Detailed Deep Submicrometer Bus Model[J]. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications. 2003, 50(10): 1280-1295.
[48]柴远波,张兴明.现代SoC设计技术[M].北京:电子工业出版社, 2009: 168-169.
[49]牛风举,刘元成,朱明程.基于IP复用的数字IC设计技术[M].北京:电子工业出版社, 2003: 180-185.
[50]陈春章,艾霞,王国雄.数字集成电路物理设计[M].北京:科学出版社, 2008: 56-59.
[51] Maliniak D. The truth about design for manufacturing[J]. Electronic Design. 2005, 53(21): 47-52.
[52] Bhasker J, Chadha R. Static Timing Analysis for Nanometer Designs[M]. New York: Springer, 2009: 120-121.
[53] Synopsys Inc. Astro Interactive Ultra User Guide. http://www.synopsys.com, 2007, 5.