GPS接收机ADC关键单元的研究与设计
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摘要
在无线通信领域中,随着GPS的不断发展,对模数转换器的性能也提出了更高的要求。模数转换器是模拟信号和数字信号之间的转换界面。在GPS射频接收机系统中,混频器降频得到的模拟信号经过模数转换器转换为数字信号送入下一级进行基带处理。通过与众多CMOS模数转换器结构相比较,流水线ADC的优越性在于保证高速工作的同时,可实现8位以上高分辨率,并且大大减少了比较器个数,从而减少了面积,降低了功耗。同时随着集成电路工艺的不断进步,对电压更低、尺寸更小的混合信号系统的研究也越显必要。因此针对上述需求,该论文完成了1.5比特/级流水线结构模数转换器的关键单元电路的研究与设计。
首先,本文利用Matlab中的Simulink工具对ADC进行系统级仿真。搭建流水线ADC的系统级模块并验证了其可行性;根据分析电路中的噪声仿真得到了电容失配、运放增益误差、失调电压等因素对级间转换电路输出范围的影响;指导电路级设计采用高性能运放、版图级设计对电容匹配的关注。
其次,在Cadence仿真环境中基于SMIC提供的1.8V单电源0.18μm CMOS混合信号工艺,对增益提高型运算放大器、采样保持电路、子ADC电路、MDAC电路进行研究与设计,最后给出了运放、采样保持电路的版图设计与后仿真结果。
本文采用了电容翻转式采样保持电路,利用增益提高型运放的高增益与较大带宽的优点实现了10位精度、40MHz采样频率的指标要求;根据S/H电路的设计思想完成了MDAC电路的设计,并实现级间转换的功能;采用动态比较器实现了子ADC电路的功能要求。最终完成了论文设计要求。
With the development of GPS receiver in wireless communication system, the high performance analog-to-digital systems are demanded. ADC is the interface between analog signal and digital signal. In the GPS system, the analog signal coming from Mixer is transferred into digital signal, and then sent to Base band. Comparing with other most ADC architecture, the pipelined ADC can achieve high speed and high resolution. Furthermore, the number of comparators will be decreased, so as to the area. Meanwhile, with the development of technology of IC, lower voltage and smaller mix-signal system is more important. In this design, we introduce the unit circuits of pipelined ADC whit 1.5 bit per stage.
First, the Matlab-Simulink tool was used in ADC's system level simulation, the model of pipelined ADC is established and proofed, the influence of offset voltage, offset capacitor and gain error to output range of pipelined stages was discussed, the high performance operational amplifier was employed in circuit design and capacitor matching was considered in layout design.
Second, the circuit was designed in SMIC 0.18μm mixed CMOS technology and stimulated by Cadence Specter in this paper. The analysis and design of S/H, subADC, MDAC were presented. Finally, the and layout and post simulation are shown in this paper.
The flip-flop S/H circuit with the advantages of high gain and wideband of gain-boosting operation amplifier were used to achieve 10-bit, 40MHz specifications required in the paper, the ideal of S/H was employed in the design of MDAC circuit, dynamic comparator was use in the design of sub ADC. The simulation results shown that the circuits meet the required specifications.
首先,本文利用Matlab中的Simulink工具对ADC进行系统级仿真。搭建流水线ADC的系统级模块并验证了其可行性;根据分析电路中的噪声仿真得到了电容失配、运放增益误差、失调电压等因素对级间转换电路输出范围的影响;指导电路级设计采用高性能运放、版图级设计对电容匹配的关注。
其次,在Cadence仿真环境中基于SMIC提供的1.8V单电源0.18μm CMOS混合信号工艺,对增益提高型运算放大器、采样保持电路、子ADC电路、MDAC电路进行研究与设计,最后给出了运放、采样保持电路的版图设计与后仿真结果。
本文采用了电容翻转式采样保持电路,利用增益提高型运放的高增益与较大带宽的优点实现了10位精度、40MHz采样频率的指标要求;根据S/H电路的设计思想完成了MDAC电路的设计,并实现级间转换的功能;采用动态比较器实现了子ADC电路的功能要求。最终完成了论文设计要求。
With the development of GPS receiver in wireless communication system, the high performance analog-to-digital systems are demanded. ADC is the interface between analog signal and digital signal. In the GPS system, the analog signal coming from Mixer is transferred into digital signal, and then sent to Base band. Comparing with other most ADC architecture, the pipelined ADC can achieve high speed and high resolution. Furthermore, the number of comparators will be decreased, so as to the area. Meanwhile, with the development of technology of IC, lower voltage and smaller mix-signal system is more important. In this design, we introduce the unit circuits of pipelined ADC whit 1.5 bit per stage.
First, the Matlab-Simulink tool was used in ADC's system level simulation, the model of pipelined ADC is established and proofed, the influence of offset voltage, offset capacitor and gain error to output range of pipelined stages was discussed, the high performance operational amplifier was employed in circuit design and capacitor matching was considered in layout design.
Second, the circuit was designed in SMIC 0.18μm mixed CMOS technology and stimulated by Cadence Specter in this paper. The analysis and design of S/H, subADC, MDAC were presented. Finally, the and layout and post simulation are shown in this paper.
The flip-flop S/H circuit with the advantages of high gain and wideband of gain-boosting operation amplifier were used to achieve 10-bit, 40MHz specifications required in the paper, the ideal of S/H was employed in the design of MDAC circuit, dynamic comparator was use in the design of sub ADC. The simulation results shown that the circuits meet the required specifications.
引文
[1]洪志良.模拟集成电路分析与设计.第一版.北京.科学出版社.2005.pp.194-198
[2]L.Sumanen,M.Waltari,K.Halonen."A 10-bit 200MS/s CMOS Parallel Pipeline A/D Converter".IEEE J.Solid-State Circuits,Jul.2001,36(7).pp.1048-1055
[3]Le H.P.,Zayegh A.Singh J."A 12-bit high performance low cost pipeline ADC".Proc.IEEE International Conference on Electronics Circuits and Systems,14-17 Dec.2003,Vol.2.pp.471-474
[4]徐世六.“高速A/D转换器技术及其产品发展研究”.微电子学.2004,12,34(6).pp.595-606
[5]陈曦,何乐年,张鲁等.“基于0.6um工艺的流水线模数转换器设计”.浙江人学学报(工学版).2006,40(6).pp.1080-1084
[6]S.M.Yoo,J.B.Park,S.H.Lee."A 2.5-V 10-bit 120M Sample/s CMOS Pipelined ADC based on Merger-capacitor switching".Circuits and SystemsⅡ:Express Briefs,IEEE Trans.,2004,51(5).pp.269-275
[7]程闪峰,张洁,阂吴.“低功耗33MHz采样频率,10比特流水线结构的模数转换器”.复旦大学学报(自然科学版).2001,40(3).pp.335-341
[8]Boris Murmann,Bernhard E.Boser."DIGITALLY ASSISTED PIPELINE ADCs".New York,Boston,Dordrecht,London,Moscow.Kluwer Academic Publishers.2004.pp.5-33
[9]Mikko Waltari."CIRCUIT TECHNIQUES FOR LOW-VOLTAGE AND HIGH-SPEED A/D CONVERTERS".[Dissertation].Helsinki University of Technology Department of Electrical and Communications Engineering.Electronic Circuit Design Laboratory.2002.pp.21-96
[10]R.J.Baker.沈树群,李国华,汤静.CMOS:混合信号电路设计.第一版.北京.科学出版社.2005年.pp.17-66
[11]Andrew M.Abo,Paul R.Gray,"A 1.5V,10-bit,14.3-MS/s CMOS Pipeline Analog-to-Digital Converter",IEEE Journal of Solid-State Circuits,vol.34,no.5,May.1999.20-52
[12]Hui Pan,Masahiro Segami,Michael Choi,Jing Cao,Asad A.Abidi."A 3.3-V 12-b 50Ms/s A/D Converterin 0.6umCMOS with over 80-db SFDR".IEEE J.Solid-State Circuits,vol.35,NO.12.December 2000
[13]S.H.Lewise."10 bit 20M sample/s analog-to-digital converter",IEEE J.Solid-State Circuits,vol.27.pp.351-358
[14]Keiichi Kusumoto,Akira Matsuzawa,Kenji Murata,"A 10-b 20-MHz 30-mW Pipelined Interpolating CMOS ADC".IEEE J.Solid-State Circuits
[15]Lin J.Haroun B."An Embedded 0.8V/480μW 6b/22MHz Flash ADC in 0.13μm Digital CMOS Process using Nonlinear Double-Interpolation Technique".ISSCC Dig.of Tec.Papers,Feb.2002.pp.307-309
[16]E.J.Siragusa,I.Galton."Gain Error Correction Technique for Pipelined Analog-To-Digital Convers".Electron Letters,2002,36(7).pp.617-618
[17]G.David."A10-bit,3V,100MS/s pipelined ADC".IEEE Custom Integrated Circuits Conferenee,Orlando,Florida:IEEE Solid-State Circuits Soeiety,2000.pp.257-260
[18]李福乐.“适宜于系统集成的高速高精度模数转换电路的设计技术研究”.[博士论文],清华大学,2003
[19]Berkeley EECS247,Analysis and Design of VLSI Analog-Digital Interface Circuits,IC776CA.
[20]黄飞鹏,王静光,何济柔等.“一种57.6mW,10位,50MS/s流水线操作CMOSA/D转换器”[J],半导体学报,2005,26(11)pp.2230-2235
[21]毕查德·拉扎维著.陈贵灿,程军等译.模拟CMOS集成电路设计[M].第一版.西安.西安交通大学出版社.2003.pp.334-345,266-267
[22]Yang W,Kelly D."A 3-V 340mW 14-b 75Msample/s CMOS ADC with 85-dB SFDR at Nyquist Input"[J].IEEE J Solid-State Circuits,2001,36(12)pp.1931-1936
[23]Kamath B Y,Meyer R G,Gray P R."Relationship Between Frequency Response and Settling Time of Operational Amplifiers"[J].IEEE J Solid-State Circuits,1974,9(12)pp.347-352
[24]Das M."Improved Design Criteria of Gain-Boosted CMOS OTA with High-Speed Optimizations"[J].IEEE Trans on Circuits and Systems Ⅱ,2002,49(3).pp.294-297
[25]Flandre D,etal." Improved Synthesis of Gain-Boosted Regulated-Cascode CMOS Stages Using Symbolic Analysis and grn/ID Methodology"[J].IEEE J Solid State Circuits,1997,32(7).pp.1006-1012
[26]Conroy C S G,Cline D W,Gray P R."An 8-b 85-MS/s parallel pipeline A/D converter in 1-μm CMOS"[J].IEEE J Solid-State Circuits,1993,28(4).pp447-454
[27]Gulati K,Hae-Seung Lee."A high-swing CMOS telescopic operational amplifier"[J].IEEE J Solid-State Circuits,1998,33(12).pp2010-2019
[28]Christopher Saint,Judy Saint.集成电路版图设计(影印版).第一版.北京.清华大学出版社.2004.pp.1-247
[2]L.Sumanen,M.Waltari,K.Halonen."A 10-bit 200MS/s CMOS Parallel Pipeline A/D Converter".IEEE J.Solid-State Circuits,Jul.2001,36(7).pp.1048-1055
[3]Le H.P.,Zayegh A.Singh J."A 12-bit high performance low cost pipeline ADC".Proc.IEEE International Conference on Electronics Circuits and Systems,14-17 Dec.2003,Vol.2.pp.471-474
[4]徐世六.“高速A/D转换器技术及其产品发展研究”.微电子学.2004,12,34(6).pp.595-606
[5]陈曦,何乐年,张鲁等.“基于0.6um工艺的流水线模数转换器设计”.浙江人学学报(工学版).2006,40(6).pp.1080-1084
[6]S.M.Yoo,J.B.Park,S.H.Lee."A 2.5-V 10-bit 120M Sample/s CMOS Pipelined ADC based on Merger-capacitor switching".Circuits and SystemsⅡ:Express Briefs,IEEE Trans.,2004,51(5).pp.269-275
[7]程闪峰,张洁,阂吴.“低功耗33MHz采样频率,10比特流水线结构的模数转换器”.复旦大学学报(自然科学版).2001,40(3).pp.335-341
[8]Boris Murmann,Bernhard E.Boser."DIGITALLY ASSISTED PIPELINE ADCs".New York,Boston,Dordrecht,London,Moscow.Kluwer Academic Publishers.2004.pp.5-33
[9]Mikko Waltari."CIRCUIT TECHNIQUES FOR LOW-VOLTAGE AND HIGH-SPEED A/D CONVERTERS".[Dissertation].Helsinki University of Technology Department of Electrical and Communications Engineering.Electronic Circuit Design Laboratory.2002.pp.21-96
[10]R.J.Baker.沈树群,李国华,汤静.CMOS:混合信号电路设计.第一版.北京.科学出版社.2005年.pp.17-66
[11]Andrew M.Abo,Paul R.Gray,"A 1.5V,10-bit,14.3-MS/s CMOS Pipeline Analog-to-Digital Converter",IEEE Journal of Solid-State Circuits,vol.34,no.5,May.1999.20-52
[12]Hui Pan,Masahiro Segami,Michael Choi,Jing Cao,Asad A.Abidi."A 3.3-V 12-b 50Ms/s A/D Converterin 0.6umCMOS with over 80-db SFDR".IEEE J.Solid-State Circuits,vol.35,NO.12.December 2000
[13]S.H.Lewise."10 bit 20M sample/s analog-to-digital converter",IEEE J.Solid-State Circuits,vol.27.pp.351-358
[14]Keiichi Kusumoto,Akira Matsuzawa,Kenji Murata,"A 10-b 20-MHz 30-mW Pipelined Interpolating CMOS ADC".IEEE J.Solid-State Circuits
[15]Lin J.Haroun B."An Embedded 0.8V/480μW 6b/22MHz Flash ADC in 0.13μm Digital CMOS Process using Nonlinear Double-Interpolation Technique".ISSCC Dig.of Tec.Papers,Feb.2002.pp.307-309
[16]E.J.Siragusa,I.Galton."Gain Error Correction Technique for Pipelined Analog-To-Digital Convers".Electron Letters,2002,36(7).pp.617-618
[17]G.David."A10-bit,3V,100MS/s pipelined ADC".IEEE Custom Integrated Circuits Conferenee,Orlando,Florida:IEEE Solid-State Circuits Soeiety,2000.pp.257-260
[18]李福乐.“适宜于系统集成的高速高精度模数转换电路的设计技术研究”.[博士论文],清华大学,2003
[19]Berkeley EECS247,Analysis and Design of VLSI Analog-Digital Interface Circuits,IC776CA.
[20]黄飞鹏,王静光,何济柔等.“一种57.6mW,10位,50MS/s流水线操作CMOSA/D转换器”[J],半导体学报,2005,26(11)pp.2230-2235
[21]毕查德·拉扎维著.陈贵灿,程军等译.模拟CMOS集成电路设计[M].第一版.西安.西安交通大学出版社.2003.pp.334-345,266-267
[22]Yang W,Kelly D."A 3-V 340mW 14-b 75Msample/s CMOS ADC with 85-dB SFDR at Nyquist Input"[J].IEEE J Solid-State Circuits,2001,36(12)pp.1931-1936
[23]Kamath B Y,Meyer R G,Gray P R."Relationship Between Frequency Response and Settling Time of Operational Amplifiers"[J].IEEE J Solid-State Circuits,1974,9(12)pp.347-352
[24]Das M."Improved Design Criteria of Gain-Boosted CMOS OTA with High-Speed Optimizations"[J].IEEE Trans on Circuits and Systems Ⅱ,2002,49(3).pp.294-297
[25]Flandre D,etal." Improved Synthesis of Gain-Boosted Regulated-Cascode CMOS Stages Using Symbolic Analysis and grn/ID Methodology"[J].IEEE J Solid State Circuits,1997,32(7).pp.1006-1012
[26]Conroy C S G,Cline D W,Gray P R."An 8-b 85-MS/s parallel pipeline A/D converter in 1-μm CMOS"[J].IEEE J Solid-State Circuits,1993,28(4).pp447-454
[27]Gulati K,Hae-Seung Lee."A high-swing CMOS telescopic operational amplifier"[J].IEEE J Solid-State Circuits,1998,33(12).pp2010-2019
[28]Christopher Saint,Judy Saint.集成电路版图设计(影印版).第一版.北京.清华大学出版社.2004.pp.1-247