基于低电压高精度12-bit SAR ADC设计
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摘要
随着微电子技术的迅速发展,尤其是数字计算和信号处理技术的广泛应用,用数字电路处理模拟信号的情况日益普遍。所以模拟信号数字化是信息技术的发展趋势,而模数转换器在其中扮演着重要的角色。逐次逼近式A/D转换器,适用于分辨率要求为8～16位的A/D转换器,是采样率低于5Msps的中等至高等分辨率应用的常见结构,具有低功耗、小尺寸的特点。这些特点使其具有很宽的应用范围,例如便携/电池供电仪表、笔输入量化器、工业控制和数据/信号采集器等。
本文设计了工作在1.8V单电源电压下,中速低功耗的12bit逐次逼近式A/D转换器。本文主要研究了A/D转换器中包括采样保持电路、D/A转换器、电容阵列和数字逻辑与时序控制等模块的设计,未研究的比较器模块由同组其它成员完成。
为了提高A/D转换的精度,本设计采用全差分和下极板采样技术克服电荷注入效应和时钟馈通效应的影响。同时将采样电容嵌入到D/A转换电容阵列中,采用并行模数转换器分辨率的扩展结构,既保证了采样电容的采样精度值,又有效节省了芯片面积。在电容阵列的设计中,利用单位电容并联的方法减小金属MIM电容值的失配误差,并通过共质心版图布局,进一步提高转换精度。在数字控制模块的电路实现中,用基于环形计数器和移位寄存器的结构设计了逐次逼近逻辑电路。在整体版图设计时采用数模混合信号(AMS)的设计流程,即在一个芯片的设计时采用多种不同的方法,针对规范性强的数字部分采用定制设计方法中的标准单元法进行设计,对于那些严重影响性能的模拟部分采用全定制法进行设计,以求缩短设计周期,提高性能和芯片面积利用率。
本次SAR ADC设计采用的是IBM 0.18μm DP6M CMOS7RF混合信号设计工艺。设计采用MOSIS公司提供的MPW(Multi-Project Wafer)方案流片,所以同一版图中还包括8-bit CPU设计和100MHz低噪声电荷泵锁相环频率合成器的设计。其中SAR ADC版图面积为172.03μm×317.92μm,MPW整体版图面积为1804μm×1804μm。完成版图后对整体电路进行仿真,设计满足12位SAR ADC的基本要求,逐次逼近ADC可以正常的工作。
With high-speed development of microelectronic technology, especially the increasing use of digital computing and signal processing technology in applications, it is becoming common to deal with analog signal with digital circuits. So digitalizing analog signal is the trend of information technology, in which Analog to Digital converter plays an important role. Successive approximation (SAR) A/D converters are frequently the architecture of choice for medium-to-high-resolution applications with sample rates under 5 Mega samples per second (Msps). Because of providing low power consumption as well as a small form factor, SAR A/D converters have a wide variety of applications, such as portable/battery-powered instrument, pen digitizers, industrial controls and data/signal acquisition.
In this paper, a 12-bit low power SAR A/D converter with medium speed is designed, which can work under a 1.8V power supply. This paper mainly focuses on several parts: S/H circuit, D/A converters, capacitance array and digital logic control in time sequence. Other group member completed the design of comparator.
This design uses the difference technique and bottom sampling technique to overcome the charge injection effect and the clock feed-through effect. Improve the A/D converter accuracy at the same time, sampling capacitor embeds into the D/A converter capacitor array, takes the expansion of parallel structure to ensure the accuracy of conversion effectively and save the chip area. In the design of the capacitor array, it uses the unit's method to reduce the mismatch error of the parallel MIM capacitance value, and adopts a whole concentric layout to increase conversion accuracy. In the digital control module of the circuit, design the successive approximation logic which based on the ring counter/shift register. In the overall layout design uses Mixed-signal (AMS) design flow, that is, in the design of digital part, uses the Full-Custom Design methodology based on the standard cell. In the analog part, uses the Full-Custom Design methodology, so as to shorten the design cycle and improve the performance and silicon available area.
In the design, the SAR A/D converter is based on IBM 0.18um DP6M CMOS7RF mixed-signal design process, which uses the MPW (Multi-Project Wafer) to tape out by MOSIS. So in the same layout, there are also 8 - bit CPU design and low noise charge pump 100 MHz PLL Synthesizer Design. The layout area of the SAR ADC is , the MPW area is . After the completion of the layout on the whole circuit simulation, the simulation results show that the design meets 12 A/D converter requirements, the SAR A/D converter can work well.
本文设计了工作在1.8V单电源电压下,中速低功耗的12bit逐次逼近式A/D转换器。本文主要研究了A/D转换器中包括采样保持电路、D/A转换器、电容阵列和数字逻辑与时序控制等模块的设计,未研究的比较器模块由同组其它成员完成。
为了提高A/D转换的精度,本设计采用全差分和下极板采样技术克服电荷注入效应和时钟馈通效应的影响。同时将采样电容嵌入到D/A转换电容阵列中,采用并行模数转换器分辨率的扩展结构,既保证了采样电容的采样精度值,又有效节省了芯片面积。在电容阵列的设计中,利用单位电容并联的方法减小金属MIM电容值的失配误差,并通过共质心版图布局,进一步提高转换精度。在数字控制模块的电路实现中,用基于环形计数器和移位寄存器的结构设计了逐次逼近逻辑电路。在整体版图设计时采用数模混合信号(AMS)的设计流程,即在一个芯片的设计时采用多种不同的方法,针对规范性强的数字部分采用定制设计方法中的标准单元法进行设计,对于那些严重影响性能的模拟部分采用全定制法进行设计,以求缩短设计周期,提高性能和芯片面积利用率。
本次SAR ADC设计采用的是IBM 0.18μm DP6M CMOS7RF混合信号设计工艺。设计采用MOSIS公司提供的MPW(Multi-Project Wafer)方案流片,所以同一版图中还包括8-bit CPU设计和100MHz低噪声电荷泵锁相环频率合成器的设计。其中SAR ADC版图面积为172.03μm×317.92μm,MPW整体版图面积为1804μm×1804μm。完成版图后对整体电路进行仿真,设计满足12位SAR ADC的基本要求,逐次逼近ADC可以正常的工作。
With high-speed development of microelectronic technology, especially the increasing use of digital computing and signal processing technology in applications, it is becoming common to deal with analog signal with digital circuits. So digitalizing analog signal is the trend of information technology, in which Analog to Digital converter plays an important role. Successive approximation (SAR) A/D converters are frequently the architecture of choice for medium-to-high-resolution applications with sample rates under 5 Mega samples per second (Msps). Because of providing low power consumption as well as a small form factor, SAR A/D converters have a wide variety of applications, such as portable/battery-powered instrument, pen digitizers, industrial controls and data/signal acquisition.
In this paper, a 12-bit low power SAR A/D converter with medium speed is designed, which can work under a 1.8V power supply. This paper mainly focuses on several parts: S/H circuit, D/A converters, capacitance array and digital logic control in time sequence. Other group member completed the design of comparator.
This design uses the difference technique and bottom sampling technique to overcome the charge injection effect and the clock feed-through effect. Improve the A/D converter accuracy at the same time, sampling capacitor embeds into the D/A converter capacitor array, takes the expansion of parallel structure to ensure the accuracy of conversion effectively and save the chip area. In the design of the capacitor array, it uses the unit's method to reduce the mismatch error of the parallel MIM capacitance value, and adopts a whole concentric layout to increase conversion accuracy. In the digital control module of the circuit, design the successive approximation logic which based on the ring counter/shift register. In the overall layout design uses Mixed-signal (AMS) design flow, that is, in the design of digital part, uses the Full-Custom Design methodology based on the standard cell. In the analog part, uses the Full-Custom Design methodology, so as to shorten the design cycle and improve the performance and silicon available area.
In the design, the SAR A/D converter is based on IBM 0.18um DP6M CMOS7RF mixed-signal design process, which uses the MPW (Multi-Project Wafer) to tape out by MOSIS. So in the same layout, there are also 8 - bit CPU design and low noise charge pump 100 MHz PLL Synthesizer Design. The layout area of the SAR ADC is , the MPW area is . After the completion of the layout on the whole circuit simulation, the simulation results show that the design meets 12 A/D converter requirements, the SAR A/D converter can work well.
引文
[1]姚建清,国内CMOSADC研发动态。电子产品世界。2007(7):62-63
[2]Robert H.Walden,Member,IEEE,"Analog-to Digital Converter Survey and Analysis".IEEE Journal on Selected Areas in Communications,Vol.17,No.4,April 1999.pp 539.
[3]McCarroll B J,Sodini C G,Lee Hae-Seung.A high speed CMOS comparator for use in anADC.IEEE J.Solid-State Circuits,1988,23(1):159-165
[4]刘付斌,邵高平,李建新.通用数据采集平台ADC电路的可靠性设计.微计算机信息.2005.21(4).92-93
[5]Parthasarathy K L,Geiger R.Unambiguous characterization and specification of D/A converter performance.Circuits and Systems,2000.Proceedings of the 43rd IEEE Midwest Symposium,2000,2:890-894
[6]模数转换器应用技术.高光天主编.薛天宇,孟庆昌,华正权编著.ADI产品应用技术从书
[7]KUSH DARIKH.A/D、D/A转换器使用性能与分辨率.今日电子,1998,10:38-41
[8]高性能处理器的新动向.电子产品世界.IC与元器件.2005.5,pp108.
[9]蔡跃明,沈永朝.选用A/D转换器的关键因素.军书通信技术,1996,01:31-37
[10]R.Van de Plassche,CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters.Kluwer Academic Publishers,second ed.,2003.
[11]B.Razavi,Principles of Data Conversion System Design.John Wiley and Sons.Inc,first ed.1995.
[12]J.L.McCreary,Successive Approximation Analog-to-Digital Conversion Techniques in MOS Integrated Circuits.PhD thesis,University of California,Berkeley,1975.
[13]Texas Instruments,Data Converter Selection Guide,2004.
[14]P.E.Allen and D.R.Holdberg,CMOS Analog Circuit Design.Oxford University Press,second ed.,2002.
[15]王若虚.超高速A/D转换结构.微电子学,1997,27(5):285-292
[16]M.E.Waltari and K.A.Halonen,Circuit Techniques for Low-Voltage and High-Speed A/D Converters.Kluwer Academic Publishers,first ed.,2002.
[17]魏智.解析逐次逼近ADC.国外电子元器件.2003年第2期
[18]许巨衍,徐世六.关于A/D与D/A转换器发展方向的一些思考.微电子学.1998,28(4):217-223
[19]J.L.McCreary and P.R.Gray,"AII-MOS charge redistribution analog-to-digital conversion techniques-part," IEEE Journal of Solid-State Circuits,vol.SC-10,no.6,pp.371-379,1975.
[20]隋海建.硕士毕业论文:全差分逐次逼近模拟数字转换器的设计.微电子学与固体电子学.20040401
[21]Gilbert Promitzer,"12-bit Low-Power Fully Diferential Switched Capacitor Noncalibrating Successiv Approximation ADC with I MS/s",IEEE JSSC,VOL.36,N0.7,JULY 2001
[22]陈林,张细先.对采样保持电路的分析.机械制造与自动化,2003,5:89-90
[23]朱樟明,杨银堂,柴常春.新型CMOS采样/保持电路的设计研究.微电子学,2004,34(3):298-301
[24]王照钢,陈诚,任俊彦等.一种低电压高精度125MHz采样/保持电路.微电子学,2004,34(3):306-309
[25]薛亮,沈延钊,张向民.一种CMOS高速采样/保持放大器.微电子学,2004,34(3):310-313
[25]Gatti U,Maloberti F.An accurate CMOS sample-and-hold circuit.IEEE J.Solid-State Circuits,1992,27(1):643-651
[26]S.Mortezapour and E.K.F.Lee,"A l-v,8-bit successive approximation ADC in standard CMOS process," IEEE Journal of Solid-State Circuits,vol.35,no.4,pp.642-646,2000.
[27]C.J.B.Fayomi,G.W.Roberts,and M.Sawan,"A l-v,10-bit rail-to-rail successive approximation analog-to-digital converter in standard 0.18um CMOS technology," IEEE International Symposium on Circuits and Systems,vol.1,pp.460-463,2001.
[28]B.Nauta and A.G.W.Venes,"A 70-MS/s 110-mW 8-b CMOS folding and interpolating A/D converter," IEEE Journal of Solid-State Circuits,vol.30,no.12,pp.1302-1308,1995.
[29]J.Sauerbrey,D.Schmitt-Landsiedel,and R.Thewes,"A 0.5-v 1-uW successive approximation ADC," IEEE Journal of Solid-State Circuits,vol.38,no.7,pp.1261-1265,2003.
[30]Semiconductor Industry Association,International Technology Roadmap for Semiconductors,2004.
[31]Y.Matsuya and J.Yamada,"1-v power supply,384 kS/s,10b A/D and D/A converters with swing-suppression noise shaping," Proc.ISSC Dig.Tech.Papers,pp.192-193,1994.
[32]C.J.B.Fayomi,M.Sawan,and G.W.Roberts,"A design strategy for a 1-v railto-raii Input/Output CMOS opamp," IEEE International Symposium on Circuits and Systems,vol.1,pp.639-642,2001.
[33]J.Park,H.-J.Park,J.-W.Kim,S.Seo,and P.Chung,"A.1 mW 10-bit 500 KSPS SAR A/D converter," IEEE International Symposium on Circuits and Systems,pp.581-584,2000.
[34]H.Neubauer,T.Desel,and H.Hauer,"A successive approximation A/D converter with 16bit 200kS/s in 0.6um CMOS using selfcalibration and low power techniques," The 8th International Conference on Electronics,Circuits and Systems,vol.2,pp.859-862,2001.
[35]S.A.Hammouda,M.S.Tawfik,and H.F.Ragaie,"Low voltage fully differential opamp with high gain wide bandwidth suitable for switched capacitor applications," Midwest Symposium on Circuits and Systems,vol.1,pp.Ⅰ-324-Ⅰ-327,2002
[36]Hjaltnrson,Robert Hagglund.Layout Generation of Matched Capacitors[C]National Conf.Radio Science(RVK).Stockholm.Sweden.2002.
[37]Hastings A.The Art of Analog Layout[M].Prentice Hall.2001.
[38]MeNutt M J,LeMarquis S,Donkey J L.Systematic Capacitance Matching Errors and Corrective Layout Procedures[J].IEEE J.Solid-State Circuits.1994,29(5).
[39]T.O.Anderson,"Optimum control logic for successive approximation analog-to-digital converters," Computer Design,vol.11,No.7 pp.81-86,1972.
[40]吕江平一种数模混合IC的版图设计.集成电路通讯.第22卷第2期.2004,6
[41]杨之廉、申明.超大规模集成电路设计方法学导论.北京:清华大学出版社,1999.
[42]Alan Hastings,"The Art of Analog Layout",2004 by Peason Education Asia Limited and Tsinghua University press.pp223-224
[43]王翠霞,范学峰,许维胜 等.Cadence版图设计环境的建立及设计规则的验证.《现代电子技术》2004年第15期总第182期。
[2]Robert H.Walden,Member,IEEE,"Analog-to Digital Converter Survey and Analysis".IEEE Journal on Selected Areas in Communications,Vol.17,No.4,April 1999.pp 539.
[3]McCarroll B J,Sodini C G,Lee Hae-Seung.A high speed CMOS comparator for use in anADC.IEEE J.Solid-State Circuits,1988,23(1):159-165
[4]刘付斌,邵高平,李建新.通用数据采集平台ADC电路的可靠性设计.微计算机信息.2005.21(4).92-93
[5]Parthasarathy K L,Geiger R.Unambiguous characterization and specification of D/A converter performance.Circuits and Systems,2000.Proceedings of the 43rd IEEE Midwest Symposium,2000,2:890-894
[6]模数转换器应用技术.高光天主编.薛天宇,孟庆昌,华正权编著.ADI产品应用技术从书
[7]KUSH DARIKH.A/D、D/A转换器使用性能与分辨率.今日电子,1998,10:38-41
[8]高性能处理器的新动向.电子产品世界.IC与元器件.2005.5,pp108.
[9]蔡跃明,沈永朝.选用A/D转换器的关键因素.军书通信技术,1996,01:31-37
[10]R.Van de Plassche,CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters.Kluwer Academic Publishers,second ed.,2003.
[11]B.Razavi,Principles of Data Conversion System Design.John Wiley and Sons.Inc,first ed.1995.
[12]J.L.McCreary,Successive Approximation Analog-to-Digital Conversion Techniques in MOS Integrated Circuits.PhD thesis,University of California,Berkeley,1975.
[13]Texas Instruments,Data Converter Selection Guide,2004.
[14]P.E.Allen and D.R.Holdberg,CMOS Analog Circuit Design.Oxford University Press,second ed.,2002.
[15]王若虚.超高速A/D转换结构.微电子学,1997,27(5):285-292
[16]M.E.Waltari and K.A.Halonen,Circuit Techniques for Low-Voltage and High-Speed A/D Converters.Kluwer Academic Publishers,first ed.,2002.
[17]魏智.解析逐次逼近ADC.国外电子元器件.2003年第2期
[18]许巨衍,徐世六.关于A/D与D/A转换器发展方向的一些思考.微电子学.1998,28(4):217-223
[19]J.L.McCreary and P.R.Gray,"AII-MOS charge redistribution analog-to-digital conversion techniques-part," IEEE Journal of Solid-State Circuits,vol.SC-10,no.6,pp.371-379,1975.
[20]隋海建.硕士毕业论文:全差分逐次逼近模拟数字转换器的设计.微电子学与固体电子学.20040401
[21]Gilbert Promitzer,"12-bit Low-Power Fully Diferential Switched Capacitor Noncalibrating Successiv Approximation ADC with I MS/s",IEEE JSSC,VOL.36,N0.7,JULY 2001
[22]陈林,张细先.对采样保持电路的分析.机械制造与自动化,2003,5:89-90
[23]朱樟明,杨银堂,柴常春.新型CMOS采样/保持电路的设计研究.微电子学,2004,34(3):298-301
[24]王照钢,陈诚,任俊彦等.一种低电压高精度125MHz采样/保持电路.微电子学,2004,34(3):306-309
[25]薛亮,沈延钊,张向民.一种CMOS高速采样/保持放大器.微电子学,2004,34(3):310-313
[25]Gatti U,Maloberti F.An accurate CMOS sample-and-hold circuit.IEEE J.Solid-State Circuits,1992,27(1):643-651
[26]S.Mortezapour and E.K.F.Lee,"A l-v,8-bit successive approximation ADC in standard CMOS process," IEEE Journal of Solid-State Circuits,vol.35,no.4,pp.642-646,2000.
[27]C.J.B.Fayomi,G.W.Roberts,and M.Sawan,"A l-v,10-bit rail-to-rail successive approximation analog-to-digital converter in standard 0.18um CMOS technology," IEEE International Symposium on Circuits and Systems,vol.1,pp.460-463,2001.
[28]B.Nauta and A.G.W.Venes,"A 70-MS/s 110-mW 8-b CMOS folding and interpolating A/D converter," IEEE Journal of Solid-State Circuits,vol.30,no.12,pp.1302-1308,1995.
[29]J.Sauerbrey,D.Schmitt-Landsiedel,and R.Thewes,"A 0.5-v 1-uW successive approximation ADC," IEEE Journal of Solid-State Circuits,vol.38,no.7,pp.1261-1265,2003.
[30]Semiconductor Industry Association,International Technology Roadmap for Semiconductors,2004.
[31]Y.Matsuya and J.Yamada,"1-v power supply,384 kS/s,10b A/D and D/A converters with swing-suppression noise shaping," Proc.ISSC Dig.Tech.Papers,pp.192-193,1994.
[32]C.J.B.Fayomi,M.Sawan,and G.W.Roberts,"A design strategy for a 1-v railto-raii Input/Output CMOS opamp," IEEE International Symposium on Circuits and Systems,vol.1,pp.639-642,2001.
[33]J.Park,H.-J.Park,J.-W.Kim,S.Seo,and P.Chung,"A.1 mW 10-bit 500 KSPS SAR A/D converter," IEEE International Symposium on Circuits and Systems,pp.581-584,2000.
[34]H.Neubauer,T.Desel,and H.Hauer,"A successive approximation A/D converter with 16bit 200kS/s in 0.6um CMOS using selfcalibration and low power techniques," The 8th International Conference on Electronics,Circuits and Systems,vol.2,pp.859-862,2001.
[35]S.A.Hammouda,M.S.Tawfik,and H.F.Ragaie,"Low voltage fully differential opamp with high gain wide bandwidth suitable for switched capacitor applications," Midwest Symposium on Circuits and Systems,vol.1,pp.Ⅰ-324-Ⅰ-327,2002
[36]Hjaltnrson,Robert Hagglund.Layout Generation of Matched Capacitors[C]National Conf.Radio Science(RVK).Stockholm.Sweden.2002.
[37]Hastings A.The Art of Analog Layout[M].Prentice Hall.2001.
[38]MeNutt M J,LeMarquis S,Donkey J L.Systematic Capacitance Matching Errors and Corrective Layout Procedures[J].IEEE J.Solid-State Circuits.1994,29(5).
[39]T.O.Anderson,"Optimum control logic for successive approximation analog-to-digital converters," Computer Design,vol.11,No.7 pp.81-86,1972.
[40]吕江平一种数模混合IC的版图设计.集成电路通讯.第22卷第2期.2004,6
[41]杨之廉、申明.超大规模集成电路设计方法学导论.北京:清华大学出版社,1999.
[42]Alan Hastings,"The Art of Analog Layout",2004 by Peason Education Asia Limited and Tsinghua University press.pp223-224
[43]王翠霞,范学峰,许维胜 等.Cadence版图设计环境的建立及设计规则的验证.《现代电子技术》2004年第15期总第182期。