工艺波动相关的集成电路互连线寄生参数提取方法研究
|
摘要
集成电路特征尺寸缩小到100纳米以下之后,多层互连线寄生电容、寄生电阻引入的延时开始超过MOSFET栅电容延迟,成为影响电路总体延时更主要的因素,进而成为制约深纳米技术高速芯片性能提高的瓶颈之一。进行互连线版图寄生参数提取(Layout Parasitic Extraction, LPE),精确获得其等效寄生参数(电阻、电容等),并应用于布线后电路仿真(Postlayout Simulation)愈来愈重要。
制备深纳米VLSI芯片的互连线层次逐渐发展到目前的8层、9层甚至10层以上。日趋复杂的工艺使得不同晶圆间、或同一晶圆不同位置处的互连线工艺差异愈加明显,互连线等效寄生参数受此影响将在一定范围内产生明显波动。建立互连线寄生参数统计学模型,精确表征工艺波动对互连线寄生参数乃至延迟的影响,并最终实现电路精确的布线后仿真成为现今半导体技术的重要研究课题。
本论文研究40nm CMOS工艺多层互连寄生参数提取,意图获得工艺波动相关的互连寄生参数表征与提取方法,优化相应的统计学互连工艺剖面实现技术。为评估各层金属互连线间及层间寄生效应与工艺差异的关联性,本文自主设计了五种模型测试结构,其中包括：1、大面积梳状金属耦合线间寄生电容测量结构,用于评估光刻、刻蚀工艺对金属层厚度及宽度的影响；2、交叉的相邻层次金属大面积梳状层间寄生电容测量结构,用于提取金属层间电介质层的厚度及介电常数；3、四端开尔文金属电阻结构,用于测量并准确提取寄生电阻；4、奇数反相器组成环形振荡器、且反相器之间通过较小尺寸线间耦合金属电容相连,用以校验金属线间寄生电容相关的提取规则准确性；5、反相器环形振荡器,且反相器间通过较小尺寸不同层间金属电容相连,用于校验金属层间寄生电容的提取规则准确。本论文研究中,采用40nm CMOS工艺的大马士革铜互连工艺制备了M1-M7共7种不同金属层互连线线间耦合寄生电容,M1&M2～M6&M7共6种层间寄生电容以及7种用于验证寄生参数提取规则的环形振荡器电路。
研究中,对上述制备结构逐一进行了在片测量和统计分析,结果表明工艺波动对互连寄生电容的影响特征为：互连线线间耦合电容与层间耦合电容均受工艺差异较大影响,数值波动范围较大；采用相同工艺流程的线间耦合电容存在较大相关性,M2-M7各层线间耦合电容测量值之间相关性均超过77%；不同工艺流程的金属层,其线间耦合寄生电容相关性较小,采用单大马士革工艺的M1层线间耦合电容测量值与其它层线间电容之间的相关性几乎都小于50%；而各层间电容的相关性则更低,几乎均低于20%。上述结论不仅为提取工艺波动相关的互连线寄生参数时提供了依据,同时也表明调整互连工艺参数时还需考虑可能引起的相关性变化。
目前互连线电阻电容寄生参数提取普遍采用互连工艺剖面(Interconnection Technology Profile, ITP)分析技术,该方法只能提取互连线上各节点的理想化寄生电阻、寄生电数值,无法评估和模拟工艺波动影响引入的参数差异,且缺乏电学测量数据支持。本文对上述典型互连工艺剖面和角互连工艺剖面提取方法进行了优化,创新性地提出一种可表征各层金属互连线间寄生电容间相关性的多层互连寄生参数提取方法,首次在互连寄生电容参数提取过程中加入电容相关性分析,自主完成了将优化的新流程嵌入完整集成电路设计流程的工作,通过对不同类型环形振荡器进行蒙特卡洛仿真,校验了该寄生参数提取方法的准确性。
本论文使用Synopsys公司的电磁场效应仿真软件Raphael针对上文所述的两种寄生电容测量结构,在场效应仿真器中构建了3D仿真结构,并采用随机漫步数值模拟算法对其进行了仿真,校准ITP文件中工艺参数数值,最终实现不同层次的寄生电容结构仿真值与测量值之间差别均小于10%。根据ITP文件生成抽取规则,各寄生电容结构提取得到的电容提取值与测量统计中值偏差小于10%。根据寄生电容统计数据提取考虑寄生电容之间相关性的工艺波动相关ITP文件,分析各金属层次线间寄生电容之间的相关性,采用主成分分析法对数据相关性进行分析,计算得到M2-M7线间寄生电容结构主成分的载荷系数以及考虑相关性影响的线间电容分布标准修正差数值。据此对电容结构对应的互连层次工艺参数建立统计模型。通过ITP文件生成抽取规则,对环形振荡器校验电路进行抽取得到包含寄生参数统计模型的布线后仿真电路。最终,参数提取之后的电路蒙特卡洛仿真结果统计分布与实际电路测量的统计分布非常吻合。其中负载M1线间耦合电容的33级环振输出信号周期测量中值与蒙特卡洛仿真中值之间差别仅为2.54%,测量标准差与仿真标准差之间差别仅为3.65%；负载M1和M2之间金属层间耦合电容的33级环振相应数据分别为-1.7%和8.22%；负载M2线间耦合电容的11级环振相应数据分别为9.16%和9.89%。所有环形振荡器校验电路进行蒙特卡洛仿真得到的仿真统计中值与测量数据中值偏差小于10%,仿真高斯分布3σ与测量数据3σ偏差小于10%,均符合半导体产业要求。
本文基于国有40nnm工艺平台,自主建立并完善了40nm CMOS工艺波动相关的多层互连线RC寄生参数提取方法,取得的突出成果如下：
1、自主创建了40nm工艺互连寄生参数提取的测试结构和电路,可用于提取互连寄生参数和参数提取准确性的校验。
2、自主提出并实现了对典型ITP文件及角ITP文件制作方法的优化方法和两者的完整提取流程,创造性地将3D互连寄生参数仿真与寄生电容结构测量校验嵌入互连寄生参数提取流程,提高了ITP文件中各工艺参数的准确性。
3、采用主成分分析法对互连线线间耦合寄生电容的相关性进行分析,且实现了包含线间耦合寄生电容相关性的互连RC寄生参数提取方法。
本文进行的工艺相关寄生提取方法经过了电路性能测量验证,环形振荡器电路布线后蒙特卡洛仿真值与测量数据统计结果之间的拟合误差达到了产业技术要求。因此,本文提出并实现的工艺波动相关的互连寄生参数提取方法不仅可应用于高端芯片的精准统计仿真,减小“过设计”,同时对互连工艺参数的调整和设定具有重要的指导意义。
As the IC process technology scales into sub-100nm, delay induced by back-end interconnects become larger. It overtakes the delay induce by MOSFET gates and become the main part of circuits delay in Integrated Circuits (IC) and the main course that limits IC's performance. It is critical to use Layout Parasitic Extraction (LPE) tools to accurately extract interconnects'parasitic resistances and capacitances in aimed IC. Running post-layout simulation with these extracted parasitic RC instances is more and more important.
16-inch Wafers are overtaking12-inch wafers to fabricated deep sub-nanometer VLSI. Even larger wafer will be developed. Interconnects layers'number in IC has grown to8-9, even ten. The advanced semi-conductor process is so complicated that the process conditions differ greatly in different wafers or in different dies at the same wafer. These differences may affect the effective unit parasitic parameters of backend interconnect and lead to parasitic parameters'variation. It becomes a very important research topic that how to accurately extract the statistical parasitic instances of backend interconnects, make them be able to describe the influence of semi-conductor backend process variation on interconnects and finally use them in post-layout simulation for ICs.
This paper focused on interconnect parasitic parameters extraction on40nm CMOS process technology and try to present a complete method to extract a process variation-aware Interconnect technology Profile. In order to investigate the inter-line parasitic capacitances between metal interconnects in the same layer and intra-layers parasitic capacitances between interconnects in the two neighbor layers, find out the connection between their values and process variation, this paper design five test keys for modeling interconnects:(1).Metal Comb test structures on one single metal layer for parasitic metal inter-line Capacitors measurements and extraction of thickness of metal layers and width loss induced by etch process.(2). Structure composed of comb layout on two neighbor layers cross over each other for the parasitic intra-layer MOM Capacitors measurement and extraction of thickness of every single dielectric layer between two neighbor metal layers as well as its permittivity.(3) Inverter Ring Oscillators (RO) for unit gate delay measurement without any metal RC load;(4).Inverter RO with small parasitic inter-line coupling capacitors loaded between every two inverters. Their results of post-layout simulation after parasitic extractions are able to verify accuracy of extraction rule related to inter-line parasitic capacitances.(5).Inverter RO with small parasitic intra-layer MOM metal capacitors loaded between every two inverters. Their results of post-layout simulation are able to verify accuracy of extraction rule related to intra-layer parasitic capacitances. In this paper,7different kinds of large inter-line coupling capacitors in M1-M7,5kinds of different intra-layer MOM metal capacitors in M1&M2-M6-M7and7kinds of inverter RO circuits are designed and manufactured with40nm dual damascene Copper interconnects process technology.
All the above-mentioned test structures are on-wafer scanning measured and statistically analyzed. The measurements data indicate the influence of process variation on parasitic capacitance of interconnects. First, there are large scale fluctuations in parasitic inter-line capacitances and intra-layer capacitances. Secondly, the inter-line coupling capacitances in metal layers made by the same process flow are largely correlated. The interconnects of M2-M7are all fabricated by dual Damascene process, correlation of their inter-line capacitor measured values are all above77%; while inter-line capacitances in metal layers made by different process, for example, Ml fabricated by single Damascene process, have small correlations with inter-line capacitances of M2-M7. Correlations of Ml inter-line capacitor measured values between capacitors' in other layers are all below50%; Intra-layer capacitances have even smaller correlations because Correlations of all the intra-layer capacitor measured values are all below20%. These conclusions not only offer basis for variation-aware Interconnection Technology Profile (ITP) extraction but also indicate that correlations of interconnects process should be considered while tuning the process parameters in ITP file.
The most popular used backend interconnect parasitic RC parameters extraction method is ITP analyzing method. It is the method that defining totally80process parameters such as every single metal layer's thickness T, every single dielectric layer's thickness H、permittivity ε、Delta width induce by etch process ΔW、 Minimum interconnects width Wmin in an ITP file. Based on this ITP file, deduce and produce a RC extraction rule file; according to this rule file, finally extract the parasitic resistance and capacitance between each nodes in circuits netlist of a certain integrated circuits by LPE toolkit. In this traditional method only idealized parasitic resistance and capacitance value can be extracted from each node in circuits, it is impossible to simulate and evaluate the variation of parasitic resistance and capacitance generated by the process fluctuations. According to this, this paper optimize the extraction method of typical ITP and corner ITP, creatively present a parasitic capacitance correlation included process variation aware back-end interconnects parasitic parameters extraction method. For the first time, induce capacitance correlation analysis in interconnects parasitic capacitance extraction and embed the optimized extraction flow into the IC design flow. Monte Carlo simulations are cast on different types of Ring Oscillators circuits; the simulation results verify the accuracy of parasitic extraction method.
3D structures of the first kind and second kind of above-mentioned capacitors in are built in Synopsys's field-effect simulation software Raphael by inputting capacitors'layouts and initial ITP file measured by Transmission electron microscope. Simulations are performed on these structures in random walk method. Based on median value of these parasitic capacitors'measurements data, the typical process parameters value of each metal layer and dielectric layer are extracted and combined into the typical ITP file for this process technology. ITP file can be calibrated and optimized according to the comparison of simulated capacitance values and median measured values of parasitic capacitors. After the calibration, all the difference between simulated and measured capacitance are less than10%. Typical capacitance values are extracted according to extraction rules generated by the typical ITP file. The deviations of extracted values from median value of measurements are all less than10%. Based on typical ITP file, variation-aware ITP file is built according to the parasitic capacitor structures' statistical measurements. Upon distribution of these capacitors' value, the correlations between the values of inter-line capacitor in every single metal layer are analyzed by Principle Component Analysis (PCA). Three principle components of M2-M7inter-line coupling parasitic capacitors which have more than98%accumulative contribute rate are calculated based on their measurements'distribution by PCA. The load factors of these three main principle components are calculated, according to which the standard deviation values of inter-line capacitors'values excluded correlation factors are obtained. The standard deviation values can be used to build statistical model of ITP related process parameters. Using rule derived from the optimized40nm variation-aware statistical ITP, post-layout netlists including variation-aware parasitic can be extracted on RO loaded with inter-line capacitors and intra-layer capacitors. Finally, Monte Carlo simulations are performed upon the netlists and the statistical distribution of simulation data is very consistent with the statistical distribution of actual circuits' measurements. The output signal periods of33stages RO loaded with M1inter-line capacitors mean measured values and Monte Carlo simulated values only have2.54%difference between each other's and difference between their standard deviations is only3.65%; the two differences number between simulated and measured values of11stages RO loaded with M2inter-line capacitors are-9.16%and9.89%; the two differences number of33stages RO loaded with M1&M2intra-layer capacitors are-1.7%and8.22%. All the Monte Carlo simulated mean value and standard deviation of RO verification ciruits'signal periods have less than10%differences compared to their measured data. It is qualified according to IC industry standard.
Based on state-owned40nm process platform, this paper independently establishes and optimizes the40nm CMOS process variation-aware interconnects technology profile extraction method; the outstanding results achieved are as follows:
1. Independently, create a set of test structures for the40nm CMOS process interconnects parameters' extraction. Including the parasitic capacitors for ITP extraction and Ring Oscillators for circuits' simulation verification.
2. Independently optimize the traditional typical ITP file extraction method; present a new complete extraction flow; creatively embed the3D backend parasitic simulations and the RC extraction toolkits'calibration by parasitic capacitors measurements into ITP extraction flow. The accuracy of process parameters in typical ITP file is highly improved.
3. Upon distribution of parasitic capacitors' measurements, the correlations between the values of parasitic coupling capacitor in every single metal layer are analyzed by Principle Component Analysis. Extraction method of variation-aware ITP file including the correlation ship of single-layer coupling capacitors related process parameters is presented. The Monte Carlo simulation results of RO circuits' postlayout extracted netlists quite fit the mesurements statistical data, which is up to the standard of industry.
制备深纳米VLSI芯片的互连线层次逐渐发展到目前的8层、9层甚至10层以上。日趋复杂的工艺使得不同晶圆间、或同一晶圆不同位置处的互连线工艺差异愈加明显,互连线等效寄生参数受此影响将在一定范围内产生明显波动。建立互连线寄生参数统计学模型,精确表征工艺波动对互连线寄生参数乃至延迟的影响,并最终实现电路精确的布线后仿真成为现今半导体技术的重要研究课题。
本论文研究40nm CMOS工艺多层互连寄生参数提取,意图获得工艺波动相关的互连寄生参数表征与提取方法,优化相应的统计学互连工艺剖面实现技术。为评估各层金属互连线间及层间寄生效应与工艺差异的关联性,本文自主设计了五种模型测试结构,其中包括：1、大面积梳状金属耦合线间寄生电容测量结构,用于评估光刻、刻蚀工艺对金属层厚度及宽度的影响；2、交叉的相邻层次金属大面积梳状层间寄生电容测量结构,用于提取金属层间电介质层的厚度及介电常数；3、四端开尔文金属电阻结构,用于测量并准确提取寄生电阻；4、奇数反相器组成环形振荡器、且反相器之间通过较小尺寸线间耦合金属电容相连,用以校验金属线间寄生电容相关的提取规则准确性；5、反相器环形振荡器,且反相器间通过较小尺寸不同层间金属电容相连,用于校验金属层间寄生电容的提取规则准确。本论文研究中,采用40nm CMOS工艺的大马士革铜互连工艺制备了M1-M7共7种不同金属层互连线线间耦合寄生电容,M1&M2～M6&M7共6种层间寄生电容以及7种用于验证寄生参数提取规则的环形振荡器电路。
研究中,对上述制备结构逐一进行了在片测量和统计分析,结果表明工艺波动对互连寄生电容的影响特征为：互连线线间耦合电容与层间耦合电容均受工艺差异较大影响,数值波动范围较大；采用相同工艺流程的线间耦合电容存在较大相关性,M2-M7各层线间耦合电容测量值之间相关性均超过77%；不同工艺流程的金属层,其线间耦合寄生电容相关性较小,采用单大马士革工艺的M1层线间耦合电容测量值与其它层线间电容之间的相关性几乎都小于50%；而各层间电容的相关性则更低,几乎均低于20%。上述结论不仅为提取工艺波动相关的互连线寄生参数时提供了依据,同时也表明调整互连工艺参数时还需考虑可能引起的相关性变化。
目前互连线电阻电容寄生参数提取普遍采用互连工艺剖面(Interconnection Technology Profile, ITP)分析技术,该方法只能提取互连线上各节点的理想化寄生电阻、寄生电数值,无法评估和模拟工艺波动影响引入的参数差异,且缺乏电学测量数据支持。本文对上述典型互连工艺剖面和角互连工艺剖面提取方法进行了优化,创新性地提出一种可表征各层金属互连线间寄生电容间相关性的多层互连寄生参数提取方法,首次在互连寄生电容参数提取过程中加入电容相关性分析,自主完成了将优化的新流程嵌入完整集成电路设计流程的工作,通过对不同类型环形振荡器进行蒙特卡洛仿真,校验了该寄生参数提取方法的准确性。
本论文使用Synopsys公司的电磁场效应仿真软件Raphael针对上文所述的两种寄生电容测量结构,在场效应仿真器中构建了3D仿真结构,并采用随机漫步数值模拟算法对其进行了仿真,校准ITP文件中工艺参数数值,最终实现不同层次的寄生电容结构仿真值与测量值之间差别均小于10%。根据ITP文件生成抽取规则,各寄生电容结构提取得到的电容提取值与测量统计中值偏差小于10%。根据寄生电容统计数据提取考虑寄生电容之间相关性的工艺波动相关ITP文件,分析各金属层次线间寄生电容之间的相关性,采用主成分分析法对数据相关性进行分析,计算得到M2-M7线间寄生电容结构主成分的载荷系数以及考虑相关性影响的线间电容分布标准修正差数值。据此对电容结构对应的互连层次工艺参数建立统计模型。通过ITP文件生成抽取规则,对环形振荡器校验电路进行抽取得到包含寄生参数统计模型的布线后仿真电路。最终,参数提取之后的电路蒙特卡洛仿真结果统计分布与实际电路测量的统计分布非常吻合。其中负载M1线间耦合电容的33级环振输出信号周期测量中值与蒙特卡洛仿真中值之间差别仅为2.54%,测量标准差与仿真标准差之间差别仅为3.65%；负载M1和M2之间金属层间耦合电容的33级环振相应数据分别为-1.7%和8.22%；负载M2线间耦合电容的11级环振相应数据分别为9.16%和9.89%。所有环形振荡器校验电路进行蒙特卡洛仿真得到的仿真统计中值与测量数据中值偏差小于10%,仿真高斯分布3σ与测量数据3σ偏差小于10%,均符合半导体产业要求。
本文基于国有40nnm工艺平台,自主建立并完善了40nm CMOS工艺波动相关的多层互连线RC寄生参数提取方法,取得的突出成果如下：
1、自主创建了40nm工艺互连寄生参数提取的测试结构和电路,可用于提取互连寄生参数和参数提取准确性的校验。
2、自主提出并实现了对典型ITP文件及角ITP文件制作方法的优化方法和两者的完整提取流程,创造性地将3D互连寄生参数仿真与寄生电容结构测量校验嵌入互连寄生参数提取流程,提高了ITP文件中各工艺参数的准确性。
3、采用主成分分析法对互连线线间耦合寄生电容的相关性进行分析,且实现了包含线间耦合寄生电容相关性的互连RC寄生参数提取方法。
本文进行的工艺相关寄生提取方法经过了电路性能测量验证,环形振荡器电路布线后蒙特卡洛仿真值与测量数据统计结果之间的拟合误差达到了产业技术要求。因此,本文提出并实现的工艺波动相关的互连寄生参数提取方法不仅可应用于高端芯片的精准统计仿真,减小“过设计”,同时对互连工艺参数的调整和设定具有重要的指导意义。
As the IC process technology scales into sub-100nm, delay induced by back-end interconnects become larger. It overtakes the delay induce by MOSFET gates and become the main part of circuits delay in Integrated Circuits (IC) and the main course that limits IC's performance. It is critical to use Layout Parasitic Extraction (LPE) tools to accurately extract interconnects'parasitic resistances and capacitances in aimed IC. Running post-layout simulation with these extracted parasitic RC instances is more and more important.
16-inch Wafers are overtaking12-inch wafers to fabricated deep sub-nanometer VLSI. Even larger wafer will be developed. Interconnects layers'number in IC has grown to8-9, even ten. The advanced semi-conductor process is so complicated that the process conditions differ greatly in different wafers or in different dies at the same wafer. These differences may affect the effective unit parasitic parameters of backend interconnect and lead to parasitic parameters'variation. It becomes a very important research topic that how to accurately extract the statistical parasitic instances of backend interconnects, make them be able to describe the influence of semi-conductor backend process variation on interconnects and finally use them in post-layout simulation for ICs.
This paper focused on interconnect parasitic parameters extraction on40nm CMOS process technology and try to present a complete method to extract a process variation-aware Interconnect technology Profile. In order to investigate the inter-line parasitic capacitances between metal interconnects in the same layer and intra-layers parasitic capacitances between interconnects in the two neighbor layers, find out the connection between their values and process variation, this paper design five test keys for modeling interconnects:(1).Metal Comb test structures on one single metal layer for parasitic metal inter-line Capacitors measurements and extraction of thickness of metal layers and width loss induced by etch process.(2). Structure composed of comb layout on two neighbor layers cross over each other for the parasitic intra-layer MOM Capacitors measurement and extraction of thickness of every single dielectric layer between two neighbor metal layers as well as its permittivity.(3) Inverter Ring Oscillators (RO) for unit gate delay measurement without any metal RC load;(4).Inverter RO with small parasitic inter-line coupling capacitors loaded between every two inverters. Their results of post-layout simulation after parasitic extractions are able to verify accuracy of extraction rule related to inter-line parasitic capacitances.(5).Inverter RO with small parasitic intra-layer MOM metal capacitors loaded between every two inverters. Their results of post-layout simulation are able to verify accuracy of extraction rule related to intra-layer parasitic capacitances. In this paper,7different kinds of large inter-line coupling capacitors in M1-M7,5kinds of different intra-layer MOM metal capacitors in M1&M2-M6-M7and7kinds of inverter RO circuits are designed and manufactured with40nm dual damascene Copper interconnects process technology.
All the above-mentioned test structures are on-wafer scanning measured and statistically analyzed. The measurements data indicate the influence of process variation on parasitic capacitance of interconnects. First, there are large scale fluctuations in parasitic inter-line capacitances and intra-layer capacitances. Secondly, the inter-line coupling capacitances in metal layers made by the same process flow are largely correlated. The interconnects of M2-M7are all fabricated by dual Damascene process, correlation of their inter-line capacitor measured values are all above77%; while inter-line capacitances in metal layers made by different process, for example, Ml fabricated by single Damascene process, have small correlations with inter-line capacitances of M2-M7. Correlations of Ml inter-line capacitor measured values between capacitors' in other layers are all below50%; Intra-layer capacitances have even smaller correlations because Correlations of all the intra-layer capacitor measured values are all below20%. These conclusions not only offer basis for variation-aware Interconnection Technology Profile (ITP) extraction but also indicate that correlations of interconnects process should be considered while tuning the process parameters in ITP file.
The most popular used backend interconnect parasitic RC parameters extraction method is ITP analyzing method. It is the method that defining totally80process parameters such as every single metal layer's thickness T, every single dielectric layer's thickness H、permittivity ε、Delta width induce by etch process ΔW、 Minimum interconnects width Wmin in an ITP file. Based on this ITP file, deduce and produce a RC extraction rule file; according to this rule file, finally extract the parasitic resistance and capacitance between each nodes in circuits netlist of a certain integrated circuits by LPE toolkit. In this traditional method only idealized parasitic resistance and capacitance value can be extracted from each node in circuits, it is impossible to simulate and evaluate the variation of parasitic resistance and capacitance generated by the process fluctuations. According to this, this paper optimize the extraction method of typical ITP and corner ITP, creatively present a parasitic capacitance correlation included process variation aware back-end interconnects parasitic parameters extraction method. For the first time, induce capacitance correlation analysis in interconnects parasitic capacitance extraction and embed the optimized extraction flow into the IC design flow. Monte Carlo simulations are cast on different types of Ring Oscillators circuits; the simulation results verify the accuracy of parasitic extraction method.
3D structures of the first kind and second kind of above-mentioned capacitors in are built in Synopsys's field-effect simulation software Raphael by inputting capacitors'layouts and initial ITP file measured by Transmission electron microscope. Simulations are performed on these structures in random walk method. Based on median value of these parasitic capacitors'measurements data, the typical process parameters value of each metal layer and dielectric layer are extracted and combined into the typical ITP file for this process technology. ITP file can be calibrated and optimized according to the comparison of simulated capacitance values and median measured values of parasitic capacitors. After the calibration, all the difference between simulated and measured capacitance are less than10%. Typical capacitance values are extracted according to extraction rules generated by the typical ITP file. The deviations of extracted values from median value of measurements are all less than10%. Based on typical ITP file, variation-aware ITP file is built according to the parasitic capacitor structures' statistical measurements. Upon distribution of these capacitors' value, the correlations between the values of inter-line capacitor in every single metal layer are analyzed by Principle Component Analysis (PCA). Three principle components of M2-M7inter-line coupling parasitic capacitors which have more than98%accumulative contribute rate are calculated based on their measurements'distribution by PCA. The load factors of these three main principle components are calculated, according to which the standard deviation values of inter-line capacitors'values excluded correlation factors are obtained. The standard deviation values can be used to build statistical model of ITP related process parameters. Using rule derived from the optimized40nm variation-aware statistical ITP, post-layout netlists including variation-aware parasitic can be extracted on RO loaded with inter-line capacitors and intra-layer capacitors. Finally, Monte Carlo simulations are performed upon the netlists and the statistical distribution of simulation data is very consistent with the statistical distribution of actual circuits' measurements. The output signal periods of33stages RO loaded with M1inter-line capacitors mean measured values and Monte Carlo simulated values only have2.54%difference between each other's and difference between their standard deviations is only3.65%; the two differences number between simulated and measured values of11stages RO loaded with M2inter-line capacitors are-9.16%and9.89%; the two differences number of33stages RO loaded with M1&M2intra-layer capacitors are-1.7%and8.22%. All the Monte Carlo simulated mean value and standard deviation of RO verification ciruits'signal periods have less than10%differences compared to their measured data. It is qualified according to IC industry standard.
Based on state-owned40nm process platform, this paper independently establishes and optimizes the40nm CMOS process variation-aware interconnects technology profile extraction method; the outstanding results achieved are as follows:
1. Independently, create a set of test structures for the40nm CMOS process interconnects parameters' extraction. Including the parasitic capacitors for ITP extraction and Ring Oscillators for circuits' simulation verification.
2. Independently optimize the traditional typical ITP file extraction method; present a new complete extraction flow; creatively embed the3D backend parasitic simulations and the RC extraction toolkits'calibration by parasitic capacitors measurements into ITP extraction flow. The accuracy of process parameters in typical ITP file is highly improved.
3. Upon distribution of parasitic capacitors' measurements, the correlations between the values of parasitic coupling capacitor in every single metal layer are analyzed by Principle Component Analysis. Extraction method of variation-aware ITP file including the correlation ship of single-layer coupling capacitors related process parameters is presented. The Monte Carlo simulation results of RO circuits' postlayout extracted netlists quite fit the mesurements statistical data, which is up to the standard of industry.
引文
[1]Mao-Chyuan Tang, Chin-Chuan Cheng, Meng-Fan Wang, "A Nondestructive Method of Extracting the Width and Thickness of Interconnects for a 40-nm Technology" [J] IEEE Transaction on Electron Devices, VOL.56, NO.9, September 2009.
[2]International Technology Roadmap for Semiconductors,2005 Edition, Interconnect, P.9, [M] Table 80a.
[3]Y. Zhou, Z. Li, Y. Tian, W. Shi, and F. Liu, "A new methodology for interconnect parasitics extraction considering photo-lithography effects," [J] ASP-DAC,2007, pp.450-455.
[4]International Technology Roadmap for Semiconductors,2005 Edition, Interconnect, P.5, [M]
[5]J.-H. Lee, K.-H. Lax, J.-K. Park, et al., "An indirect extraction of interconnect technology parameters for efficient statistical interconnect modeling and its applications," [C] IEEE International Workshop Statistical Metrology.,2000, pp.38-41.
[6]W. Gong. W. Yu, and Y Lu. "A parasitic extraction method of VLSI interconnects for pre-route timing analysis," [C] ICCCAS,2010, pp.871-875.
[7]S.-Y. Oh, W. Y Jung, J.-T. Kong, and K.-H. Lee, "Interconnect modeling in deep submicron design," [C] 6th ICVC,1999, pp.73-80.
[8]Verilux Design Technology.. Sunnyvale, CA, [Z] SWIM User's Guide 1.0,1999.
[9]Kaanta.C.W. Bombardier.S.G, Cote.W,J., et al. "Dual Damascene:a ULSI wiring technology," [C] Eighth International IEEE VLSI Multilevel Interconnection Conference,1991, Page(s): 144-152.
[10]Yang.S., Ahmed. S., Arcot.B.,et al. "A high performance 180 nm generation logic technology,' [C] International Electron Devices Meeting,1998. Technical Digest. Page(s):197-200.
[11]Mandal. R.P.. Cheung.D.. Wai-Fan Yau.Cohen,et al. "Comparison of κ<3 silicon oxide-based dielectric pre-copper metallization preclean processes using black diamond." [C], IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop,1999, Page(s):299-303.
[12]Van Driel, W.D., Grech, A.-M., Hauck, et al. "Virtual Prototyping based Design Optimization of the Substrate. Leadframe, and Flip Chip Package Families with Low-k Technology," [C], The International Conference on Thermal Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems,2006. EuroSime 2006.7,2006 Page(s):1-6.
[13]IEEE Standard for Integrated Circuit (IC) Delay and Power Calculation System, "IEEE Standard 1481-1999," [Z] IEEE Computer Society, New York,1999.
[14]Kobayashi, S., Edahiro, M, Hayashi, Y, et al."New interconnect structure design methodology by Layout-design-based Interconnect Structure Optimization System (LAD1NOS)," [C], The IEEE 2000 International Interconnect Technology Conference,2000, Page(s):12-14.
[15]Raphael User Guide and Raphael Reference Manual, Synopsys, Inc., [Z], June 2009.
[16]Star-RCXT User guide, Star-RCXT Version D-2010.06, Synopsys, Inc. [Z],June 2010.
[17]J.wang, P.Ghanta, S. Vrudhula, et al. "Stochastic analysis of interconnect performance in the presence of process variations," [C] The 2004 IEEE/ACM International conference on Computer-aided design, Pages 880-886.
[18]Ghanta, P., Vrudhula, S., "Variational interconnect delay metrics for statistical timing analysis," [C] 7th International Symposium on Quality Electronic Design, ISQED '06,2006, Page(s):6 pp.-24.
[19]"Field solver technologies for variation-aware interconnect parasitic extraction," [D] Tarek El-Moselhy, Massachusetts Institute of technology,2010.2.
[20]Mutlu, A., Jiayong Le, Molina, R., et al."Parametric analysis to determine accurate interconnect extraction corners for design performance," [C] Quality Electronic Design of Electronic Design,2009.Page(s):419-423.
[21]HX Zhang, J Li, D Lin, et al. "40nm Low Power MOSFET Transistor VT Fluctuation Control" [J] ECS Transactions,2012.volume 44, issue 1.P767-771.
[22]杨杨.考虑工艺波动的互连信号完整性分析[D].西安：西安电子科技大学,2009.
[23]薛萌.考虑工艺波动的互连功耗分析[D].西安：西安电子科技大学,2011.
[1]Kucar. D.Vannelli. "A.InterconnectionModelling Using Distributed RLC Models,"[C] The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications,2003. Page(s):32-35.
[2]Tani. S., Uchida.Y Furuie.M. "Parasitic capacitance modeling for multi-level interconnects," [C] 2002 Asia-Pacific Conference on Circuits and Systems. Volume: 1 Page(s):59-64.
[3]Weibing Gong, Wenjian Yu, Yongqiang Lu, et al. "A Parasitic Extraction Method of VLSI Interconnects for Pre-Route Timing Analysis" [C].2010 International Conference on Communications, Circuits and Systems (ICCCAS).2010, Page(s):871-875.
[4]Roberto Suaya, Rafael Escovar, Salvador Ortiz, et al. "Modeling and Extraction of Nanometer Scale Interconnects Challenges and Opportunities," [C] 23rd Advanced Metallization Conference.2006.
[5]Wenjian Yu, Zeyi Wang, Jiangchun Gu,"Fast capacitance extraction of actual 3-D VLSI interconnects using quasi-multiple medium accelerated BEM," [J] IEEE Transactions on Microwave Theory and Techniques, Volume: 51, Issue: 1, Part:1.2003,Page(s):109-119.
[6]吴启明,王泽毅 “边界元素法在集成电路CAD中的应用”[J]《计算物理》1992年03期
[7]Savidis.I.,"Closed-Form Expressions of 3-D Via Resistance, Inductance, and Capacitance," [J] IEEE Transactions on Electron Devices, Sept.2009 Volume: 56, Issue: 9 Page(s):1873-1881.
[8]International Technology Roadmap for Semiconductors,2005 Edition, Interconnect, P.6, [M] Figure 70.
[9]Tagai.M., Fukai.T. Hiro.M. "Cu single damascene interconnects with plasma-polymerized organic polymes (k=2.6) for high-speed,0.1 μm CMOS devices," [C] International Electron Devices Meeting,2000.Page(s):851-853.
[10]Shyue-Shyh Lin, Chih-Wei Chen, Shien-Ming Huang, et al."An optimized integration scheme for 0.13 μm technology node dual-damascene Cu Interconnect," [C] Interconnect Technology Conference, 2000, Page(s):273-275.
[11]Lee.K.W., Shin.H.J., Hwang.J.W, et al. "Highly manufacturable Cu/low-k dual damascene process integration for 65nm technology node," [C] Interconnect Technology Conference,2004, Page(s):57-59.
[12]周从树,辅助图形在工艺窗口OPC模型中的应用以及广义OPC的概念[D].上海：复旦大学,2009.5-7.
[13]J.Steigerwald, M. Zirpoli, S. P. Murarka, et al. "Pattern geometry in chemical mechanical polishing of inlaid copper structures," [J] Journal Electrochem. Society, vol.141, no.10, pp.2842- 2848, Oct.1994.
[14]J. T. Pan, P. Li, K. Wijekoon, S. Tsai, and F. Redekar, "Copper CMP integration and time dependent pattern effect," [C] Int. Interconnect Technology Conf.,1999. pp.164-166.
[15]Chang.E., Stine.B. Maung.T, et al. "Using a Statistical Metrology Framework to Identify Systematic and Random Sources of Die and Waferlevel ILD Thickness Vaiation in CMP Processes" [C] International Electron Devices Meeting,1995. Page(s):499-502.
[16]Ohta. T.,Fujinaga. M.,Kimura. M, et al."A simulation system for capacitance variation by CMP process including defocus effect" [C] International Conference on Simulation of Semiconductor Processes and Devices, Page(s):102-105.
[1]Yeo.A., Wong Foo Lam, Lee. C. et al. "Development of Novel Joint Resistance Modeling Technique for Flip Chip Interconnection Systems," [C] 31st International Conference on Electronics Manufacturing and Technology,2006,Page(s):115-119.
[2]Kunikiyo.T., Watanabe.T., Kanamoto.T., et al. "Test Structure Measuring Inter- and Intralayer Coupling Capacitance of Interconnection With SubfemtoFarad Resolution," [J] IEEE Transactions on Electron Devices, Volume: 51, Issue: 5,2004, Page(s):726-735.
[3]Yungseon Eo, Eisenstadt.W.R., Ju Young Jeong, et al. "A New On-Chip Interconnect Crosstalk Model and Experimental Verification for CMOS VLSI Circuit Design," [J] IEEE Transactions on Electron Devices, Volume: 47, Issue: 1,2000, Page(s):129-140.
[4]Xiaoxiao Wang, Tehranipoor.M., Datta, R., et al. "Path-RO:A novel on-chip critical path delay measurement under process variations," [C] IEEE/ACM International Conference on Computer-Aided Design,2008, Page(s): 640-646.
[5]Das.B.P., Amrutur.B., Jamadagni.H.S., et al. "Within-Die Gate Delay Variability Measurement Using Reconfigurable Ring Oscillator," [J] IEEE Transactions on Semiconductor Manufacturing, Volume: 22, Issue:2,2009, Page(s):256-267.
[6]Lane.T., Belcourt.F., Jensen.R., et al. "Electrical Characteristics of Copper/Polyimide Thin-Film Multilayer Interconnects," [J] IEEE Transactions on Components, Hybrids, and Manufacturing Technology,Volume:10, Issue:4,1987, Page(s):577-585.
[7]夏学江,史斌星,陈惟荣.”电磁学”[M]清华大学出版社,1994年6月,P157-159
[8]V V Sarwate, "Electromagnetic Fields And Waves," [M] New Age International(P) Ltd.,2006 P131.
[9]苏武浔,魏腾雄,陈燊年”各向异性介质中的静电场强度与高斯定理,”[J]华侨大学学报(自然科学版)1996年10月第17卷第4期P411-414.
[10]El-Moselhy.T.A., Elfadel.I.M, Daniel. L, et al. "Ahierarchical floating random walk algorithm for fabric-aware 3D capacitance extraction," [C] International Conference on Computer-Aided Design - Digest of Technical Papers,2009. Page(s):752-758.
[11]El-Moselhy.T.A., Elfadel.I.M., Daniel.L., et al. "A capacitance solver for incremental variation-aware extraction," [C] International Conference on Computer-Aided Design 2008.Page(s):662-669.
[12]Brambilla.A.; Maffezzoni.P., "A statistical algorithm for 3D capacitance extraction," [J] IEEE Microwave and Guided Wave Letters,Volume:10, Issue:8,2000, Page(s):304-306.
[13]Raphael NXT User Guide,Version A-2008.06, Synopsys, Inc., [Z], June 2008.
[1]Weibing Gong, Wenjian Yu, Yongqiang Lu, "A Parasitic Extraction Method of VLSI Interconnects for Pre-Route Timing Analysis," [C] 2010 International Conference on Communications, Circuits and Systems (ICCCAS),2010, Page(s):871-875.
[2]Basel. M.,"Accurate and efficient extraction of interconnect circuits for full-chip timing analysis" Microelectronics Communications Technology Producing Quality Products Mobile and Portable Power Emerging Technologies'1995.
[3]C. Q. Shi, J.Wu, C. Y Chang, et al. "Study of LVS Methodology for Layout Physical Verfication" [J]. Chinese Journal of Electron Devices,2002,125 (2):165-169.
[4]xCalibrate Interactive User's Manual Version 2007.4, Mentor Graphics, Inc. [Z] 2007. [5]Star-RCXT User guide, Star-RCXT Version D-2010.06, Synopsys, Inc. [Z], June 2010.
[6]Mao-Chyuan Tang, Chin-Chuan Cheng, Meng-Fan Wang, et al., "A Nondestructive Method of Extracting the Width and Thickness of Interconnects for a 40-nm Technology," IEEE Transactions on Electron Devices, Volume:56, Issue: 9,2009, Page(s):1891-1896.
[1]Mutlu.A., Jiayong Le, Molina.R., et al. "Parametric Analysis to Determine Accurate Interconnect Extraction Corners for Design Performance." [C] Quality of Electronic Design,2009 Page(s):419-423.
[2]Soo-Young Oh, Won-Young Jung, Jeong-Taek Kong, et al, "Interconnect modeling in deep submicron design," [C] 6th International Conference on VLSI and CAD,1999, Page(s):73-80
[3]盛骤,谢式千,潘承毅, “概率论与数理统计”[M]浙江大学：高等教育出版社,2008年6月,第四版：P46-50.
[4]Ning Lu, "Statistical and Corner Modeling of Interconnect Resistance and Capacitance," [C] IEEE Custom Integrated Circuits Conference,2006, Page(s):853-856.
[5]Doganis.A., Chen.J.C., "Interconnect Simple, Accurate and Statistical Models Using On-Chip Measurements for Calibration," [C] Twelfth International Conference On VLSI Design, 1999,Page(s):120-125.
[6]Joo-Hee Lee, Keun-Ho Lee, Jin-Kyu Park, et al, "An indirect extraction of interconnect technology parameters for efficient statistical interconnect modeling and its applications," [C] 5th International Workshop on Statistical Metrology,2000, Page(s):38-41.
[1]Joo-Hee Lee, Keun-Ho Lee, Jin-Kyu Park, "An indirect Extraction of hterconnect Technology parameters for Efficient Statistical Interconnect Modeling and Its Applications," [C] 5th International Workshop on Statistical Metrology.,2000, Page(s):38-41.
[2]Jun-Fu Huang, Changm VCY, Liu, S.,"Modeling Sub-90nm On-Chip Variation Using Monte Carlo Method for DFM" [C] Asia and South Pacific Design Automation Conference,2007,Page(s): 221-225.
[3]El-Moselhy.T., Daniel.L., "Variation-aware interconnect extraction using statistical moment preserving model order reduction," [C] Design, Automation & Test in Europe Conference & Exhibition (DATE),2010, Page(s):453-458.
[4]Brambilla,A.. Maffezzoni.P., "Statistical Method for the Analysis of Interconnects Delay in Submicrometer Layouts," [J] IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume:20, Issue:8,2001,Page(s):957-966.
[5]Ying Liu, Pileggi.L.T., Strojwas.A.J.,"Model Order-Reduction of RC(L) Interconnect including Variational Analysis," [C] 36th Design Automation Conference,1999, Page(s):201-206.
[6]黄恒君.项泾渭,刘晓梅,”主成分回归分析的直接实现——基于SPSS二次开发”,[J]《甘肃科学学报》2007年第19卷第2期.
[7]J.Cadima, I.T.Jolliffe, "Loading and correlations in the interpretation of principle compenents," [J] Journal of Applied Statistics, Volume 22, Issue 2,1995, Pages 203-214.
[8]张梅,张瑰,“二维变量的主成分分析和回归分析的关系研究”,[J]《数学的实践与以识》2010年第40卷第24期.
[9]Fan.J., Ning Mi, Tan.S.X.-D., "Statistical Model Order Reduction for Interconnect Circuits Considering Spatial Correlations," [C] Design, Automation & Test in Europe Conference & Exhibition,2007.Page(s):1-6.
[11]Star-RCXT User guide. Star-RCXT Version D-2010.06, Synopsys, Inc. [Z], June 2010.
[2]International Technology Roadmap for Semiconductors,2005 Edition, Interconnect, P.9, [M] Table 80a.
[3]Y. Zhou, Z. Li, Y. Tian, W. Shi, and F. Liu, "A new methodology for interconnect parasitics extraction considering photo-lithography effects," [J] ASP-DAC,2007, pp.450-455.
[4]International Technology Roadmap for Semiconductors,2005 Edition, Interconnect, P.5, [M]
[5]J.-H. Lee, K.-H. Lax, J.-K. Park, et al., "An indirect extraction of interconnect technology parameters for efficient statistical interconnect modeling and its applications," [C] IEEE International Workshop Statistical Metrology.,2000, pp.38-41.
[6]W. Gong. W. Yu, and Y Lu. "A parasitic extraction method of VLSI interconnects for pre-route timing analysis," [C] ICCCAS,2010, pp.871-875.
[7]S.-Y. Oh, W. Y Jung, J.-T. Kong, and K.-H. Lee, "Interconnect modeling in deep submicron design," [C] 6th ICVC,1999, pp.73-80.
[8]Verilux Design Technology.. Sunnyvale, CA, [Z] SWIM User's Guide 1.0,1999.
[9]Kaanta.C.W. Bombardier.S.G, Cote.W,J., et al. "Dual Damascene:a ULSI wiring technology," [C] Eighth International IEEE VLSI Multilevel Interconnection Conference,1991, Page(s): 144-152.
[10]Yang.S., Ahmed. S., Arcot.B.,et al. "A high performance 180 nm generation logic technology,' [C] International Electron Devices Meeting,1998. Technical Digest. Page(s):197-200.
[11]Mandal. R.P.. Cheung.D.. Wai-Fan Yau.Cohen,et al. "Comparison of κ<3 silicon oxide-based dielectric pre-copper metallization preclean processes using black diamond." [C], IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop,1999, Page(s):299-303.
[12]Van Driel, W.D., Grech, A.-M., Hauck, et al. "Virtual Prototyping based Design Optimization of the Substrate. Leadframe, and Flip Chip Package Families with Low-k Technology," [C], The International Conference on Thermal Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems,2006. EuroSime 2006.7,2006 Page(s):1-6.
[13]IEEE Standard for Integrated Circuit (IC) Delay and Power Calculation System, "IEEE Standard 1481-1999," [Z] IEEE Computer Society, New York,1999.
[14]Kobayashi, S., Edahiro, M, Hayashi, Y, et al."New interconnect structure design methodology by Layout-design-based Interconnect Structure Optimization System (LAD1NOS)," [C], The IEEE 2000 International Interconnect Technology Conference,2000, Page(s):12-14.
[15]Raphael User Guide and Raphael Reference Manual, Synopsys, Inc., [Z], June 2009.
[16]Star-RCXT User guide, Star-RCXT Version D-2010.06, Synopsys, Inc. [Z],June 2010.
[17]J.wang, P.Ghanta, S. Vrudhula, et al. "Stochastic analysis of interconnect performance in the presence of process variations," [C] The 2004 IEEE/ACM International conference on Computer-aided design, Pages 880-886.
[18]Ghanta, P., Vrudhula, S., "Variational interconnect delay metrics for statistical timing analysis," [C] 7th International Symposium on Quality Electronic Design, ISQED '06,2006, Page(s):6 pp.-24.
[19]"Field solver technologies for variation-aware interconnect parasitic extraction," [D] Tarek El-Moselhy, Massachusetts Institute of technology,2010.2.
[20]Mutlu, A., Jiayong Le, Molina, R., et al."Parametric analysis to determine accurate interconnect extraction corners for design performance," [C] Quality Electronic Design of Electronic Design,2009.Page(s):419-423.
[21]HX Zhang, J Li, D Lin, et al. "40nm Low Power MOSFET Transistor VT Fluctuation Control" [J] ECS Transactions,2012.volume 44, issue 1.P767-771.
[22]杨杨.考虑工艺波动的互连信号完整性分析[D].西安：西安电子科技大学,2009.
[23]薛萌.考虑工艺波动的互连功耗分析[D].西安：西安电子科技大学,2011.
[1]Kucar. D.Vannelli. "A.InterconnectionModelling Using Distributed RLC Models,"[C] The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications,2003. Page(s):32-35.
[2]Tani. S., Uchida.Y Furuie.M. "Parasitic capacitance modeling for multi-level interconnects," [C] 2002 Asia-Pacific Conference on Circuits and Systems. Volume: 1 Page(s):59-64.
[3]Weibing Gong, Wenjian Yu, Yongqiang Lu, et al. "A Parasitic Extraction Method of VLSI Interconnects for Pre-Route Timing Analysis" [C].2010 International Conference on Communications, Circuits and Systems (ICCCAS).2010, Page(s):871-875.
[4]Roberto Suaya, Rafael Escovar, Salvador Ortiz, et al. "Modeling and Extraction of Nanometer Scale Interconnects Challenges and Opportunities," [C] 23rd Advanced Metallization Conference.2006.
[5]Wenjian Yu, Zeyi Wang, Jiangchun Gu,"Fast capacitance extraction of actual 3-D VLSI interconnects using quasi-multiple medium accelerated BEM," [J] IEEE Transactions on Microwave Theory and Techniques, Volume: 51, Issue: 1, Part:1.2003,Page(s):109-119.
[6]吴启明,王泽毅 “边界元素法在集成电路CAD中的应用”[J]《计算物理》1992年03期
[7]Savidis.I.,"Closed-Form Expressions of 3-D Via Resistance, Inductance, and Capacitance," [J] IEEE Transactions on Electron Devices, Sept.2009 Volume: 56, Issue: 9 Page(s):1873-1881.
[8]International Technology Roadmap for Semiconductors,2005 Edition, Interconnect, P.6, [M] Figure 70.
[9]Tagai.M., Fukai.T. Hiro.M. "Cu single damascene interconnects with plasma-polymerized organic polymes (k=2.6) for high-speed,0.1 μm CMOS devices," [C] International Electron Devices Meeting,2000.Page(s):851-853.
[10]Shyue-Shyh Lin, Chih-Wei Chen, Shien-Ming Huang, et al."An optimized integration scheme for 0.13 μm technology node dual-damascene Cu Interconnect," [C] Interconnect Technology Conference, 2000, Page(s):273-275.
[11]Lee.K.W., Shin.H.J., Hwang.J.W, et al. "Highly manufacturable Cu/low-k dual damascene process integration for 65nm technology node," [C] Interconnect Technology Conference,2004, Page(s):57-59.
[12]周从树,辅助图形在工艺窗口OPC模型中的应用以及广义OPC的概念[D].上海：复旦大学,2009.5-7.
[13]J.Steigerwald, M. Zirpoli, S. P. Murarka, et al. "Pattern geometry in chemical mechanical polishing of inlaid copper structures," [J] Journal Electrochem. Society, vol.141, no.10, pp.2842- 2848, Oct.1994.
[14]J. T. Pan, P. Li, K. Wijekoon, S. Tsai, and F. Redekar, "Copper CMP integration and time dependent pattern effect," [C] Int. Interconnect Technology Conf.,1999. pp.164-166.
[15]Chang.E., Stine.B. Maung.T, et al. "Using a Statistical Metrology Framework to Identify Systematic and Random Sources of Die and Waferlevel ILD Thickness Vaiation in CMP Processes" [C] International Electron Devices Meeting,1995. Page(s):499-502.
[16]Ohta. T.,Fujinaga. M.,Kimura. M, et al."A simulation system for capacitance variation by CMP process including defocus effect" [C] International Conference on Simulation of Semiconductor Processes and Devices, Page(s):102-105.
[1]Yeo.A., Wong Foo Lam, Lee. C. et al. "Development of Novel Joint Resistance Modeling Technique for Flip Chip Interconnection Systems," [C] 31st International Conference on Electronics Manufacturing and Technology,2006,Page(s):115-119.
[2]Kunikiyo.T., Watanabe.T., Kanamoto.T., et al. "Test Structure Measuring Inter- and Intralayer Coupling Capacitance of Interconnection With SubfemtoFarad Resolution," [J] IEEE Transactions on Electron Devices, Volume: 51, Issue: 5,2004, Page(s):726-735.
[3]Yungseon Eo, Eisenstadt.W.R., Ju Young Jeong, et al. "A New On-Chip Interconnect Crosstalk Model and Experimental Verification for CMOS VLSI Circuit Design," [J] IEEE Transactions on Electron Devices, Volume: 47, Issue: 1,2000, Page(s):129-140.
[4]Xiaoxiao Wang, Tehranipoor.M., Datta, R., et al. "Path-RO:A novel on-chip critical path delay measurement under process variations," [C] IEEE/ACM International Conference on Computer-Aided Design,2008, Page(s): 640-646.
[5]Das.B.P., Amrutur.B., Jamadagni.H.S., et al. "Within-Die Gate Delay Variability Measurement Using Reconfigurable Ring Oscillator," [J] IEEE Transactions on Semiconductor Manufacturing, Volume: 22, Issue:2,2009, Page(s):256-267.
[6]Lane.T., Belcourt.F., Jensen.R., et al. "Electrical Characteristics of Copper/Polyimide Thin-Film Multilayer Interconnects," [J] IEEE Transactions on Components, Hybrids, and Manufacturing Technology,Volume:10, Issue:4,1987, Page(s):577-585.
[7]夏学江,史斌星,陈惟荣.”电磁学”[M]清华大学出版社,1994年6月,P157-159
[8]V V Sarwate, "Electromagnetic Fields And Waves," [M] New Age International(P) Ltd.,2006 P131.
[9]苏武浔,魏腾雄,陈燊年”各向异性介质中的静电场强度与高斯定理,”[J]华侨大学学报(自然科学版)1996年10月第17卷第4期P411-414.
[10]El-Moselhy.T.A., Elfadel.I.M, Daniel. L, et al. "Ahierarchical floating random walk algorithm for fabric-aware 3D capacitance extraction," [C] International Conference on Computer-Aided Design - Digest of Technical Papers,2009. Page(s):752-758.
[11]El-Moselhy.T.A., Elfadel.I.M., Daniel.L., et al. "A capacitance solver for incremental variation-aware extraction," [C] International Conference on Computer-Aided Design 2008.Page(s):662-669.
[12]Brambilla.A.; Maffezzoni.P., "A statistical algorithm for 3D capacitance extraction," [J] IEEE Microwave and Guided Wave Letters,Volume:10, Issue:8,2000, Page(s):304-306.
[13]Raphael NXT User Guide,Version A-2008.06, Synopsys, Inc., [Z], June 2008.
[1]Weibing Gong, Wenjian Yu, Yongqiang Lu, "A Parasitic Extraction Method of VLSI Interconnects for Pre-Route Timing Analysis," [C] 2010 International Conference on Communications, Circuits and Systems (ICCCAS),2010, Page(s):871-875.
[2]Basel. M.,"Accurate and efficient extraction of interconnect circuits for full-chip timing analysis" Microelectronics Communications Technology Producing Quality Products Mobile and Portable Power Emerging Technologies'1995.
[3]C. Q. Shi, J.Wu, C. Y Chang, et al. "Study of LVS Methodology for Layout Physical Verfication" [J]. Chinese Journal of Electron Devices,2002,125 (2):165-169.
[4]xCalibrate Interactive User's Manual Version 2007.4, Mentor Graphics, Inc. [Z] 2007. [5]Star-RCXT User guide, Star-RCXT Version D-2010.06, Synopsys, Inc. [Z], June 2010.
[6]Mao-Chyuan Tang, Chin-Chuan Cheng, Meng-Fan Wang, et al., "A Nondestructive Method of Extracting the Width and Thickness of Interconnects for a 40-nm Technology," IEEE Transactions on Electron Devices, Volume:56, Issue: 9,2009, Page(s):1891-1896.
[1]Mutlu.A., Jiayong Le, Molina.R., et al. "Parametric Analysis to Determine Accurate Interconnect Extraction Corners for Design Performance." [C] Quality of Electronic Design,2009 Page(s):419-423.
[2]Soo-Young Oh, Won-Young Jung, Jeong-Taek Kong, et al, "Interconnect modeling in deep submicron design," [C] 6th International Conference on VLSI and CAD,1999, Page(s):73-80
[3]盛骤,谢式千,潘承毅, “概率论与数理统计”[M]浙江大学：高等教育出版社,2008年6月,第四版：P46-50.
[4]Ning Lu, "Statistical and Corner Modeling of Interconnect Resistance and Capacitance," [C] IEEE Custom Integrated Circuits Conference,2006, Page(s):853-856.
[5]Doganis.A., Chen.J.C., "Interconnect Simple, Accurate and Statistical Models Using On-Chip Measurements for Calibration," [C] Twelfth International Conference On VLSI Design, 1999,Page(s):120-125.
[6]Joo-Hee Lee, Keun-Ho Lee, Jin-Kyu Park, et al, "An indirect extraction of interconnect technology parameters for efficient statistical interconnect modeling and its applications," [C] 5th International Workshop on Statistical Metrology,2000, Page(s):38-41.
[1]Joo-Hee Lee, Keun-Ho Lee, Jin-Kyu Park, "An indirect Extraction of hterconnect Technology parameters for Efficient Statistical Interconnect Modeling and Its Applications," [C] 5th International Workshop on Statistical Metrology.,2000, Page(s):38-41.
[2]Jun-Fu Huang, Changm VCY, Liu, S.,"Modeling Sub-90nm On-Chip Variation Using Monte Carlo Method for DFM" [C] Asia and South Pacific Design Automation Conference,2007,Page(s): 221-225.
[3]El-Moselhy.T., Daniel.L., "Variation-aware interconnect extraction using statistical moment preserving model order reduction," [C] Design, Automation & Test in Europe Conference & Exhibition (DATE),2010, Page(s):453-458.
[4]Brambilla,A.. Maffezzoni.P., "Statistical Method for the Analysis of Interconnects Delay in Submicrometer Layouts," [J] IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume:20, Issue:8,2001,Page(s):957-966.
[5]Ying Liu, Pileggi.L.T., Strojwas.A.J.,"Model Order-Reduction of RC(L) Interconnect including Variational Analysis," [C] 36th Design Automation Conference,1999, Page(s):201-206.
[6]黄恒君.项泾渭,刘晓梅,”主成分回归分析的直接实现——基于SPSS二次开发”,[J]《甘肃科学学报》2007年第19卷第2期.
[7]J.Cadima, I.T.Jolliffe, "Loading and correlations in the interpretation of principle compenents," [J] Journal of Applied Statistics, Volume 22, Issue 2,1995, Pages 203-214.
[8]张梅,张瑰,“二维变量的主成分分析和回归分析的关系研究”,[J]《数学的实践与以识》2010年第40卷第24期.
[9]Fan.J., Ning Mi, Tan.S.X.-D., "Statistical Model Order Reduction for Interconnect Circuits Considering Spatial Correlations," [C] Design, Automation & Test in Europe Conference & Exhibition,2007.Page(s):1-6.
[11]Star-RCXT User guide. Star-RCXT Version D-2010.06, Synopsys, Inc. [Z], June 2010.