带锁存的高稳定性分段12位D/A转换器设计
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摘要
本文设计了一个带锁存的高稳定性分段12位D／A转换器，本转换器由一个高稳定性的次表面齐纳基准源、内部12位并行数字输入锁存器、权电流D／A单元、电压—电流转换单元及输出运算放大器等六大部分组成。在输入端加入了一个12位的数字信号锁存器，这样可以避免出现尖峰干扰。在基准源设计部分采用了一个次表面击穿齐纳二极管电压加两个BE结电压的温度特性互补设计方式，这样可以提高基准源的温度特性，同时在基准源的恒流源设计上采用了双恒流源串联的稳定结构，可以增强基准源的稳定性。在D／A转换单元设计部分采用三段加权电流转换结构，提高了D／A转换器的转换精度。
本D／A转换器在工作温度范围内保持严格的单调性、转换精度高(线性误差≤±1 LSB、微分误差≤±1 LSB)、转换速度快(电压输出建立时间≤3μs)、转换功耗低(功耗≤600mW)、温度性能好(增益温度系数≤30ppm)、输出电压幅度大(±10V)并且可以灵活应用于0～5V、0～10V、±2.5V、+5V、+10V多种输出范围。输入端数字信号锁存器对最小宽度为40ns的写脉冲进行响应，不仅可以为内部电路提供基准电压源，同时也可以为外部电路提供10V的参考电压输出。
本文所做的主要工作包括：简单介绍了单片集成D／A转换器件的发展动态以及集成D／A转换器的工作原理和设计方法，详细分析了该D／A转换器六大部分的工作原理以及设计思路，着重对次表面齐纳基准电源部分的温度补偿电路优化设计、基准源的双镜像电流源优化设计、D／A转换单元的高、中、低三段分段转换设计和模拟差分开关对设计的设计思路以及工作原理进行了详细的理论分析和推导。同时简单介绍了模拟集成电路的基本工艺流程和基本工艺标准。然后根据中国电子科技集团第24研究所所提供的模拟集成电路工艺标准，完成了整个D／A转换器的电路制版工作，并附上电路版图。最后利用Candence软件建立了仿真电路模型，对电路原理进行功能仿真分析，就该D／A转换器的差分非线性误差、单调性、线性误差、基准源温度特性和D／A转换器建立时间等性能指标进行了模拟仿真。
This dissertation designs a high stability subsection D/A convertor with 12 bits signal input flip-latch.The converter is made up of a high stability subsurface zener benchmark power supplye, an inside 12 bits parallel digital signal input flip-latch,an authority current D/A conversion cell, a voltage-current conversion cell and an output operation amplifier.Adding a 12 bits signal flip-latch to the input port so that the DAC can avoid the peak interference.To design the subsurface zener benchmark power supplye,the dissertation chooses the way of a zener diode voltage and two BE voltage in order to improve the temprature characteristic of the benchmark power supplye and the dissertation also applies a double mirror image current to the benchmark power supplye in order to strengthen the stability of the benchmark power supplye. To design the D/A convertor part the dissertation divide the D/A convertor to three authority current segments so that the DAC can increase the precision of the convertor.
When this kind of converter is working at the prescribed temperature confine,it keeps being humdrum character,high precision of the conversion(linetype error ≤ ± 1 LSB、 differential coefficient error ≤ ±1 LSB), speediness(the time of establishing the putput voltage ≤3 μ s), low power consume(power consume ≤ 600mW),good temperature capability(the temperature coefficient ≤30ppm), large-scale output range.This convertor response to a write pulse whose least width is 40 μ s. This converter can not only offer inside benchmark voltage,but also offer outside 10V benchmark voltage.
The primary work of the dissertation is that the dissertation simply introduces the development of the integration D/A convertor and its working principle and also the way of designing it. This dissertation specially analyses and design the parts of subsurface zener benchmark power supplye,the double mirror image current design, the idea to detach the converter to high、 middle and low three segments and the design of difference switch circuit. The dissertation introduces the technics processes of the analog integrated circuit .At last, according to the technics standard that supplied by the 24th graduate school of China electronic company,the dissertation finishs the circuit diagram of the D/A converter,and also adds the circuit diagram in this discourse.The
本D／A转换器在工作温度范围内保持严格的单调性、转换精度高(线性误差≤±1 LSB、微分误差≤±1 LSB)、转换速度快(电压输出建立时间≤3μs)、转换功耗低(功耗≤600mW)、温度性能好(增益温度系数≤30ppm)、输出电压幅度大(±10V)并且可以灵活应用于0～5V、0～10V、±2.5V、+5V、+10V多种输出范围。输入端数字信号锁存器对最小宽度为40ns的写脉冲进行响应，不仅可以为内部电路提供基准电压源，同时也可以为外部电路提供10V的参考电压输出。
本文所做的主要工作包括：简单介绍了单片集成D／A转换器件的发展动态以及集成D／A转换器的工作原理和设计方法，详细分析了该D／A转换器六大部分的工作原理以及设计思路，着重对次表面齐纳基准电源部分的温度补偿电路优化设计、基准源的双镜像电流源优化设计、D／A转换单元的高、中、低三段分段转换设计和模拟差分开关对设计的设计思路以及工作原理进行了详细的理论分析和推导。同时简单介绍了模拟集成电路的基本工艺流程和基本工艺标准。然后根据中国电子科技集团第24研究所所提供的模拟集成电路工艺标准，完成了整个D／A转换器的电路制版工作，并附上电路版图。最后利用Candence软件建立了仿真电路模型，对电路原理进行功能仿真分析，就该D／A转换器的差分非线性误差、单调性、线性误差、基准源温度特性和D／A转换器建立时间等性能指标进行了模拟仿真。
This dissertation designs a high stability subsection D/A convertor with 12 bits signal input flip-latch.The converter is made up of a high stability subsurface zener benchmark power supplye, an inside 12 bits parallel digital signal input flip-latch,an authority current D/A conversion cell, a voltage-current conversion cell and an output operation amplifier.Adding a 12 bits signal flip-latch to the input port so that the DAC can avoid the peak interference.To design the subsurface zener benchmark power supplye,the dissertation chooses the way of a zener diode voltage and two BE voltage in order to improve the temprature characteristic of the benchmark power supplye and the dissertation also applies a double mirror image current to the benchmark power supplye in order to strengthen the stability of the benchmark power supplye. To design the D/A convertor part the dissertation divide the D/A convertor to three authority current segments so that the DAC can increase the precision of the convertor.
When this kind of converter is working at the prescribed temperature confine,it keeps being humdrum character,high precision of the conversion(linetype error ≤ ± 1 LSB、 differential coefficient error ≤ ±1 LSB), speediness(the time of establishing the putput voltage ≤3 μ s), low power consume(power consume ≤ 600mW),good temperature capability(the temperature coefficient ≤30ppm), large-scale output range.This convertor response to a write pulse whose least width is 40 μ s. This converter can not only offer inside benchmark voltage,but also offer outside 10V benchmark voltage.
The primary work of the dissertation is that the dissertation simply introduces the development of the integration D/A convertor and its working principle and also the way of designing it. This dissertation specially analyses and design the parts of subsurface zener benchmark power supplye,the double mirror image current design, the idea to detach the converter to high、 middle and low three segments and the design of difference switch circuit. The dissertation introduces the technics processes of the analog integrated circuit .At last, according to the technics standard that supplied by the 24th graduate school of China electronic company,the dissertation finishs the circuit diagram of the D/A converter,and also adds the circuit diagram in this discourse.The
引文
[1] 刘书明，刘斌 高性能数模与模数转换器件 西安：西安电子科技大学出版社，2000
[2] 陈贵灿，邵志标，程军，林长贵 CMOS集成电路设计 西安：西安交通大学出版社，2000
[3] 许居衍，徐世六 关于A／D、D／A转换器发展动向的一些思考[J] 微电子学，1998 217-223
[4] Kester. W. High speed—design techniques. Analog Device Inc. 1999 4-37—4-40
[5] 陈震初 发展我国数据转换电路的几点建议[J] 微电子学 1998 28(4) 233-235
[6] Klaas Bult, "High Speed DAC's", Broadcom Netherlands BV Bunnik, May 2000
[7] P.R. Gray R.G. Meyer, Analysis and Design of Analog Integrated Circuit, New York, Wiley, 1977, 1984
[8] 于继洲 集成A／D和D／A转换器应用技术[M] 北京：国防工业出版社，1989
[9] 复旦大学微电子教研组 模拟集成电路[M] 北京：高等教育出版社，1983
[10] P.R. Gray R.G. Meyer, MOS operational amplifier design—tutorial overview, IEEE J. Solid-State Circuit, Dec. 1982
[11] R.J.Widlar. "New Developments in IC Voltage Regulators," IEEE Journal df solid-State Cireuits, Vol. SC-6, pp.2～7, February 1971.
[12] 贾松良 双极集成电路分析与设计基础[M]．北京：电子工业出版社，1987
[13] 李联 MOS运算放大器—原理、设计、与运用[M] 上海：复旦大学出版社，1988
[14] D.B. Ribner and M.A. Copeland, Design techniques for cascaded CMOS Op Amps with improved PSRR and common-mode input range, IEEE J. Solid-State Circuit, vol SC- 19, No.6, Dec. 1984
[15] B. Gilbert, Wideband Negative-Current Mirror, Electronics Letters, Vol. 11, No. 6 1975
[16] C. Toumazou F.J. Lidgey & D.G.Haigh编，姚玉洁、冯军、尹洪等译 模拟集成电路设计—电流模法[M] 北京：高等教育出版社，1996
[17] M.G. Degrauwe, J. Rijmenants, E. A. Vittoz, and H.. J. De Man, Adaptive biasing CMOS amplifiers, IEEE J. Solid—State Circuit, Vol. SC—17, June, 1982
[18] J. E. Solomon, The Monolithic OP. Amp. A Tutorial Study, IEEE J. Solid—State Circuit, Vol. SC—9, June, 1974, PP.314—332
[19] C. T. Chuang, Analysis of the setting behavior of an operational amplifier, IEEE J. Solid—State Circuit, Vol. SC—17, Feb, 1982, PP.74—80
[20] Hogervorst R, Tero J P, Eschauzier R G H, et al. A compact power-efficient 3V CMOS rail-to-rail input/output operational amplifier for VLSI cell libraries [J]. IEEE J. Sol Sta Circ, 1994; 29(12): 1505-1512
[21] Hogervorst R, Tero J P, Huijsing J H. Compact CMOS constant-gm rail-to-rail input stage with gin-control by an electronic Zener diode [J]. IEEE J. Sol Sta Circ, 1996; 31 (7): 1035-1040
[22] Langen K J, Huijsing J H. Compact low-voltage power-efficient operational amplifier cells for VLSI [J]. IEEE J. Sol Sta Circ, 1998; 33(10): 1482-1496
[23] Sakurai S, Ismail M. Robust design of rail-to-rail CMOS operational amplifiers for a low power supply voltage [J]. IEEE J. Sol Sta Circ, 1996; 31 (2): 146-156
[24] 徐栋麟，林越，任俊彦 恒电压增益的低电压Rail-To-Rail运算放大器[J] 微电子学 2001 31(4)246-251
[25] 唐长文，张洁，闵昊 与工艺无关的Rail-To-Rail CMOS运算放大器[J] 微电子学 2002 32(1)46-50
[26] 刘凯，邵丙铣 一种低电压全摆幅CMOS运算放大器[J] 微电子学 2002 32(1) 51-53
[27] 周震，吴金，扬廉峰等 一种3V CMOS恒跨导运算放大器的设计 [J] 微电子学 2002 32(1) 51-53
[28] Hogervorst R, Huijsing J H. Design of low-voltage low-power operational amplifier cells [M]. Kluwer Academic Publishers, Netherlands
[29] E. A. Vittoz MOS Transistors Operated in the Lateral Bipolar Mode and Their Application in CMOS Technology [J]. IEEE J. Sol Sta Circ, Vol. SC-18 1983; PP: 273-279
[30] C. A. Laber, C. F. Rahim, S. F. Dreyer, etc, Design Considerations for a High performance 3-μm CMOS Analog Standard-Cell Library [J]. IEEE J. Sol Sta Circ, Vol. SC-22 1987; PP: 181-189
[31] E. A. Vittoz CMOS Voltage References Using Lateral Bipolar Transisters [J]. IEEE J. Sol Sta Circ, Vol. SC-20 1985; PP: 1151-1157
[32] T. Pan and A. A. Abidi, A 50dB Variable Gain Amplifier Using Parasitic Bipolar Transistor in CMOS [J]. IEEE J. Sol Sta Circ, Vol. SC-24 1989; PP: 951-961
[33] 刘韬 徐志伟 程君侠 一种高电源抑制比CMOS能隙基准电压源[J] 微电子学 1999 29(2) 128-131
[34] Song B S, Gray P R. A precision curvature compensated CMOS bandgap reference. [J]. IEEE J. Sol Sta Circ, 1983; 18(6) PP: 634-643
[35] Nicollini G, Senderowicz D. A CMOS bandgap reference for differential signal processing [J]. IEEE J. Sol Sta Circ, I991; 26(1) PP: 41-51
[36] Tham K-M, Nagaraj K. A low supply voltage high PSRR voltage reference in CMOS process [J]. IEEE J. Sol Sta Circ, 1995; 30(1) PP: 586-590
[2] 陈贵灿，邵志标，程军，林长贵 CMOS集成电路设计 西安：西安交通大学出版社，2000
[3] 许居衍，徐世六 关于A／D、D／A转换器发展动向的一些思考[J] 微电子学，1998 217-223
[4] Kester. W. High speed—design techniques. Analog Device Inc. 1999 4-37—4-40
[5] 陈震初 发展我国数据转换电路的几点建议[J] 微电子学 1998 28(4) 233-235
[6] Klaas Bult, "High Speed DAC's", Broadcom Netherlands BV Bunnik, May 2000
[7] P.R. Gray R.G. Meyer, Analysis and Design of Analog Integrated Circuit, New York, Wiley, 1977, 1984
[8] 于继洲 集成A／D和D／A转换器应用技术[M] 北京：国防工业出版社，1989
[9] 复旦大学微电子教研组 模拟集成电路[M] 北京：高等教育出版社，1983
[10] P.R. Gray R.G. Meyer, MOS operational amplifier design—tutorial overview, IEEE J. Solid-State Circuit, Dec. 1982
[11] R.J.Widlar. "New Developments in IC Voltage Regulators," IEEE Journal df solid-State Cireuits, Vol. SC-6, pp.2～7, February 1971.
[12] 贾松良 双极集成电路分析与设计基础[M]．北京：电子工业出版社，1987
[13] 李联 MOS运算放大器—原理、设计、与运用[M] 上海：复旦大学出版社，1988
[14] D.B. Ribner and M.A. Copeland, Design techniques for cascaded CMOS Op Amps with improved PSRR and common-mode input range, IEEE J. Solid-State Circuit, vol SC- 19, No.6, Dec. 1984
[15] B. Gilbert, Wideband Negative-Current Mirror, Electronics Letters, Vol. 11, No. 6 1975
[16] C. Toumazou F.J. Lidgey & D.G.Haigh编，姚玉洁、冯军、尹洪等译 模拟集成电路设计—电流模法[M] 北京：高等教育出版社，1996
[17] M.G. Degrauwe, J. Rijmenants, E. A. Vittoz, and H.. J. De Man, Adaptive biasing CMOS amplifiers, IEEE J. Solid—State Circuit, Vol. SC—17, June, 1982
[18] J. E. Solomon, The Monolithic OP. Amp. A Tutorial Study, IEEE J. Solid—State Circuit, Vol. SC—9, June, 1974, PP.314—332
[19] C. T. Chuang, Analysis of the setting behavior of an operational amplifier, IEEE J. Solid—State Circuit, Vol. SC—17, Feb, 1982, PP.74—80
[20] Hogervorst R, Tero J P, Eschauzier R G H, et al. A compact power-efficient 3V CMOS rail-to-rail input/output operational amplifier for VLSI cell libraries [J]. IEEE J. Sol Sta Circ, 1994; 29(12): 1505-1512
[21] Hogervorst R, Tero J P, Huijsing J H. Compact CMOS constant-gm rail-to-rail input stage with gin-control by an electronic Zener diode [J]. IEEE J. Sol Sta Circ, 1996; 31 (7): 1035-1040
[22] Langen K J, Huijsing J H. Compact low-voltage power-efficient operational amplifier cells for VLSI [J]. IEEE J. Sol Sta Circ, 1998; 33(10): 1482-1496
[23] Sakurai S, Ismail M. Robust design of rail-to-rail CMOS operational amplifiers for a low power supply voltage [J]. IEEE J. Sol Sta Circ, 1996; 31 (2): 146-156
[24] 徐栋麟，林越，任俊彦 恒电压增益的低电压Rail-To-Rail运算放大器[J] 微电子学 2001 31(4)246-251
[25] 唐长文，张洁，闵昊 与工艺无关的Rail-To-Rail CMOS运算放大器[J] 微电子学 2002 32(1)46-50
[26] 刘凯，邵丙铣 一种低电压全摆幅CMOS运算放大器[J] 微电子学 2002 32(1) 51-53
[27] 周震，吴金，扬廉峰等 一种3V CMOS恒跨导运算放大器的设计 [J] 微电子学 2002 32(1) 51-53
[28] Hogervorst R, Huijsing J H. Design of low-voltage low-power operational amplifier cells [M]. Kluwer Academic Publishers, Netherlands
[29] E. A. Vittoz MOS Transistors Operated in the Lateral Bipolar Mode and Their Application in CMOS Technology [J]. IEEE J. Sol Sta Circ, Vol. SC-18 1983; PP: 273-279
[30] C. A. Laber, C. F. Rahim, S. F. Dreyer, etc, Design Considerations for a High performance 3-μm CMOS Analog Standard-Cell Library [J]. IEEE J. Sol Sta Circ, Vol. SC-22 1987; PP: 181-189
[31] E. A. Vittoz CMOS Voltage References Using Lateral Bipolar Transisters [J]. IEEE J. Sol Sta Circ, Vol. SC-20 1985; PP: 1151-1157
[32] T. Pan and A. A. Abidi, A 50dB Variable Gain Amplifier Using Parasitic Bipolar Transistor in CMOS [J]. IEEE J. Sol Sta Circ, Vol. SC-24 1989; PP: 951-961
[33] 刘韬 徐志伟 程君侠 一种高电源抑制比CMOS能隙基准电压源[J] 微电子学 1999 29(2) 128-131
[34] Song B S, Gray P R. A precision curvature compensated CMOS bandgap reference. [J]. IEEE J. Sol Sta Circ, 1983; 18(6) PP: 634-643
[35] Nicollini G, Senderowicz D. A CMOS bandgap reference for differential signal processing [J]. IEEE J. Sol Sta Circ, I991; 26(1) PP: 41-51
[36] Tham K-M, Nagaraj K. A low supply voltage high PSRR voltage reference in CMOS process [J]. IEEE J. Sol Sta Circ, 1995; 30(1) PP: 586-590