集成电路缺陷分布模型和容错技术研究
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摘要
本文对集成电路制造过程中的缺陷空间分布模型和IC的容错结构及其成品率
做了系统地理论研究。主要研究结果如下：
根据缺陷在圆片上的位置首先给出了每个缺陷的模糊度，然后利用圆片上的
缺陷与缺陷之间、缺陷与缺陷团之间以及缺陷团与缺陷团之间的相关性定义了缺
陷团与团之间的相关系数，首次提出了适合于划分缺陷团的变步长模糊聚类算法
（CSFCM）。其次对采集到的一批有缺陷的圆片样本利用变步长的模糊聚类算法进
行缺陷团划分处理。最后对划分后的样本进行统计检验，得到了缺陷团在圆片上
服从参数为λ的Poisson分布、团内缺陷数服从参数为α的Reyleigh分布等规律。
根据前面得到的缺陷团在圆片上的分布以及团内缺陷数的分布等规律给出了
缺陷空间分布新模型。在XD—YES模拟器中，分别采用负二项式分布模型和新
模型作为空间分布模型对给定的IC版图进行模拟。模拟结果表明，在芯片面积比
较小时，两个模型模拟结果之间差别很小，并且与实测结果也很接近；当芯片面
积比较大时，两个模型模拟结果之间差别较大，新模型的模拟结果更接近于实测
结果。
本文根据用冗余行和冗余列修复缺陷阵列对应的二分图的特点，提出了一种
Hopfield网络算法，有效地解决了冗余行和冗余列的最小分配问题。通过大量的实
例验证，用该算法求解冗余行和冗余列的最小分配问题是十分有效的。
本文根据修复缺陷阵列时冗余行数和冗余列数的变化情况，利用Markov链精
确地分析了有冗余的存储器阵列的成品率。分析过程中考虑了缺陷的空间分布模
型对存储器芯片成品率的影响。实例分析表明，用Markov链方法分析有冗余的存
储器阵列的成品率比用传统的成品率分析方法精度高。
随着冗余行和冗余列加入到存储器阵列，芯片面积在增加，一个圆片上的有
效芯片数目在减少。本文综合考虑了当两级冗余加入芯片时，芯片面积的变化对
成品率的影响情况。在冗余行（列）数目和冗余模块数目给定的条件下，给出了把给
定容量的多兆位存储器最优地划分成若干模块的准则。对应这种划分可使存储器
芯片的成品率得到最优地改善。
容错技术主要集中在给系统中加入一定量的冗余单元来提高系统的成品
率。然而，由于不同类型的子电路所占的芯片面积不同，当给系统中加入一定量
的冗余单元时并没有使系统的成品率得到最优的改善。本文首次将整体优化的思
想应用于集成电路的容错设计中，利用最优化的思想，提出了在芯片面积增量一
集成电路缺陷分布模型和容错技术研究
定的条件下使系统成品率改善最大的最优化模型。利用遗传算法求解了该优化模
型。
实验结果表明，在芯片面积增量一定的条件f，为使芯片成品率达到最优地
改善，需要加入的冗余子电路数随着芯片上的缺陷密度的增加而增加：随电路中
支撑电路面积的增加而减少，其原因是支撑电路没有容错能力，一旦有缺陷落入
支撑电路，整个电路就会失效。
研究结果表明：本文提出的容错技术对于提高电路的动态和静态成品率和可
靠性是十分有效的。
Abstract
This dissertation airns at discussing the model of defect spatial distribution, IC's
fault-tolerant structures and yield. A large numbers of simulation examples show the
rnodels and the methods presented in this dissertation are very effective by using
XD-YES simulator (XiDian university held EStimator).
The autl1or's main contributions are as fOllowing f
First, the fozzy degree of each defect is defined according to the position of the
detbct o11 tIle wafbr and the correlative coefficient between a detbct cluster and a defect
cluster is defined An effective change-step fuzzy cluster algorithm (CSFCM), which is
suitable to partitioning the defects into clusters, is firstly presented in this dissertation
'1-lle (listributioIl of tl1e 11ull1ber of clusters oIl tlle 1vafer, x\/hicl1 obeys Poisso11's
distribution with;. as a parameter, and the distribution of the number of defects in a
clLlster, 1vIlicI1 obeys Releigll's distributiOIl with a as a paraIl1eter, are obtained by
statistic and testing the data.
The new defect spatial distribution is presented in this dissertation based on the
distribution of the number of clusters on the wafer and the number of defects in a cluster
The negative binomial distribution and the new defect spatial distribution are
respectively used as the defect spatial distribution in the XD-YES simulator when the
given layouts are simu1ated with XD-YES simulator, The simulation results show that
the difference between results obtained by the negative binomial distribution and the
new model is small fOr a small area chip, and that the simulation results consistent well
with testing results, the difference between the results obtained by the negative binomial
distribution and the new tnodel is large fOr a large-area chip, the simulation result using
the new model is more close to the testing results.
A Hopfield network algorithm to solve the allocation of spare rows and columns in
a memory array is presented in this dissertation according to the property of the defect
array fixed by spare elements. A large numbers of validated examples indicate that the
Hopfield network algorithm is very effective to solve the allocation of spare rows and
columns in a memory array.
The Markov chain is used to analyze the yield of the memory array with spare
rows and columns according to the change of the number of spare elements. The effect
of the defect spatial distribution to the yield of the memory array is taken into account during analysis yield. A comparison of the yield method of Markov抯 chain and the traditional yield methods shows that the Markov抯 chain method has higher precision than traditional method by analyzing a number of examples.
As redundancy is added the yield of the memory goes up, but the area of each chip also increases. This in turn reduces the number of chips that can be obtained from a wafer. The influence of chip area variation on yield is synthetically considered in this dissertation when the two-level hierarchical redundancy added into the chips. The rule, which optimally partitions the given multimegabit RAM抯 into modules to make the RAM抯 yield be optimal, is given in this paper.
Finally, an optimal allocation model of the sub-processing-element (sub-PE) level redundancy is developed by genetic algorithm. The average defect density D and the support circuit parameterS are considered in the allocation model to accurately analyze the element yield. Under the condition of the given area constraint, simulation results indicate that the number of the optimal redundant sub-circuit added into a PE and the PE抯 yield decrease for any given average defect density D as S increases; the number of the optimal redundant sub-circuit increases, while the optimal yield of the PE decreases for any given support circuit area parameter S as D increases.
做了系统地理论研究。主要研究结果如下：
根据缺陷在圆片上的位置首先给出了每个缺陷的模糊度，然后利用圆片上的
缺陷与缺陷之间、缺陷与缺陷团之间以及缺陷团与缺陷团之间的相关性定义了缺
陷团与团之间的相关系数，首次提出了适合于划分缺陷团的变步长模糊聚类算法
（CSFCM）。其次对采集到的一批有缺陷的圆片样本利用变步长的模糊聚类算法进
行缺陷团划分处理。最后对划分后的样本进行统计检验，得到了缺陷团在圆片上
服从参数为λ的Poisson分布、团内缺陷数服从参数为α的Reyleigh分布等规律。
根据前面得到的缺陷团在圆片上的分布以及团内缺陷数的分布等规律给出了
缺陷空间分布新模型。在XD—YES模拟器中，分别采用负二项式分布模型和新
模型作为空间分布模型对给定的IC版图进行模拟。模拟结果表明，在芯片面积比
较小时，两个模型模拟结果之间差别很小，并且与实测结果也很接近；当芯片面
积比较大时，两个模型模拟结果之间差别较大，新模型的模拟结果更接近于实测
结果。
本文根据用冗余行和冗余列修复缺陷阵列对应的二分图的特点，提出了一种
Hopfield网络算法，有效地解决了冗余行和冗余列的最小分配问题。通过大量的实
例验证，用该算法求解冗余行和冗余列的最小分配问题是十分有效的。
本文根据修复缺陷阵列时冗余行数和冗余列数的变化情况，利用Markov链精
确地分析了有冗余的存储器阵列的成品率。分析过程中考虑了缺陷的空间分布模
型对存储器芯片成品率的影响。实例分析表明，用Markov链方法分析有冗余的存
储器阵列的成品率比用传统的成品率分析方法精度高。
随着冗余行和冗余列加入到存储器阵列，芯片面积在增加，一个圆片上的有
效芯片数目在减少。本文综合考虑了当两级冗余加入芯片时，芯片面积的变化对
成品率的影响情况。在冗余行（列）数目和冗余模块数目给定的条件下，给出了把给
定容量的多兆位存储器最优地划分成若干模块的准则。对应这种划分可使存储器
芯片的成品率得到最优地改善。
容错技术主要集中在给系统中加入一定量的冗余单元来提高系统的成品
率。然而，由于不同类型的子电路所占的芯片面积不同，当给系统中加入一定量
的冗余单元时并没有使系统的成品率得到最优的改善。本文首次将整体优化的思
想应用于集成电路的容错设计中，利用最优化的思想，提出了在芯片面积增量一
集成电路缺陷分布模型和容错技术研究
定的条件下使系统成品率改善最大的最优化模型。利用遗传算法求解了该优化模
型。
实验结果表明，在芯片面积增量一定的条件f，为使芯片成品率达到最优地
改善，需要加入的冗余子电路数随着芯片上的缺陷密度的增加而增加：随电路中
支撑电路面积的增加而减少，其原因是支撑电路没有容错能力，一旦有缺陷落入
支撑电路，整个电路就会失效。
研究结果表明：本文提出的容错技术对于提高电路的动态和静态成品率和可
靠性是十分有效的。
Abstract
This dissertation airns at discussing the model of defect spatial distribution, IC's
fault-tolerant structures and yield. A large numbers of simulation examples show the
rnodels and the methods presented in this dissertation are very effective by using
XD-YES simulator (XiDian university held EStimator).
The autl1or's main contributions are as fOllowing f
First, the fozzy degree of each defect is defined according to the position of the
detbct o11 tIle wafbr and the correlative coefficient between a detbct cluster and a defect
cluster is defined An effective change-step fuzzy cluster algorithm (CSFCM), which is
suitable to partitioning the defects into clusters, is firstly presented in this dissertation
'1-lle (listributioIl of tl1e 11ull1ber of clusters oIl tlle 1vafer, x\/hicl1 obeys Poisso11's
distribution with;. as a parameter, and the distribution of the number of defects in a
clLlster, 1vIlicI1 obeys Releigll's distributiOIl with a as a paraIl1eter, are obtained by
statistic and testing the data.
The new defect spatial distribution is presented in this dissertation based on the
distribution of the number of clusters on the wafer and the number of defects in a cluster
The negative binomial distribution and the new defect spatial distribution are
respectively used as the defect spatial distribution in the XD-YES simulator when the
given layouts are simu1ated with XD-YES simulator, The simulation results show that
the difference between results obtained by the negative binomial distribution and the
new model is small fOr a small area chip, and that the simulation results consistent well
with testing results, the difference between the results obtained by the negative binomial
distribution and the new tnodel is large fOr a large-area chip, the simulation result using
the new model is more close to the testing results.
A Hopfield network algorithm to solve the allocation of spare rows and columns in
a memory array is presented in this dissertation according to the property of the defect
array fixed by spare elements. A large numbers of validated examples indicate that the
Hopfield network algorithm is very effective to solve the allocation of spare rows and
columns in a memory array.
The Markov chain is used to analyze the yield of the memory array with spare
rows and columns according to the change of the number of spare elements. The effect
of the defect spatial distribution to the yield of the memory array is taken into account during analysis yield. A comparison of the yield method of Markov抯 chain and the traditional yield methods shows that the Markov抯 chain method has higher precision than traditional method by analyzing a number of examples.
As redundancy is added the yield of the memory goes up, but the area of each chip also increases. This in turn reduces the number of chips that can be obtained from a wafer. The influence of chip area variation on yield is synthetically considered in this dissertation when the two-level hierarchical redundancy added into the chips. The rule, which optimally partitions the given multimegabit RAM抯 into modules to make the RAM抯 yield be optimal, is given in this paper.
Finally, an optimal allocation model of the sub-processing-element (sub-PE) level redundancy is developed by genetic algorithm. The average defect density D and the support circuit parameterS are considered in the allocation model to accurately analyze the element yield. Under the condition of the given area constraint, simulation results indicate that the number of the optimal redundant sub-circuit added into a PE and the PE抯 yield decrease for any given average defect density D as S increases; the number of the optimal redundant sub-circuit increases, while the optimal yield of the PE decreases for any given support circuit area parameter S as D increases.
引文
第一章
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