纳米尺度集成电路统计时序分析与成品率优化方法研究
|
摘要
作为有史以来发展最为快速的工业之一,半导体工业的进步依赖于不断缩小的特征尺寸以及由此获得的器件性能的快速提高和芯片集成度的指数增长。然而,随着亚波长光刻和化学机械抛光等复杂纳米工艺的普遍采用,越来越严重的工艺参数偏差造成了集成电路成品率的快速恶化。这主要是由于严重的工艺偏差将造成芯片中的关键路径时延呈现显著的非高斯随机分布,从而造成芯片的时序失败概率快速上升。这些时延的随机分布信息可以通过最先进的统计静态时序分析方法,在芯片生产前精确地获得。但目前还缺乏可以充分利用这些统计信息的电路优化方法和工具,从而造成在芯片设计阶段依然缺乏有效的方法来改善芯片的成品率。成品率问题已成为集成电路工艺向纳米时代迈进中,数字芯片设计的致命性瓶颈问题之一。
本博士论文的工作将针对成品率的分析和优化问题展开研究。研究主要包括以下两个方面。第一,提出了一种基于端口移除和稀疏网格的随机配置算法和一种基于随机配置法的自适应算法,实现对统计静态时序分析(SSTA)方法中关键性的求最大值MAX问题的快速求解,并显著地提高了国际上已有SSTA算法的精度和效率。第二,在国际上首次提出一种可以精确考虑非高斯关键路径时延分布的时钟偏斜规划方法,从而实现在设计阶段对芯片成品率的优化。本文在以上两个方面的工作中提出以下算法:
1.纳米工艺偏差影响下的统计静态时序分析方法。
(1)为求解统计静态时序分析中的关键性的求极大值MAX问题,本文提出一种采用基于稀疏网格的随机配置算法SSCM(Stochastic Sparse-grid CollocationMethod)。与目前国际上MAX求解精度最高的基于降维技术的随机Galerkin方法相比,SSCM解决了其计算精度不稳定的问题。其次,SSCM避免了直接张量积配置方法所导致的配置点个数随随机参数个数的增加而指数增长的问题。与在国际项级会议DAC2005上提出的一种基于矩匹配的算法相比,SSCM有显著的精度提升。结合本文提出的端口移除技术,SSCM的运算时间快于上述的各种作为对照的快速算法,且比10,000次蒙特卡罗算法快最少100倍。
(2)在SSCM算法的基础上,本文提出了一种自适应的MAX快速计算方法ASCM(Adaptive Stochastic Collocation Method)。通过对MAX在不同统计输入下的非线性特性的分析和分类,ASCM选择最合适的算法来求解不同非线性程度的MAX,从而可以在算法效率和精度间做最佳权衡。在ISCAS'85基准组合逻辑电路上进行统计静态时序分析的结果显示,ASCM与国际上已有的基于降维技术的随机Galerkin方法和一种基于矩匹配的MAX逼近算法相比,可以获得最大10倍的精度提升,且运算时间近似相同。
2.纳米工艺偏差影响下,基于时钟偏斜规划的成品率优化方法
(1)在时钟偏斜规划研究领域,本文在国际上首次提出一种可以精确考虑非高斯关键路径时延分布的成品率优化问题的描述方法。基于MIN-MAX形式,本文所提出的成品率优化问题描述涵盖了自上世纪90年代以来,在国际顶级ICCAD和DAC会议上提出的相关领域的大部分已有工作。本文基于所提出的通用描述获得对这些已有方法的统计解释,并从理论上指出它们的局限性。
(2)此外,本文提出基于最小平衡法的一种通用算法来有效求解所提出的成品率优化问题。为了提高算法的效率,本文提出一种基于分段线性插值的反累积分布函数的快速数值计算方法。在ISCAS'89基准时序逻辑电路上的测试表明,本文所提出的方法在成品率优化结果上较已有的两种在国际上具有代表性的方法(由德国波恩大学的C.Albrecht和Jens Vygen教授等在ICCAD1999会议上提出的EVEN法,和由美国威斯康星麦迪逊大学的Charlie Chung-Ping Chen教授和Kewal K.Saluja教授等在ICCAD2004会议上提出的PROP法)有最高33.6%,平均17.7%的显著改善。
The great improvements of the semiconductor industry depend on continuously technology scaling,which provides device with better performance and exponentially increasing integration capability.However,complex nano-technology such as sub-wavelength lithography and chemical-mechanical polishing will cause more and more large process variations and therefore seriously deteriorate the yield.The yield loss is primarily due to non-Gaussian critical path delay distributions arising from process variations.The most advanced statistical static timing analysis(SSTA) methods can now provide accurate predictions about these distributions before manufacture.But it is still hard to make yield optimization during chip design stage since the circuit optimization methods driven by those statistical timing information are not available now.Yield loss problem has become a fateful and critical problem for nanometer chip design.
In order to address the critical yield analysis and optimization problem mentioned above,several works have been done in this dissertation.Firstly a stochastic sparse-grid collocation method with input truncation and an adaptive stochastic collocation method are proposed for solving the critical MAX problem in SSTA.The proposed methods can achieve better efficiency and accuracy compared with the existing methods.Based on the simulation results from SSTA,a novel timing yield driven clock skew scheduling method is proposed,which can address non-Gaussian distributions on critical path delays.The algorithms proposed in the above research work are listed below.
1.Statistical static timing analysis method considering nanometer process variations.
(1).In order to solve the critical MAX problem during SSTA,a Stochastic Sparse-grid Collocation Method(SSCM) is proposed in this paper.Compared with the existing work,the proposed method can provide stabler approximation results than the most accurate algorithm up to now,which is based on the stochastic Galerkin method with dimension reduction technique.Secondly,the proposed SSCM could avoid the exponential increase of the number of collocation points generated by direct tensor product scheme in the high dimensional random space.Combined with the intput truncation technique proposed in this paper,the SSCM requires shortest computing time compared with most of the other methods and 100x faster than 10,000 Monte Carlo method.
(2).Based on SSCM,a novel adaptive algorithm(ASCM) is proposed for MAX approximation.The proposed ASCM adaptively chooses the optimal algorithm from a set of stochastic collocation methods by considering different input conditions of MAX operator and makes a good trade-off between efficiency and accuracy. Experimental results on ISCAS' 85 benchmark circuits have shown that the proposed method has up to 10x improvements in the accuracy while using the same order of computation time compared with the existing methods.
2.Clock skew scheduling for yield optimization considering nanometer process variations.
(1).A general probleme formulation is proposed for timing yield driven clock skew scheduling problem and non-Gaussian critical path delay distributions can be accurately addressed for the first time.With a MIN-MAX style,the proposed formulation covers most of the previous formulations which were proposed in the top-level conferences such as ICCAD and DAC since 1990.Furthermore,the limitations of those existing methods are indicated with statistical interpretations.
(2) A general minimum balancing(GMB) algorithm is proposed for solving the yield optimization problem with the proposed formulation.The efficiency of the algorithm is enhanced by a fast Piece-wise linear interpolation based numerical algorithm for computing the inverse CDF involved in the formulation.Compared with the best results by two representative existing methods,which include the one with the name EVEN was proposed in ICCAD1999 by C.Albrecht and Professor Jens Vygen,et.al. from Born University,and the one with the name PROP proposed in ICCAD2004 by Professor Charlie Chung-Ping Chen,Kewal K.Saluja,et.al.from University of Wisconsin,Madison,the proposed GMB method significantly exceeds in the yield optimization with up to 33.6%and averagely 17.7%improvements,which are tested on benchmark ISCAS' 89 benchmark circuits.
本博士论文的工作将针对成品率的分析和优化问题展开研究。研究主要包括以下两个方面。第一,提出了一种基于端口移除和稀疏网格的随机配置算法和一种基于随机配置法的自适应算法,实现对统计静态时序分析(SSTA)方法中关键性的求最大值MAX问题的快速求解,并显著地提高了国际上已有SSTA算法的精度和效率。第二,在国际上首次提出一种可以精确考虑非高斯关键路径时延分布的时钟偏斜规划方法,从而实现在设计阶段对芯片成品率的优化。本文在以上两个方面的工作中提出以下算法:
1.纳米工艺偏差影响下的统计静态时序分析方法。
(1)为求解统计静态时序分析中的关键性的求极大值MAX问题,本文提出一种采用基于稀疏网格的随机配置算法SSCM(Stochastic Sparse-grid CollocationMethod)。与目前国际上MAX求解精度最高的基于降维技术的随机Galerkin方法相比,SSCM解决了其计算精度不稳定的问题。其次,SSCM避免了直接张量积配置方法所导致的配置点个数随随机参数个数的增加而指数增长的问题。与在国际项级会议DAC2005上提出的一种基于矩匹配的算法相比,SSCM有显著的精度提升。结合本文提出的端口移除技术,SSCM的运算时间快于上述的各种作为对照的快速算法,且比10,000次蒙特卡罗算法快最少100倍。
(2)在SSCM算法的基础上,本文提出了一种自适应的MAX快速计算方法ASCM(Adaptive Stochastic Collocation Method)。通过对MAX在不同统计输入下的非线性特性的分析和分类,ASCM选择最合适的算法来求解不同非线性程度的MAX,从而可以在算法效率和精度间做最佳权衡。在ISCAS'85基准组合逻辑电路上进行统计静态时序分析的结果显示,ASCM与国际上已有的基于降维技术的随机Galerkin方法和一种基于矩匹配的MAX逼近算法相比,可以获得最大10倍的精度提升,且运算时间近似相同。
2.纳米工艺偏差影响下,基于时钟偏斜规划的成品率优化方法
(1)在时钟偏斜规划研究领域,本文在国际上首次提出一种可以精确考虑非高斯关键路径时延分布的成品率优化问题的描述方法。基于MIN-MAX形式,本文所提出的成品率优化问题描述涵盖了自上世纪90年代以来,在国际顶级ICCAD和DAC会议上提出的相关领域的大部分已有工作。本文基于所提出的通用描述获得对这些已有方法的统计解释,并从理论上指出它们的局限性。
(2)此外,本文提出基于最小平衡法的一种通用算法来有效求解所提出的成品率优化问题。为了提高算法的效率,本文提出一种基于分段线性插值的反累积分布函数的快速数值计算方法。在ISCAS'89基准时序逻辑电路上的测试表明,本文所提出的方法在成品率优化结果上较已有的两种在国际上具有代表性的方法(由德国波恩大学的C.Albrecht和Jens Vygen教授等在ICCAD1999会议上提出的EVEN法,和由美国威斯康星麦迪逊大学的Charlie Chung-Ping Chen教授和Kewal K.Saluja教授等在ICCAD2004会议上提出的PROP法)有最高33.6%,平均17.7%的显著改善。
The great improvements of the semiconductor industry depend on continuously technology scaling,which provides device with better performance and exponentially increasing integration capability.However,complex nano-technology such as sub-wavelength lithography and chemical-mechanical polishing will cause more and more large process variations and therefore seriously deteriorate the yield.The yield loss is primarily due to non-Gaussian critical path delay distributions arising from process variations.The most advanced statistical static timing analysis(SSTA) methods can now provide accurate predictions about these distributions before manufacture.But it is still hard to make yield optimization during chip design stage since the circuit optimization methods driven by those statistical timing information are not available now.Yield loss problem has become a fateful and critical problem for nanometer chip design.
In order to address the critical yield analysis and optimization problem mentioned above,several works have been done in this dissertation.Firstly a stochastic sparse-grid collocation method with input truncation and an adaptive stochastic collocation method are proposed for solving the critical MAX problem in SSTA.The proposed methods can achieve better efficiency and accuracy compared with the existing methods.Based on the simulation results from SSTA,a novel timing yield driven clock skew scheduling method is proposed,which can address non-Gaussian distributions on critical path delays.The algorithms proposed in the above research work are listed below.
1.Statistical static timing analysis method considering nanometer process variations.
(1).In order to solve the critical MAX problem during SSTA,a Stochastic Sparse-grid Collocation Method(SSCM) is proposed in this paper.Compared with the existing work,the proposed method can provide stabler approximation results than the most accurate algorithm up to now,which is based on the stochastic Galerkin method with dimension reduction technique.Secondly,the proposed SSCM could avoid the exponential increase of the number of collocation points generated by direct tensor product scheme in the high dimensional random space.Combined with the intput truncation technique proposed in this paper,the SSCM requires shortest computing time compared with most of the other methods and 100x faster than 10,000 Monte Carlo method.
(2).Based on SSCM,a novel adaptive algorithm(ASCM) is proposed for MAX approximation.The proposed ASCM adaptively chooses the optimal algorithm from a set of stochastic collocation methods by considering different input conditions of MAX operator and makes a good trade-off between efficiency and accuracy. Experimental results on ISCAS' 85 benchmark circuits have shown that the proposed method has up to 10x improvements in the accuracy while using the same order of computation time compared with the existing methods.
2.Clock skew scheduling for yield optimization considering nanometer process variations.
(1).A general probleme formulation is proposed for timing yield driven clock skew scheduling problem and non-Gaussian critical path delay distributions can be accurately addressed for the first time.With a MIN-MAX style,the proposed formulation covers most of the previous formulations which were proposed in the top-level conferences such as ICCAD and DAC since 1990.Furthermore,the limitations of those existing methods are indicated with statistical interpretations.
(2) A general minimum balancing(GMB) algorithm is proposed for solving the yield optimization problem with the proposed formulation.The efficiency of the algorithm is enhanced by a fast Piece-wise linear interpolation based numerical algorithm for computing the inverse CDF involved in the formulation.Compared with the best results by two representative existing methods,which include the one with the name EVEN was proposed in ICCAD1999 by C.Albrecht and Professor Jens Vygen,et.al. from Born University,and the one with the name PROP proposed in ICCAD2004 by Professor Charlie Chung-Ping Chen,Kewal K.Saluja,et.al.from University of Wisconsin,Madison,the proposed GMB method significantly exceeds in the yield optimization with up to 33.6%and averagely 17.7%improvements,which are tested on benchmark ISCAS' 89 benchmark circuits.
引文
[1]International Technology Roadmap for Semiconductors 2007 Edition[R].ITRS,2007.
[2]Paul B C,Kang K,Kufluoglu H,et al.Impact of NBTI on the temporal performance degradation of digital circuits[J].IEEE Electron Device Letters.2003,26:560-562.
[3]Bhardwaj S,Wang W,Vattikonda R,et al.Predictive modeling of NBTI effect for reliable design[C].In:IEEE Custom Integrated Circuits Conference.2006.
[4]B S D.Rapid characterization and modeling of pattern dependent variation in chemical mechanical polishing[J].IEEE Transaction:Semiconductor Manufacturing.1998,11(1).
[5]Xiong J,Zolotov V,He L.Robust extraction of spatial correlation[J].IEEE Transaction on Computer-Aided Design of Integration Circuits and System.2007,26(4):619-631.
[6]Chang H,Zolotov V,Narayan S,et al.Parameterized block-based statistical timing analysis with non-gaussian parameters,nonlinear delay functions[C].In:Proceedings of IEEE/ACM International Conference on Design Automation Conference.2005.71-76.
[7]Zhan Y,Strojwas A J,Li X,et al.Correlation-aware statistical timing analysis with non-gaussian delay distribution[C].In:Proceedings of IEEE/ACM International Conference on Design Automation Conference.2005.77-82.
[8]Zhang L,Chen W,Hu Y,et al.Correlation-preserved non-Gaussian statistical timing analysis with quadratic timing model[C].In:Proceedings of IEEE/ACM International Conference on Design Automation Conference.2005.83-88.
[9]Khandelwal V,Srivastava A.A general framework for accurate statistical timing analysis considering correlations[C].In:Proceedings of IEEE/ACM International Conference on Design Automation Conference.2005.89-94.
[10]陶俊.纳米尺度集成电路建模与分析方法研究[D].博士,复旦大学,2007.
[11]Koenemann B.Test in the era of "What You see Is NOT What You Get"[C].In:IEEE International Test Conference.2004.
[12]Borker S,Al.Parameter variations and impact on circuits and microarchitecture[C].In:IEEE/ACM Design Automation Conference.2003. 338-342.
[13] Nassif S. Modeling and analysis of manufacturing variations[C]. In: IEEE CICC.2001. 223-228.
[14] Sachin S. Timing[M]. Boston: Kluwer Academic Publishers, 2004.
[15] Visweswariah C, Ravindran K, Kalafala K, et al. First order incremental block based statistical timing analysis[C]. In: Proceedings of IEEE/ACM International Conference on Design Automation Conference.2004. 331-336.
[16] Singh J, Sapatnekar S. Statistical timing analysis with correlated non-Gaussian parameters using independent component analysis[C]. In: Proceedings of IEEE/ACM International Conference on Design Automation Conference.2006. 155-160.
[17] Visweswariah C. Statistical techniques to achieve robustness and quality[C]. In: 9th International Symposium on Quality Electronic Design.San Jose, CA USA: 2008.
[18] Kourtev I S, Friedman E G. Timing optimization through clock skew scheduling[M]. Kluwer Academic Publishers, 2000.
[19] Coudert O. Gate sizing for constrained delay/power/area optimization[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 1997, VLSI-5: 465-472.
[20] Xiong J, Zolotov V, Venkateswaran N, et al. Criticality computation in parameterized statistical timing[C]. In: Proceedings of IEEE/ACM International Conference on Design Automation Conference.San Francisco: 2006. 53-68.
[21] He L, Kahng A B, Tam K H, et al. Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random Leff variation[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2007, 26: 845-857.
[22] Jacobs E T A F, Berkelaar M R C M. Gate sizing using a statistical delay model[C]. In: Proceedings of the Design, Automation and Test in Europe Conference and Exhibition.2000.
[23] Xiu D, Karniadakis G E. The wiener-asky polynomial chaos for stochastic differential equations[J]. 2005, 27:1118-1139.
[24] Ghanem R G, Spanos P. Stochastic finite elements: A Spectral Approach[M]. Springer-Verlag, 1991.
[25] Bhardaj S, Ghanta P, Vrudhula S. A framework for statistical timing analysis using non-linear delay and slew models[C]. In: Proceedings of the IEEE/ACM International Conference on Computer-aided Design.2006. 225-230.
[26] Zhang L, Shao J, Chen C C. Non-gaussian statistical parameter modeling for SSTA with confidence interval analysis[C]. In: Proceedings of International Symposium on Quality Electronic Design.2006. 33-38.
[27] Deokar R B, Sapatnekar S S. A graph-theoretic approach to clock skew optimization[C]. In: Proceedings of IEEE International Symposium on Circuits and Systems.London: 1994. 407--410.
[28] Fishbum J P. Clock skew optimization[J]. IEEE Transactions on Computers. 1990,39:945-951.
[29] Kourtev I S, Friedman E G. Clock skew scheduling for improved reliability via quadratic programming[C]. In: Proceedings of the IEEE/ACM International Conference on Computer-aided Design. 1999. 239-243.
[30] Neves J L, Friedman E G. Optimal clock skew scheduling tolerant to process variations[C]. In: Proceedings of IEEE/ACM International Conference on Design Automation Conference. 1996. 623-628.
[31] Albrecht C, Korte B, Schietke J, et al. Cycle time and slack optimization for VLSI-chips[C]. In: Proceedings of the IEEE/ACM International Conference on Computer-aided Design. 1999. 232-238.
[32] Wei X, Cai Y, Hong X. Clock skew scheduling under process variations[C]. In: Proceedings of International Symposium on Quality Electronic Design.2006.
[33] Young N E, Tarjan R E, Orlin J B. Faster parametric shortest path and minimum-balance algorithms[J]. Networks. 1991, 21: 205-221.
[34] Tsai J, Baik D, Chen C C, et al. A yield improvement methodology using pre-and post-silicon statistical clock scheduling[C]. In: Proceedings of the IEEE/ACM International Conference on Computer-aided Design.2004. 611-618.
[35] Tsai J, Baik D H, Chen C C, et al. Yield-driven, false-path-aware clock skew scheduling[J]. 2005, 22: 214-222.
[36] Wang Y, Zeng X, Tao J, et al. Adaptive stochastic collocation method (ASCM) for parameterized statistical timing analysis with quadratic delay model[C]. In: 9th International Symposium on Quality Electronic Design.San Jose, CA, U.S.A.: IEEE, 2008.
[37] Chiang C C, Kawa J. Design for manufacturability and yield for nano-scale CMOS[M]. Springer, 2007.
[38] Lin C, Tsai M, Lee K, et al. Recent research and emerging challenges in physical design for manufacturability/reliablity[C]. In: IEEE Asia and South Pacific Design Automation Conference.2007.
[39] Chang K J. Accurate on-chip variation modeling to achieve design for manufacturability[C]. In: IEEE. International Workshop on System-on-Chip for Real-Time Applications.2004.
[40] Mehrotra V. Modeling the efects of systematic process variation on circuit performance[D]. Ph.D., Massachusetts Institute of Technulogy, 2001.
[41] Mutlu A. Statistical analysis and optimization of process variation effects on circuit operation[D]. Ph.D., Santa Clara university, 2004.
[42] Karnik T, Borkar S, De V. Sub-90nm technologies—challenges and opportunities for CAD[C]. In: Proceedings of the IEEE/ACM International Conference on Computer-aided Design.2002. 203-206.
[43] Cheng Y, Kang S M. A temperature-aware simulation environment for reliable ULSI chip design[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2000, 19: 1211-1220.
[44] Chen G, Sapatnekar S S. Partition-driven standard cell thermal placement[C]. In: ACM International Symposium on Physical Design.2003.
[45] Sapatnekar S S, Su H. Analysis and optimization of power grids[J]. IEEE Design and Test. 2002,20:7-15.
[46] Gbondo-tugbawa T E. Chip-scale modeling of pattern dependencies in copper chemical mechanical polishing processes[D], Ph.D, MIT, 2002.
[47] Jilla S. Using multi-corner multi-mode techniques to meet the P&R challenges at 65 nm and below[Z]. EDA Tech Forum, 2007.
[48] Chung D S B A J E. Statistical metrology: understanding spatial variation in semiconductor manufacturing[C]. In: Microelectronic Manufacturing Yield, Reliability, and Failure Analysis II: SPIE 1996 Symp. on Microelectronic Manufacturing. 1996. 16-26.
[49] Stine B E, Boning D S, Chung J E. Analysis and decomposition of spatial variation in integrated circuit processes and devices[J]. 10. 1997(1): 24-41.
[50] Verghese N, Hurat P. DFM reality in sub-nanometer IC design[C]. In: IEEE Asia and South Pacific Design Automation Conference.2007. 226-231.
[51] Luo J, Sinha S, Su Q, et al. An IC manufacturing yield model considering intra-die variations[C]. In: ACM/IEEE 43rd Design Automation Conference.San Francisco, USA: 2006. 749-754.
[52] Li X, pileggi L T. Asymptotic probability extraction for non-Normal distributions of circuit performance[C]. In: IEEE/ACM International Conference on Computer Aided Design.2004. 2-9.
[53] Orshansky M, Bandyopadhyay A. Fast statistical timing analysis handling arbitrary delay correlations[C]. In: IEEE/ACM International Conference on Design Automation Conference.2003.
[54] Morrison D F. Multivariate statistical methods[M]. New York: McGraw-Hill, 1976.
[55] Chang H, Sapatnekar S S. Statistical timing analysis considering spatialcorrelations using a single PERT-like traversal[C]. In: IEEE/ACM International Conference on Computer-aided Design.2003. 621-625.
[56] Papoulis A,Pillai S U．概率、随机变量与随机过程(第四版)[M]．西安交通大学出版社,2004．
[57] Press W H, Teukolsky S A, Vetterling W T, et al. Numerical recipes in C: The art of scientific computing, second edition[M]. Cambridge University Press, 1997.
[58] Ju Y, Saleh R A. Incremental techniques for the identification of statically sensitizable critical paths[C]. In: ACM/IEEE Design Automation Conferenc.1991. 541-546.
[59] Liou J, Krstic A, Wang L, et al. False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation[C]. In: Proceedings of IEEE/ACM International Conference on Design Automation Conference.2002.
[60] Amin C S, Menezes N, Killpack K, et al. Statistical static timing analysis: How Simple Can We Get[C]. In: IEEE/ACM International Conference on Design Automation Conference.2005.
[61] Wang J M, Ghanta P, Vrudhula S. Stochastic analysis of interconnect performance in the presence of process variations[C]. In: International Conference on Computer Aided Design.2004. 880-886.
[62] Ghanta P, Vrudhula S, Panda R, et al. Stochastic power grid analysis considering process variations[C]. In: Design, Automation and Test in Europe.2005. 964-969.
[63] Y S K, Li J, Talarico C, et al. A probabilistic collocation method based statistical gate delay model considering process variations and multiple input switching[C]. In:Proceedings of the Design, Automation and Test in Europe Conference and Exhibition.2005.
[64] Xiu D, Karniadakis G E. The wiener-askey polynomial chaos for stochastic differential equations[J]. SIAM Journal of Science and computaion. 2002, 24: 619-644.
[65] Rahrer L P A R. Asymptotic waveform evaluation for timing analysis[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 1990, 9: 352-366.
[66] Clark C E. The greates of a finite set of random variables[J]. Operations Research. 1961: 145-162.
[67] Golub G H, Welsch J H. Calculation of gauss quadrature rules[J]. Mathematics of Computation. 1969, 23: 220-230.
[68] Smolyak S. Quadrature and interpolation formulas for tensor products of certain classes of functions [J]. Soviet Math. Dokl. 1963, 4: 240-243.
[69] Zhu H, Zeng X, Cai W, et al. A sparse grid based spectral stochastic collocation method for variations-aware capacitance extraction of interconnects under nanometer process technology[C]. In: Proceedings of the Design, Automation and Test in Europe Conference and Exhibition.2007. 1-6.
[70] Novak E, Ritter K. Simple cubature formulas with high polynomial exactness [J]. Constructuve Approximation[J]. Constructuve Approximation. 1999, 15: 449-522.
[71] Mead C, Conway L. Introduction to VLSI Systems[M]. Addison-Wesley Publishing Company, 1982.
[72] Weste N H E, Eshraghian K. Principles of CMOS design: A Systems Perspective[M]. Addison-Wesley Publishing Company, 1988.
[73] Kohavi Z. Switching and finite automata theory, 2nd ed.[M]. New York:McGraw-Hill Book Company, 1978.
[74] Uyemura J P. Circuit design for CMOS VLSI[M]. Kluwer Academic Publishers, 1992.
[75] Blair G M. Low-Power Double-Edge Triggered Flip-Flop[J]. Electronics Letters. 1997,33:845-847.
[76] Lu S -. A Novel CMOS Implementation of Double-Edge-Triggered D-Flip-Flops[J]. IEEE Journal of Solid State Circuits. 1990, SC-25: 1008-1010.
[77] Afghani M, Yuan J. Double-Edge-Triggered D-Flip-Flops for high-speed CMOS circuits[J]. IEEE Journal of Solid State Circuits. 1991, SC-26: 1168-1170.
[78] Friedman E G. Clock distribution networks in VLSI circuits and systems[M]. IEEE Press, 1995.
[79] Cormen T H, Leiserson C E, Riverst R L, et al. Introduction to algorithms[M]. Second ed. Cambridge, Massachusetts: MIT Press and McGraw-Hill, 2001.
[80] Heloue K R. Statistical timing analysis under process variations[D]. M.A. Sc., University of Toronto (Canada), 2006.
[81] Spanos C J. Special Issues in Semiconductor Manufacturing[Z]. 2005.
[82] Shoji M. Elimination of process-dependent clock skew in CMOS VLSI[J]. IEEE Journal of Solid-State Circuits. 1986: 875-880.
[83] Tsay R. Exact zero skew, [R]. Technical Report RC 16683, IBM Yorktown Research Center, 1991.
[84] Huang S, Cheng C, Chang C, et al. Clock period minimization with minimum delay insertion[C]. In: Proceedings of IEEE/ACM International Conference on Design Automation Conference.2007. 970-975.
[85] Huang S, Nieh Y, Lu F. Race-condition-aware clock skew scheduling[C]. In: Proceedings of IEEE/ACM International Conference on Design Automation Conference.2005. 475-478.
[86] Fishbum J P. Clock skew optimization[J]. IEEE Transactions on Computers. 1990,39:945-951.
[87] Dasdan A, Gupta R K. Faster maximum and minimum mean cycle algorithms for system performance analysis[J]. IEEE Transactions on Computer-aided Design. 1997.
[88] Jun F, Wai-shing L, Wenqing Z. True worst-case clock skew estimation under process variations using affine arithmetic [J]. 2007, 16: 631-636.
[89] Dasdan A, Irani S S, Gupta R K. Efficient algorithms for optimum cycle mean and optimum cost to time ratio problems[C]. In: IEEE/ACM International Conference on Design Automation Conference. 1999.
[90] Hartmann M, Orlin J B. Finding minimum cost to time ratio cycles with small integral transit times[J]. Networks. 1993, 23: 567-574.
[91] Karp R M. A characterization of the minimum cycle mean in a digraph[J]. Discrete Math. 1978, 23: 309-311.
[92] Mehlhorn K, Naher S. The leda platform for combinatorial and geometric computing[M]. UK: Cambridge University Press, 1999.
[2]Paul B C,Kang K,Kufluoglu H,et al.Impact of NBTI on the temporal performance degradation of digital circuits[J].IEEE Electron Device Letters.2003,26:560-562.
[3]Bhardwaj S,Wang W,Vattikonda R,et al.Predictive modeling of NBTI effect for reliable design[C].In:IEEE Custom Integrated Circuits Conference.2006.
[4]B S D.Rapid characterization and modeling of pattern dependent variation in chemical mechanical polishing[J].IEEE Transaction:Semiconductor Manufacturing.1998,11(1).
[5]Xiong J,Zolotov V,He L.Robust extraction of spatial correlation[J].IEEE Transaction on Computer-Aided Design of Integration Circuits and System.2007,26(4):619-631.
[6]Chang H,Zolotov V,Narayan S,et al.Parameterized block-based statistical timing analysis with non-gaussian parameters,nonlinear delay functions[C].In:Proceedings of IEEE/ACM International Conference on Design Automation Conference.2005.71-76.
[7]Zhan Y,Strojwas A J,Li X,et al.Correlation-aware statistical timing analysis with non-gaussian delay distribution[C].In:Proceedings of IEEE/ACM International Conference on Design Automation Conference.2005.77-82.
[8]Zhang L,Chen W,Hu Y,et al.Correlation-preserved non-Gaussian statistical timing analysis with quadratic timing model[C].In:Proceedings of IEEE/ACM International Conference on Design Automation Conference.2005.83-88.
[9]Khandelwal V,Srivastava A.A general framework for accurate statistical timing analysis considering correlations[C].In:Proceedings of IEEE/ACM International Conference on Design Automation Conference.2005.89-94.
[10]陶俊.纳米尺度集成电路建模与分析方法研究[D].博士,复旦大学,2007.
[11]Koenemann B.Test in the era of "What You see Is NOT What You Get"[C].In:IEEE International Test Conference.2004.
[12]Borker S,Al.Parameter variations and impact on circuits and microarchitecture[C].In:IEEE/ACM Design Automation Conference.2003. 338-342.
[13] Nassif S. Modeling and analysis of manufacturing variations[C]. In: IEEE CICC.2001. 223-228.
[14] Sachin S. Timing[M]. Boston: Kluwer Academic Publishers, 2004.
[15] Visweswariah C, Ravindran K, Kalafala K, et al. First order incremental block based statistical timing analysis[C]. In: Proceedings of IEEE/ACM International Conference on Design Automation Conference.2004. 331-336.
[16] Singh J, Sapatnekar S. Statistical timing analysis with correlated non-Gaussian parameters using independent component analysis[C]. In: Proceedings of IEEE/ACM International Conference on Design Automation Conference.2006. 155-160.
[17] Visweswariah C. Statistical techniques to achieve robustness and quality[C]. In: 9th International Symposium on Quality Electronic Design.San Jose, CA USA: 2008.
[18] Kourtev I S, Friedman E G. Timing optimization through clock skew scheduling[M]. Kluwer Academic Publishers, 2000.
[19] Coudert O. Gate sizing for constrained delay/power/area optimization[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 1997, VLSI-5: 465-472.
[20] Xiong J, Zolotov V, Venkateswaran N, et al. Criticality computation in parameterized statistical timing[C]. In: Proceedings of IEEE/ACM International Conference on Design Automation Conference.San Francisco: 2006. 53-68.
[21] He L, Kahng A B, Tam K H, et al. Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random Leff variation[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2007, 26: 845-857.
[22] Jacobs E T A F, Berkelaar M R C M. Gate sizing using a statistical delay model[C]. In: Proceedings of the Design, Automation and Test in Europe Conference and Exhibition.2000.
[23] Xiu D, Karniadakis G E. The wiener-asky polynomial chaos for stochastic differential equations[J]. 2005, 27:1118-1139.
[24] Ghanem R G, Spanos P. Stochastic finite elements: A Spectral Approach[M]. Springer-Verlag, 1991.
[25] Bhardaj S, Ghanta P, Vrudhula S. A framework for statistical timing analysis using non-linear delay and slew models[C]. In: Proceedings of the IEEE/ACM International Conference on Computer-aided Design.2006. 225-230.
[26] Zhang L, Shao J, Chen C C. Non-gaussian statistical parameter modeling for SSTA with confidence interval analysis[C]. In: Proceedings of International Symposium on Quality Electronic Design.2006. 33-38.
[27] Deokar R B, Sapatnekar S S. A graph-theoretic approach to clock skew optimization[C]. In: Proceedings of IEEE International Symposium on Circuits and Systems.London: 1994. 407--410.
[28] Fishbum J P. Clock skew optimization[J]. IEEE Transactions on Computers. 1990,39:945-951.
[29] Kourtev I S, Friedman E G. Clock skew scheduling for improved reliability via quadratic programming[C]. In: Proceedings of the IEEE/ACM International Conference on Computer-aided Design. 1999. 239-243.
[30] Neves J L, Friedman E G. Optimal clock skew scheduling tolerant to process variations[C]. In: Proceedings of IEEE/ACM International Conference on Design Automation Conference. 1996. 623-628.
[31] Albrecht C, Korte B, Schietke J, et al. Cycle time and slack optimization for VLSI-chips[C]. In: Proceedings of the IEEE/ACM International Conference on Computer-aided Design. 1999. 232-238.
[32] Wei X, Cai Y, Hong X. Clock skew scheduling under process variations[C]. In: Proceedings of International Symposium on Quality Electronic Design.2006.
[33] Young N E, Tarjan R E, Orlin J B. Faster parametric shortest path and minimum-balance algorithms[J]. Networks. 1991, 21: 205-221.
[34] Tsai J, Baik D, Chen C C, et al. A yield improvement methodology using pre-and post-silicon statistical clock scheduling[C]. In: Proceedings of the IEEE/ACM International Conference on Computer-aided Design.2004. 611-618.
[35] Tsai J, Baik D H, Chen C C, et al. Yield-driven, false-path-aware clock skew scheduling[J]. 2005, 22: 214-222.
[36] Wang Y, Zeng X, Tao J, et al. Adaptive stochastic collocation method (ASCM) for parameterized statistical timing analysis with quadratic delay model[C]. In: 9th International Symposium on Quality Electronic Design.San Jose, CA, U.S.A.: IEEE, 2008.
[37] Chiang C C, Kawa J. Design for manufacturability and yield for nano-scale CMOS[M]. Springer, 2007.
[38] Lin C, Tsai M, Lee K, et al. Recent research and emerging challenges in physical design for manufacturability/reliablity[C]. In: IEEE Asia and South Pacific Design Automation Conference.2007.
[39] Chang K J. Accurate on-chip variation modeling to achieve design for manufacturability[C]. In: IEEE. International Workshop on System-on-Chip for Real-Time Applications.2004.
[40] Mehrotra V. Modeling the efects of systematic process variation on circuit performance[D]. Ph.D., Massachusetts Institute of Technulogy, 2001.
[41] Mutlu A. Statistical analysis and optimization of process variation effects on circuit operation[D]. Ph.D., Santa Clara university, 2004.
[42] Karnik T, Borkar S, De V. Sub-90nm technologies—challenges and opportunities for CAD[C]. In: Proceedings of the IEEE/ACM International Conference on Computer-aided Design.2002. 203-206.
[43] Cheng Y, Kang S M. A temperature-aware simulation environment for reliable ULSI chip design[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2000, 19: 1211-1220.
[44] Chen G, Sapatnekar S S. Partition-driven standard cell thermal placement[C]. In: ACM International Symposium on Physical Design.2003.
[45] Sapatnekar S S, Su H. Analysis and optimization of power grids[J]. IEEE Design and Test. 2002,20:7-15.
[46] Gbondo-tugbawa T E. Chip-scale modeling of pattern dependencies in copper chemical mechanical polishing processes[D], Ph.D, MIT, 2002.
[47] Jilla S. Using multi-corner multi-mode techniques to meet the P&R challenges at 65 nm and below[Z]. EDA Tech Forum, 2007.
[48] Chung D S B A J E. Statistical metrology: understanding spatial variation in semiconductor manufacturing[C]. In: Microelectronic Manufacturing Yield, Reliability, and Failure Analysis II: SPIE 1996 Symp. on Microelectronic Manufacturing. 1996. 16-26.
[49] Stine B E, Boning D S, Chung J E. Analysis and decomposition of spatial variation in integrated circuit processes and devices[J]. 10. 1997(1): 24-41.
[50] Verghese N, Hurat P. DFM reality in sub-nanometer IC design[C]. In: IEEE Asia and South Pacific Design Automation Conference.2007. 226-231.
[51] Luo J, Sinha S, Su Q, et al. An IC manufacturing yield model considering intra-die variations[C]. In: ACM/IEEE 43rd Design Automation Conference.San Francisco, USA: 2006. 749-754.
[52] Li X, pileggi L T. Asymptotic probability extraction for non-Normal distributions of circuit performance[C]. In: IEEE/ACM International Conference on Computer Aided Design.2004. 2-9.
[53] Orshansky M, Bandyopadhyay A. Fast statistical timing analysis handling arbitrary delay correlations[C]. In: IEEE/ACM International Conference on Design Automation Conference.2003.
[54] Morrison D F. Multivariate statistical methods[M]. New York: McGraw-Hill, 1976.
[55] Chang H, Sapatnekar S S. Statistical timing analysis considering spatialcorrelations using a single PERT-like traversal[C]. In: IEEE/ACM International Conference on Computer-aided Design.2003. 621-625.
[56] Papoulis A,Pillai S U．概率、随机变量与随机过程(第四版)[M]．西安交通大学出版社,2004．
[57] Press W H, Teukolsky S A, Vetterling W T, et al. Numerical recipes in C: The art of scientific computing, second edition[M]. Cambridge University Press, 1997.
[58] Ju Y, Saleh R A. Incremental techniques for the identification of statically sensitizable critical paths[C]. In: ACM/IEEE Design Automation Conferenc.1991. 541-546.
[59] Liou J, Krstic A, Wang L, et al. False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation[C]. In: Proceedings of IEEE/ACM International Conference on Design Automation Conference.2002.
[60] Amin C S, Menezes N, Killpack K, et al. Statistical static timing analysis: How Simple Can We Get[C]. In: IEEE/ACM International Conference on Design Automation Conference.2005.
[61] Wang J M, Ghanta P, Vrudhula S. Stochastic analysis of interconnect performance in the presence of process variations[C]. In: International Conference on Computer Aided Design.2004. 880-886.
[62] Ghanta P, Vrudhula S, Panda R, et al. Stochastic power grid analysis considering process variations[C]. In: Design, Automation and Test in Europe.2005. 964-969.
[63] Y S K, Li J, Talarico C, et al. A probabilistic collocation method based statistical gate delay model considering process variations and multiple input switching[C]. In:Proceedings of the Design, Automation and Test in Europe Conference and Exhibition.2005.
[64] Xiu D, Karniadakis G E. The wiener-askey polynomial chaos for stochastic differential equations[J]. SIAM Journal of Science and computaion. 2002, 24: 619-644.
[65] Rahrer L P A R. Asymptotic waveform evaluation for timing analysis[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 1990, 9: 352-366.
[66] Clark C E. The greates of a finite set of random variables[J]. Operations Research. 1961: 145-162.
[67] Golub G H, Welsch J H. Calculation of gauss quadrature rules[J]. Mathematics of Computation. 1969, 23: 220-230.
[68] Smolyak S. Quadrature and interpolation formulas for tensor products of certain classes of functions [J]. Soviet Math. Dokl. 1963, 4: 240-243.
[69] Zhu H, Zeng X, Cai W, et al. A sparse grid based spectral stochastic collocation method for variations-aware capacitance extraction of interconnects under nanometer process technology[C]. In: Proceedings of the Design, Automation and Test in Europe Conference and Exhibition.2007. 1-6.
[70] Novak E, Ritter K. Simple cubature formulas with high polynomial exactness [J]. Constructuve Approximation[J]. Constructuve Approximation. 1999, 15: 449-522.
[71] Mead C, Conway L. Introduction to VLSI Systems[M]. Addison-Wesley Publishing Company, 1982.
[72] Weste N H E, Eshraghian K. Principles of CMOS design: A Systems Perspective[M]. Addison-Wesley Publishing Company, 1988.
[73] Kohavi Z. Switching and finite automata theory, 2nd ed.[M]. New York:McGraw-Hill Book Company, 1978.
[74] Uyemura J P. Circuit design for CMOS VLSI[M]. Kluwer Academic Publishers, 1992.
[75] Blair G M. Low-Power Double-Edge Triggered Flip-Flop[J]. Electronics Letters. 1997,33:845-847.
[76] Lu S -. A Novel CMOS Implementation of Double-Edge-Triggered D-Flip-Flops[J]. IEEE Journal of Solid State Circuits. 1990, SC-25: 1008-1010.
[77] Afghani M, Yuan J. Double-Edge-Triggered D-Flip-Flops for high-speed CMOS circuits[J]. IEEE Journal of Solid State Circuits. 1991, SC-26: 1168-1170.
[78] Friedman E G. Clock distribution networks in VLSI circuits and systems[M]. IEEE Press, 1995.
[79] Cormen T H, Leiserson C E, Riverst R L, et al. Introduction to algorithms[M]. Second ed. Cambridge, Massachusetts: MIT Press and McGraw-Hill, 2001.
[80] Heloue K R. Statistical timing analysis under process variations[D]. M.A. Sc., University of Toronto (Canada), 2006.
[81] Spanos C J. Special Issues in Semiconductor Manufacturing[Z]. 2005.
[82] Shoji M. Elimination of process-dependent clock skew in CMOS VLSI[J]. IEEE Journal of Solid-State Circuits. 1986: 875-880.
[83] Tsay R. Exact zero skew, [R]. Technical Report RC 16683, IBM Yorktown Research Center, 1991.
[84] Huang S, Cheng C, Chang C, et al. Clock period minimization with minimum delay insertion[C]. In: Proceedings of IEEE/ACM International Conference on Design Automation Conference.2007. 970-975.
[85] Huang S, Nieh Y, Lu F. Race-condition-aware clock skew scheduling[C]. In: Proceedings of IEEE/ACM International Conference on Design Automation Conference.2005. 475-478.
[86] Fishbum J P. Clock skew optimization[J]. IEEE Transactions on Computers. 1990,39:945-951.
[87] Dasdan A, Gupta R K. Faster maximum and minimum mean cycle algorithms for system performance analysis[J]. IEEE Transactions on Computer-aided Design. 1997.
[88] Jun F, Wai-shing L, Wenqing Z. True worst-case clock skew estimation under process variations using affine arithmetic [J]. 2007, 16: 631-636.
[89] Dasdan A, Irani S S, Gupta R K. Efficient algorithms for optimum cycle mean and optimum cost to time ratio problems[C]. In: IEEE/ACM International Conference on Design Automation Conference. 1999.
[90] Hartmann M, Orlin J B. Finding minimum cost to time ratio cycles with small integral transit times[J]. Networks. 1993, 23: 567-574.
[91] Karp R M. A characterization of the minimum cycle mean in a digraph[J]. Discrete Math. 1978, 23: 309-311.
[92] Mehlhorn K, Naher S. The leda platform for combinatorial and geometric computing[M]. UK: Cambridge University Press, 1999.