集成电路功能成品率仿真与优化技术研究
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摘要
本文对集成电路功能成品率模型、仿真技术以及功能成品率优化设计方法进
行了系统研究。主要研究结果如下：
首先，研究了工艺缺陷引起电路故障的机理，在冗余物缺陷和丢失物缺陷的
研究基础上，考虑了介质层针孔缺陷对功能成品率的影响，得到了针孔缺陷的故
障识别算法（应用于Monte Carlo成品率仿真）和关键面积提取算法。
本文对不同种类的缺陷分别提出了相应的故障识别算法。故障识别算法是功
能成品率仿真的核心技术。由于实际集成电路的复杂性，缺陷能否引起电路故障
与其出现位置以及版图图形有密切关系。在局部识别导体冗余物缺陷能否引起短
路故障时，考虑了实际版图图元的连接关系，消除了冗余物短路同一电连接网络
图元的误判断。分别对导体冗余物引起短路、丢失物引起开路、介质层针孔缺陷
引起纵向短路等故障情形提出了判别准则，并提出了有效的实现算法。
成功的开发了Monte Carlo功能成品率仿真系统。该系统综合了本文在制造
缺陷模型、负二项分布随机数发生、CIF版图解码、缺陷故障识别以及MC成品
率仿真策略等方面的研究结果，用超过8000行C++语言编程实现了图形界面交
互式功能成品率仿真。能够在多种缺陷模式下同时对IC多个故障敏感层进行
MC成品率分析并报告成品率。通过对金属微电子测试阵列和终端接口芯片XT-1
的成品率仿真实例，对仿真系统进行了检验。这是迄今为止的第一个集成电路功
能成品率仿真与设计系统。
本文在研究了现有关键面积计算模型及其不足之处后，首次提出了适用于一
般版图图形结构的关键面积计算模型，在实际算法设计中，通过同一版图层图元
连接关系的提取而避免了导体冗余物短路关键面积提取的错误情形，采用版图图
元分组排序算法而提高了短路关键面积提取计算效率。针对丢失物和针孔关键面
积也提出了相应的实现算法。并利用关键面积的概念，论述了Monte Carlo方法
和关键面积方法在芯片故障敏感度分析中的统一性。
本文在功能成品率优化设计方法研究上取得重要结果。论述了基本优化策
略，重点研究了基于局部版图布线调整的功能成品率优化方法。版图优化区域以
故障敏感度为根据进行分块优选。在分块优选中，采用Monte Carlo方法进行分
块版图敏感度分析，避免了关键面积方法在局部应用上的缺点，解决了局部版图
优化的分块优选问题。在局部版图优化调整方法上，提出了金属互连线层成品率
优化的局部线宽优化算法，并对线宽优化的特性进行了实例分析，说明了线宽优
集成电路功能成品率仿真与优化技术研究
化算法的有效性和适用情形。本文还研究了基于线型调整和连线位置调整的局部
版图优化技术，通过实际版图结构的关键面积特性对比说明了这两种技术的有效
性。此外，还对全局版图调整的功能成品率优化进行了研究与探讨，分析了版图
设计规则变化对功能成品率的影响。
研究结果表明，本文提出的功能成品率仿真与优化设计方法对成品率预报和
提高是十分有效的。
This dissertation aims at discussing the model, simulation and optimization
methods of functional yield of integrated circuits. The Author抯 main contributions are
as following:
First, the principle of circuit faults caused by manufacturing defects is studied.
Some manufacturing defects that have the most significant influence upon functional
yield, such as extra material defects, missing material defects and dielectric pinhole
defects, are discussed to obtain the corresponding geometrical abstractions. Then a
fault recognition algorithm and the critical area extraction method of dielectric
pinhole defects are presented.
Second, fault recognition is one of the kernel techniques of a functional yield
simulation system. In this dissertation, corresponding fault recognition algorithms are
proposed according to different defect types. Due to the complexity of layout, whether
a defect causes circuit faults or not is determined by the size, position of the defect
and the surrounding layout geometry. So the actual geometry net of local layout must
be extracted to avoid such a misrecognition case as an extra material defect touches
two or more neighboring conductors within a same electrical net. As a result, effective
rules to recognize defect-induced faults are presented to recognize primary fault
patterns, such as circuit short faults caused by extra material defects, line open faults
caused by missing material defects and circuit short faults between neighboring layers
caused by dielectric pinhole defects.
After combining research results of defects model, negative binomial random
number generation, CIF layout decoding, fault-recognition and Monte Carlo
functional yield simulation methodology, a functional yield simulation system is
developed. With its graphics user interface and interactive operations, the simulation
system can be applied to obtain the functional yield of an integrated circuiU by
analyzing its many defect modes and defect sensitive layers. With the simulation
results of a metal test structure layout and a terminal interface chip XT- 1, the
simulation system is checked.
Then, the available critical area extraction model and its disadvantages are
studied and an improved critical area extraction model is presented in this dissertation.
The improved model performs a good accuracy in critical area extraction for general
layout geomeity. Especially, geometry net of local layout is taken into account to
derive the efficient critical area extraction algorithms of extra material defects. A
grouping-sorting technique is also developed to improve the computation efficiency
of short critical area extraction. Therefore, different critical area extraction algorithms
ar~ developed according to diffem~f defect tvnes~ With the concept of critical area, the
unitarity of Monte Carlo method and critical area method is discussed in
fault-sensitivity analysis.
Finally, optimization design techniques for functional yield enhancement are
studied in this dissertation. By comparison of yield optimization methodologies, the
geometry adjustment method of local layout is proved suitable to improve functional
yield without increasing chip area. Based on the criterion of sub-block
fault-sensitivities of layout, the optimization selection problem of layout sub-blocks is
solved. Applying the Monte Carlo fault-sensitivity analysis method to layout
sub-blocks, the disadvantages of critical area extraction in local layout geometry are
elimi
行了系统研究。主要研究结果如下：
首先，研究了工艺缺陷引起电路故障的机理，在冗余物缺陷和丢失物缺陷的
研究基础上，考虑了介质层针孔缺陷对功能成品率的影响，得到了针孔缺陷的故
障识别算法（应用于Monte Carlo成品率仿真）和关键面积提取算法。
本文对不同种类的缺陷分别提出了相应的故障识别算法。故障识别算法是功
能成品率仿真的核心技术。由于实际集成电路的复杂性，缺陷能否引起电路故障
与其出现位置以及版图图形有密切关系。在局部识别导体冗余物缺陷能否引起短
路故障时，考虑了实际版图图元的连接关系，消除了冗余物短路同一电连接网络
图元的误判断。分别对导体冗余物引起短路、丢失物引起开路、介质层针孔缺陷
引起纵向短路等故障情形提出了判别准则，并提出了有效的实现算法。
成功的开发了Monte Carlo功能成品率仿真系统。该系统综合了本文在制造
缺陷模型、负二项分布随机数发生、CIF版图解码、缺陷故障识别以及MC成品
率仿真策略等方面的研究结果，用超过8000行C++语言编程实现了图形界面交
互式功能成品率仿真。能够在多种缺陷模式下同时对IC多个故障敏感层进行
MC成品率分析并报告成品率。通过对金属微电子测试阵列和终端接口芯片XT-1
的成品率仿真实例，对仿真系统进行了检验。这是迄今为止的第一个集成电路功
能成品率仿真与设计系统。
本文在研究了现有关键面积计算模型及其不足之处后，首次提出了适用于一
般版图图形结构的关键面积计算模型，在实际算法设计中，通过同一版图层图元
连接关系的提取而避免了导体冗余物短路关键面积提取的错误情形，采用版图图
元分组排序算法而提高了短路关键面积提取计算效率。针对丢失物和针孔关键面
积也提出了相应的实现算法。并利用关键面积的概念，论述了Monte Carlo方法
和关键面积方法在芯片故障敏感度分析中的统一性。
本文在功能成品率优化设计方法研究上取得重要结果。论述了基本优化策
略，重点研究了基于局部版图布线调整的功能成品率优化方法。版图优化区域以
故障敏感度为根据进行分块优选。在分块优选中，采用Monte Carlo方法进行分
块版图敏感度分析，避免了关键面积方法在局部应用上的缺点，解决了局部版图
优化的分块优选问题。在局部版图优化调整方法上，提出了金属互连线层成品率
优化的局部线宽优化算法，并对线宽优化的特性进行了实例分析，说明了线宽优
集成电路功能成品率仿真与优化技术研究
化算法的有效性和适用情形。本文还研究了基于线型调整和连线位置调整的局部
版图优化技术，通过实际版图结构的关键面积特性对比说明了这两种技术的有效
性。此外，还对全局版图调整的功能成品率优化进行了研究与探讨，分析了版图
设计规则变化对功能成品率的影响。
研究结果表明，本文提出的功能成品率仿真与优化设计方法对成品率预报和
提高是十分有效的。
This dissertation aims at discussing the model, simulation and optimization
methods of functional yield of integrated circuits. The Author抯 main contributions are
as following:
First, the principle of circuit faults caused by manufacturing defects is studied.
Some manufacturing defects that have the most significant influence upon functional
yield, such as extra material defects, missing material defects and dielectric pinhole
defects, are discussed to obtain the corresponding geometrical abstractions. Then a
fault recognition algorithm and the critical area extraction method of dielectric
pinhole defects are presented.
Second, fault recognition is one of the kernel techniques of a functional yield
simulation system. In this dissertation, corresponding fault recognition algorithms are
proposed according to different defect types. Due to the complexity of layout, whether
a defect causes circuit faults or not is determined by the size, position of the defect
and the surrounding layout geometry. So the actual geometry net of local layout must
be extracted to avoid such a misrecognition case as an extra material defect touches
two or more neighboring conductors within a same electrical net. As a result, effective
rules to recognize defect-induced faults are presented to recognize primary fault
patterns, such as circuit short faults caused by extra material defects, line open faults
caused by missing material defects and circuit short faults between neighboring layers
caused by dielectric pinhole defects.
After combining research results of defects model, negative binomial random
number generation, CIF layout decoding, fault-recognition and Monte Carlo
functional yield simulation methodology, a functional yield simulation system is
developed. With its graphics user interface and interactive operations, the simulation
system can be applied to obtain the functional yield of an integrated circuiU by
analyzing its many defect modes and defect sensitive layers. With the simulation
results of a metal test structure layout and a terminal interface chip XT- 1, the
simulation system is checked.
Then, the available critical area extraction model and its disadvantages are
studied and an improved critical area extraction model is presented in this dissertation.
The improved model performs a good accuracy in critical area extraction for general
layout geomeity. Especially, geometry net of local layout is taken into account to
derive the efficient critical area extraction algorithms of extra material defects. A
grouping-sorting technique is also developed to improve the computation efficiency
of short critical area extraction. Therefore, different critical area extraction algorithms
ar~ developed according to diffem~f defect tvnes~ With the concept of critical area, the
unitarity of Monte Carlo method and critical area method is discussed in
fault-sensitivity analysis.
Finally, optimization design techniques for functional yield enhancement are
studied in this dissertation. By comparison of yield optimization methodologies, the
geometry adjustment method of local layout is proved suitable to improve functional
yield without increasing chip area. Based on the criterion of sub-block
fault-sensitivities of layout, the optimization selection problem of layout sub-blocks is
solved. Applying the Monte Carlo fault-sensitivity analysis method to layout
sub-blocks, the disadvantages of critical area extraction in local layout geometry are
elimi
引文
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第二章
[2.1] 马佩军，郝跃，刘红霞，针孔缺陷对集成电路功能成品率影响分析与仿真，半导体学报，Vol．22，No．1，2001．
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[2.4] L. Jastrzebski, Origin and Control of Material Defects in Silicon in VLSI Technologies: An Overview, IEEE Journal of Solid-State Circuits, 1982, 17(2): 105～107.
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[2.8] W. Maly, Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits, IEEE Trans. CAD/IC, 1985, 4(3): 166-177.
[2.9] 姜晓鸿，郝跃，徐国华，IC缺陷轮廓的分形插值模型，电子科学学刊(待发表)
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[2.13] G. Spiegel and A .P .Stroele, Optimization of deterministic test sets using an estimation of product quality, presented at the Asian Test Symp., Bejing, China. Nov.1993.
[2.14] W, Maly, Computer-Aided Design for VLSI Circuit Manufacturability, Proceedings of the IEEE, 1990, 78(2): 356～392.
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[2.16] J. P. De Gyvez and D .Chennian, IC Defect Sensitivity for Footprint Type Spot Defects, IEEE Trans. Computer-Aided Design, 1992, 11(5): 638～658.
[2.17] Christopher Hess and Albrecht Strole, Modeling of Real Defect Outlines for Defect Size Distribution and Yield Prediction, Proc .IEEE Int .Conference on Microelectronics Test Structures, 1993, 6(3): 85-91.
[2.18] 姜晓鸿，郝跃，徐国华，IC 制造中的真实缺陷轮廓表征方法研究，电子学报，1998，26(2)：11-14．
[2.19] Xiaohong Jiang, Yue Hao, G. Xu, Equivalent Circular Defect Model of Real Defect Outlines in the IC Manufacturing Process, IEEE Trans. On Semiconductor Manufacturing. 1998,11(3):432-441.
[2.20] Xiaohong Jiang, Yue Hao and Guohua Xu, A New Model of IC Defect Outlines for IC Fault Estimation and Yield Prediction. Submitted to the 1998 First International Conference on Intergrated Circuit Yield.
[2.21] 姜晓鸿，赵天绪，郝跃，徐国华，一种 IC 缺陷轮廓建模的新方法，电子学报，1999，27(5)：46～48．
[2.22] 姜晓鸿，郝跃，徐国华，IC 制造中的真实缺陷轮廓的分形特征，半导体学报，1998，19(2)：206～212．
[2.23] 姜晓鸿，郝跃，徐国华，IC 缺陷轮廓的分形插值模型，电子科学学刊(待发表)．
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[3.4] G. Moore, Switching Circuits for Yield Enhancement of an Array Chip,Electronics Letters, 1984, 18(6): 667～669.
[3.5] C. H. Stapper , Defect Density Distribution for LSI Yield Calculations, IEEE Transactions on Electron Devices, 1973, 20(7); 655～657.
[3.6] I. Chen and A. J. Strojwas, Realistic Yield summation for VLSIC Structural Failures, IEEE Transactions on Computer-Aided Design, 1987, 6(5): 965～980.
[3.7] C. H. Stapper, Yield Model for Fault Clusters Within Integrated Circuits, IBM J. Res. Develop., 1984, 28(5): 636～639.
[3.8] C. H. Stapper, Defect Density Distribution for LSI Yield Calculations, IEEE Trans. ED.,1973, 20(7): 655～657.
[3.9] J. Price, A New Look at Yield Integrated Circuits, Proceedings of the IEEE, 1970,58(8): 1209～1291.
[3.10] C. H. Stapper, F. M. Armstrong, and K. Saji, Integrated Circuits Yield Statistics,Proceeding of IEEE, 1983,71(4): 453～470.
[3.11] 郝跃，马佩军，张卫东，赵天绪，功能成品率估算的缺陷特征参数提取方法，电子学报，2000，28(8)：76～78．
[3.12] 姜晓鸿，集成电路局部缺陷及其相关的功能成品率和电迁徙问题的研究，西安电子科技大学博士学位论文，1998，11．
[3.13] Christopher Hess and Larg H.Weiland, Harp Test Structure to Electrically Determine Size Distributions of Killer Defects, IEEE Trans. On Semiconductor Manufacturing 1998, 11(2):194～203.
[3.14] C.Hess and L. H. Weiland, Extraction of Wafer-Level Defect Density Distribution to Improve Yield Prediction, IEEE Trans. On Semiconductor Manufacturing 1999,12(2): 175～183.
[3.15] 赵天绪，集成电路缺陷分布模型和容错技术研究，西安电子科技大学博士学位论文，1999．12．
第四章
[4.1] 马佩军，郝跃，刘红霞，针孔缺陷对集成电路功能成品率影响分析与仿真，半导体学报，Vol．22，No．1，2001．
[4.2] H. Walker, Yield Simulation for Integrated Circuit, Kluwer Academic Publishers, USA.,1987.
[4.3] 郝跃，林锐，马佩军，VLSI成品率预测与仿真，电子学报，Vol．27，No．2，Feb 1999
[4.4] 徐士良，C语言常用算法程序集，清华大学出版社，1994．
[4.5] 吴新瞻，吴新垣，随机模型与计算机模拟，电子工业出版社，1990．
[4.6] 贾新章，郝跃，微电子技术概论，1992．
[4.7] 林锐，集成电路可制造性设计系统的研究，西安电子科技大学硕士学位论文，1996．12．
[4.8] 孙家广，许隆文，计算机图形学，清华大学出版社，1986．
[4.9] 蔡希尧，陈平，面向对象技术技术，西安电子科技大学出版社，1993．
[4.10] 乔林，C++Builder 5技术内幕，中国铁道出版社，2000．
第五章
[5.1] C.H.Stapper and R.J.Rosner. Integrated Circuit Yield Management and Yield Analysis: Development and Implementation, IEEE Trans. On Semiconductor Manufacturing 1995, 8(2): 95～102,
[5.2] L.S.Milor, J.Orth and D.Stelle. The Application of Submicron Lithography Defect Simulation to IC Yield Improvement,IEEE Trans. On Semiconductor Manufacturing 1999,12(1): 11～25
[5.3] A.V. Ferris-Prabhu, Modeling the Critical Area in Yield Forecasts, IEEE J.of Solid-State Circuits, 1985 Vol.SC-20,No.4 p874～878
[5.4] Albert V. Ferris-Prabhu, Defect Size Variations and Their Effect on the Critical Area of VLSI Devices , IEEE J.of Solid-State Circuits, 1985 Vol. SC-20,No.4 p878～882
[5.5] C.Mead,L.Conway, Introduction to VLSISysstem,Addison-Wesley Publishing Comp.,1988
[5.6] 马佩军，郝跃，寇芸，一种改进的 VLSI 关键面积计算模型和方法，半导体学报(已投)
[5.7] 夏海良，张安康．半导体器件制造工艺，上海科学技术出版社，1988，P60～61
[5.8] G. A. Allan and A. J. Walton. Efficient critical area algorithms and their application to yield improvement and test strategies. In IEEE Workshop on Defect and Fault Tolerance in VLSI Systems,1994,pages 88～96,Montreal,Quebec,Canada.
[5.9] 姜晓鸿，《集成电路局部缺陷及相关的功能成品率和电迁徙问题的研究》，西安电子科技大学博士论文，1998，11
[5.10] 马佩军，郝跃，刘红霞，针孔缺陷对集成电路功能成品率影响分析与仿真，半导体学报，Vol．22，No．1，2001．
第六章
[6.1] G. A. Allan and A. J. Walton. Efficient critical area algorithms and their application to yield improvement and test strategies. In IEEE Workshop on Defect and Fault Tolerance in VLSI Systems, pages 88-96, Montreal, Quebec, Canada, Oct 1994.
[6.2] V.K.R. Chiluvuri and I. Koren. New routing and compaction strategies for yield enhancement. In IEEE Workshop on Defect and Fault Tolerance in VLSI Systems, Nov 1992.
[6.3] D. D. Hill. Algorithms and Techniques for VLSI layout synthesis. Kluwer, Boston; Lancaster:, 1989.
[6.4] K. Ueda, R. Rasai, and T. Sudo. Layout strategy, standardization and CAD tools. In T. Ohtsuki, editor, Layout Design and Verification. Elsevier Science Publishers, B.V North-Holland, 1986.
[6.5] T. Yoshimura and E. S. Kuh. Efficient algorithms for channel routing. IEEE Trans Comp. Aided Design, CAD-1 (1):25-35, Jan 1982.
[6.6] M. Burstein. Channel routing. In T. Ohtsuki, editor, Layout Design and Verification. Elsevier Science Publishers, B.V North-Holland, 1986.
[6.7] A. Pitaksanonkul, S Thanawastien, C. Lursinsap, and J.A. Gandhi. DTR: A defect-tolerant routing algorithm. In 26th ACM/IEEE Design Automation Conference, pages 795-798, 1989.
[6.8] S. Kuo. YOR: A yield-optimizing routing algorithm by minimizing critical areas and vias. IEEE Trans Comp. Aided Design, 12(9), Sep 1993.
[6.9] V.K.R. Chiluvuri and I. Koren. New routing and compaction strategies for yield enhancement. In IEEE Workshop on Defect and Fault Tolerance in VLSI Systems, Nov 1992.
[6.10]Vnkat K.R.Chiluvuri, and Israel Koren, Layout-Synthesis Techniques for Yield Enhancement, IEEE Transactions On Semeconductor Manufacturing, P178～P187, Vol.8, No.2, May 1995
[6.11]C.H.Stapper. Modeling of integrated circuit deect sensitivities. IBM J.Res. Develop., 27(6):549--557, Nov 1983.
[6.12]G.A. Allan, J.P.Elliott, A.J. Walton;"EYE: A Tool for Measuring the Defect Sensitivity of IC Layout", IEE Colloquium on Improving the Eiciency of IC Manuacturing Technology,, No 1995/153,pp.5/1-5/4,12th April 1995.
[6.13]G.A. Allan, A.J.Walton;" A Defect Sensitivity Measurement Tool Enabling Comparison of IC Layout Sensitivity", VLSI Multi-Level Interconnect conference, pp. 655-657, June 1995.
[6.14]马佩军，郝跃，提高成品率的VLSI互连线线宽优化，西安电子科技(已投)
[6.15]张廷庆，张开华，朱兆宗，半导体集成电路，上海科学技术出版社，1988．
[6.16]郝跃，林锐，马佩军，VLSI成品率预测与仿真，电子学报，Vol．27，No．2，Feb 1999．
[1.2] CERN, The Second PASTA Report-The LHC Technology Tracking Team for Processors, Memory, Architectures, Storage and Tapes, August 1999,pp8
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[1.4] H. Walker, Yield Simulation for Integrated Circuit, Kluwer Academic Publishers, USA., 1987.
[1.5] 郝跃，集成电路制造动力学理论与研究，河北教育出版社，1995年11月第一版．
[1.6] A. J. Strojwas, Design for Manufacturing and Yield, 1989 26th ACM/IEEE Design Automation Conf., USA, 454～459,1989.
[1.7] C. H. Stapper, Yield Model for Fault Clusters Within Integrated Circuits, IBM J. Research and Development, 1984, 28(5): 636～639.
[1.8] A. Gupta, Yield Analysis of Large Integrated Circuit Chips, IEEE J. SSC., 1972, 7(5): 389～395.
[1.9] C. H. Stapper, The Effects of Wafer to Wafer Defect Density Variation on Integrated Circuit Defect and Fault Distribution, IBM J. Research and Development, 1985, 29(1): 87～97.
[1.10] A. Ferris-Prabhu, Radial Yield Variation in Semiconductor Wafers, IEEE Circuits and Devices Magazine, 1987, 3(2): 42～47.
[1.11] A. Gupta, Defect Analysis and Yiled Degradation of Integrated Circuits, IEEE J. SSC., 1974, 9(3): 96～103.
[1.12] I.Chen, A. J. Strojwas, Realistic Yield Simulation for VLSIC Structural Failures, IEEE Trans. CAD/IC, 1987, 6(6): 965～980.
[1.13] C. Hess, L. H. Weiland, Extraction of Wafer-Level Defect Density Distribution to Improve Yield Prediction, IEEE Trans. On Semiconductor Manufacturing, 1999, 12(2): 175～183.
[1． 14] K. Antreich, Design Centering by Yield Prediction, IEEE Trans. CAS., 1982, 29(2) : 88-95．
[1． 15] J. Rankin, S. R. Soin, Efficient Monte Carlo Yield Prediction Using Control Variations, Proc. IEEE Int. Symp. CAS., 1981,pp.l43-148．
[1． 16] C. Mead, L. Conway, Introduction to VLSI System, Addison-Wesley Publishing Comp., 1988．
[1． 17] C. H. Stapper, Evolution and Accomplishments of VLSI Yield Management at IBM, IBM J. Res. Development, 1982, 26(5) : 532-545．
[1． 18] Z. Stamenkovic, S. Dimitrijew, and N. Stojadinovic, Integrated Circuit Production Yield Assurance Based on Yield Analysis, Microelectronics Journal, 1993, 24(4) : 819-822．
[1． 19] S. Dimitrijew, N. Stojadinovic, and Z. Stamenkovic, Yield Model for In-Line Integrated Circuit Production Control, Solid-State Electronics, 1988, 31(5) : 975-979．
[1． 20] M. Jacomet, W. Guggenuhl, Layout Dependent Fault Analysis and Test Synthesis for CMOS Circuits, IEEE Trans. CAD/IC, 1993, 10(3) :888-899．
[1． 21] A. R. Dalai, P. D. Franzov, A Layout-Driven Yield prediction and Fault Generator for VLSI, IEEE Trans. Semiconductor Manufacturing, 1993, 6(1) : 77-82．
[1． 22] R. K. Brayton, R. Spence, A Survey of Optimization Techniques for Integrated-Circuit Design, Proceeding of IEEE, 1981, 69(19) : 1334-1362．
[1． 23] R. K. Brayton, R. Spence, Sensitivity and Optimization, CAD of Electronic Circuits, Elservier Scientific Pub. Comp., 1980．
[1． 24] J. Khare, and W. Maly, Accurate Estimation of Defect-Related Yield Loss in Reconfigurable VLSI Circuits, IEEE J. Solid-State Circuit, 1993, 28(2) :146-157．
[1． 25] T. L. Mchalka, R. C. Varshney,and J. D. Meindl, A Discussion of Modeling with Defecting, Circuit Repair, and Circuit Redundancy, IEEE Trans. Semiconductor Manufacturing, 1990, 3(1) : 116-127．
[1． 26] J. Raffel, A. Anderson, A Wafer-Scale Digital Integrated Circuit Using Restructurable VLSI, IEEE J. Solid-State Circuit, 1985,25(1) : 399-406．
第二章
[2.1] 马佩军，郝跃，刘红霞，针孔缺陷对集成电路功能成品率影响分析与仿真，半导体学报，Vol．22，No．1，2001．
[2.2] R. Ashecaska, G, Filaretor. Prediction of the Yield of Suitable MOS Structures with Respct to the Subgate Dielectric, IEEE Journal of Solid-State Circuits, 1980, 15(4): 687～693.
[2.3] K. Satio, and E. Arai, Experimental Analysis and New Modeling of MOS LSI Yield Aassociated with the Number of Elements, IEEE Journal of Solid-State Circuits, 1982, 17(1): 28～33.
[2.4] L. Jastrzebski, Origin and Control of Material Defects in Silicon in VLSI Technologies: An Overview, IEEE Journal of Solid-State Circuits, 1982, 17(2): 105～107.
[2.5] C.H. Stapper, P. Castrussi, R. Maeder, W. Rowe,and R. Verhelst, Evolution and Acomplishments of VLSI Yield Management at IBM, IBM J. RES. DEVELOP.,1982, 2695): 532～545.
[2.6] I. Koren, Z. Koren, Defect Tolerance in VLSI Circuits: Techniques and Yield Analysis, Proceedings of the IEEE, 1998, 86(9): 1819～1836.
[2.7] T. Mangir, Sources of Failures and Yield Improvement for VLSI and Restructurable Interconnects for VLSI and WSI: Part I-Sources of Failures and Yield Improvement for VLSI, Proceedings of the IEEE, 1984, 72(6):690～708.
[2.8] W. Maly, Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits, IEEE Trans. CAD/IC, 1985, 4(3): 166-177.
[2.9] 姜晓鸿，郝跃，徐国华，IC缺陷轮廓的分形插值模型，电子科学学刊(待发表)
[2.10] F .J .Ferguson and J .P .Shen, Extraction and Simulation of Realistic CMOS Faults Using Inductive Fault Analysis , Presented at the Internet. Test Conf.,1988.
[2.11] A..V. Ferris Prabhu, Modeling the critical area in yield forecasts, IEEE J.Solid-State Circ., 1985, SC20(4): 874～878.
[2.12] W. Lukaszek, W .Yarbrough, T. Walker ,and J. Meindl, CMOS test chip design for process problem debugging and yield prediction experiments, Solid State Technol.,1986,29(3)87～93
[2.13] G. Spiegel and A .P .Stroele, Optimization of deterministic test sets using an estimation of product quality, presented at the Asian Test Symp., Bejing, China. Nov.1993.
[2.14] W, Maly, Computer-Aided Design for VLSI Circuit Manufacturability, Proceedings of the IEEE, 1990, 78(2): 356～392.
[2.15] A. V. Ferris-Prabhu, Defect Size Variations and Their Effect on the Critical Area of VLSI Devices, IEEE J.Solid-State Circ.,1985, 20(4): 874～8778.
[2.16] J. P. De Gyvez and D .Chennian, IC Defect Sensitivity for Footprint Type Spot Defects, IEEE Trans. Computer-Aided Design, 1992, 11(5): 638～658.
[2.17] Christopher Hess and Albrecht Strole, Modeling of Real Defect Outlines for Defect Size Distribution and Yield Prediction, Proc .IEEE Int .Conference on Microelectronics Test Structures, 1993, 6(3): 85-91.
[2.18] 姜晓鸿，郝跃，徐国华，IC 制造中的真实缺陷轮廓表征方法研究，电子学报，1998，26(2)：11-14．
[2.19] Xiaohong Jiang, Yue Hao, G. Xu, Equivalent Circular Defect Model of Real Defect Outlines in the IC Manufacturing Process, IEEE Trans. On Semiconductor Manufacturing. 1998,11(3):432-441.
[2.20] Xiaohong Jiang, Yue Hao and Guohua Xu, A New Model of IC Defect Outlines for IC Fault Estimation and Yield Prediction. Submitted to the 1998 First International Conference on Intergrated Circuit Yield.
[2.21] 姜晓鸿，赵天绪，郝跃，徐国华，一种 IC 缺陷轮廓建模的新方法，电子学报，1999，27(5)：46～48．
[2.22] 姜晓鸿，郝跃，徐国华，IC 制造中的真实缺陷轮廓的分形特征，半导体学报，1998，19(2)：206～212．
[2.23] 姜晓鸿，郝跃，徐国华，IC 缺陷轮廓的分形插值模型，电子科学学刊(待发表)．
[3.1] B. Murphy, Cost-Size Optima of Monolithic Integrated Circuits, Proceeding of the IEEE, 1964, 50(12):1525～11527.
[3.2] R. Seeds, Yield and Cost Analysis of Bipolar LSI, IEDM., 1967.
[3.3] J. Price, A New Looh at Yield of Integrated Circuits, Proceeding of the IEEE,1970, 58(8): 1209～1291.
[3.4] G. Moore, Switching Circuits for Yield Enhancement of an Array Chip,Electronics Letters, 1984, 18(6): 667～669.
[3.5] C. H. Stapper , Defect Density Distribution for LSI Yield Calculations, IEEE Transactions on Electron Devices, 1973, 20(7); 655～657.
[3.6] I. Chen and A. J. Strojwas, Realistic Yield summation for VLSIC Structural Failures, IEEE Transactions on Computer-Aided Design, 1987, 6(5): 965～980.
[3.7] C. H. Stapper, Yield Model for Fault Clusters Within Integrated Circuits, IBM J. Res. Develop., 1984, 28(5): 636～639.
[3.8] C. H. Stapper, Defect Density Distribution for LSI Yield Calculations, IEEE Trans. ED.,1973, 20(7): 655～657.
[3.9] J. Price, A New Look at Yield Integrated Circuits, Proceedings of the IEEE, 1970,58(8): 1209～1291.
[3.10] C. H. Stapper, F. M. Armstrong, and K. Saji, Integrated Circuits Yield Statistics,Proceeding of IEEE, 1983,71(4): 453～470.
[3.11] 郝跃，马佩军，张卫东，赵天绪，功能成品率估算的缺陷特征参数提取方法，电子学报，2000，28(8)：76～78．
[3.12] 姜晓鸿，集成电路局部缺陷及其相关的功能成品率和电迁徙问题的研究，西安电子科技大学博士学位论文，1998，11．
[3.13] Christopher Hess and Larg H.Weiland, Harp Test Structure to Electrically Determine Size Distributions of Killer Defects, IEEE Trans. On Semiconductor Manufacturing 1998, 11(2):194～203.
[3.14] C.Hess and L. H. Weiland, Extraction of Wafer-Level Defect Density Distribution to Improve Yield Prediction, IEEE Trans. On Semiconductor Manufacturing 1999,12(2): 175～183.
[3.15] 赵天绪，集成电路缺陷分布模型和容错技术研究，西安电子科技大学博士学位论文，1999．12．
第四章
[4.1] 马佩军，郝跃，刘红霞，针孔缺陷对集成电路功能成品率影响分析与仿真，半导体学报，Vol．22，No．1，2001．
[4.2] H. Walker, Yield Simulation for Integrated Circuit, Kluwer Academic Publishers, USA.,1987.
[4.3] 郝跃，林锐，马佩军，VLSI成品率预测与仿真，电子学报，Vol．27，No．2，Feb 1999
[4.4] 徐士良，C语言常用算法程序集，清华大学出版社，1994．
[4.5] 吴新瞻，吴新垣，随机模型与计算机模拟，电子工业出版社，1990．
[4.6] 贾新章，郝跃，微电子技术概论，1992．
[4.7] 林锐，集成电路可制造性设计系统的研究，西安电子科技大学硕士学位论文，1996．12．
[4.8] 孙家广，许隆文，计算机图形学，清华大学出版社，1986．
[4.9] 蔡希尧，陈平，面向对象技术技术，西安电子科技大学出版社，1993．
[4.10] 乔林，C++Builder 5技术内幕，中国铁道出版社，2000．
第五章
[5.1] C.H.Stapper and R.J.Rosner. Integrated Circuit Yield Management and Yield Analysis: Development and Implementation, IEEE Trans. On Semiconductor Manufacturing 1995, 8(2): 95～102,
[5.2] L.S.Milor, J.Orth and D.Stelle. The Application of Submicron Lithography Defect Simulation to IC Yield Improvement,IEEE Trans. On Semiconductor Manufacturing 1999,12(1): 11～25
[5.3] A.V. Ferris-Prabhu, Modeling the Critical Area in Yield Forecasts, IEEE J.of Solid-State Circuits, 1985 Vol.SC-20,No.4 p874～878
[5.4] Albert V. Ferris-Prabhu, Defect Size Variations and Their Effect on the Critical Area of VLSI Devices , IEEE J.of Solid-State Circuits, 1985 Vol. SC-20,No.4 p878～882
[5.5] C.Mead,L.Conway, Introduction to VLSISysstem,Addison-Wesley Publishing Comp.,1988
[5.6] 马佩军，郝跃，寇芸，一种改进的 VLSI 关键面积计算模型和方法，半导体学报(已投)
[5.7] 夏海良，张安康．半导体器件制造工艺，上海科学技术出版社，1988，P60～61
[5.8] G. A. Allan and A. J. Walton. Efficient critical area algorithms and their application to yield improvement and test strategies. In IEEE Workshop on Defect and Fault Tolerance in VLSI Systems,1994,pages 88～96,Montreal,Quebec,Canada.
[5.9] 姜晓鸿，《集成电路局部缺陷及相关的功能成品率和电迁徙问题的研究》，西安电子科技大学博士论文，1998，11
[5.10] 马佩军，郝跃，刘红霞，针孔缺陷对集成电路功能成品率影响分析与仿真，半导体学报，Vol．22，No．1，2001．
第六章
[6.1] G. A. Allan and A. J. Walton. Efficient critical area algorithms and their application to yield improvement and test strategies. In IEEE Workshop on Defect and Fault Tolerance in VLSI Systems, pages 88-96, Montreal, Quebec, Canada, Oct 1994.
[6.2] V.K.R. Chiluvuri and I. Koren. New routing and compaction strategies for yield enhancement. In IEEE Workshop on Defect and Fault Tolerance in VLSI Systems, Nov 1992.
[6.3] D. D. Hill. Algorithms and Techniques for VLSI layout synthesis. Kluwer, Boston; Lancaster:, 1989.
[6.4] K. Ueda, R. Rasai, and T. Sudo. Layout strategy, standardization and CAD tools. In T. Ohtsuki, editor, Layout Design and Verification. Elsevier Science Publishers, B.V North-Holland, 1986.
[6.5] T. Yoshimura and E. S. Kuh. Efficient algorithms for channel routing. IEEE Trans Comp. Aided Design, CAD-1 (1):25-35, Jan 1982.
[6.6] M. Burstein. Channel routing. In T. Ohtsuki, editor, Layout Design and Verification. Elsevier Science Publishers, B.V North-Holland, 1986.
[6.7] A. Pitaksanonkul, S Thanawastien, C. Lursinsap, and J.A. Gandhi. DTR: A defect-tolerant routing algorithm. In 26th ACM/IEEE Design Automation Conference, pages 795-798, 1989.
[6.8] S. Kuo. YOR: A yield-optimizing routing algorithm by minimizing critical areas and vias. IEEE Trans Comp. Aided Design, 12(9), Sep 1993.
[6.9] V.K.R. Chiluvuri and I. Koren. New routing and compaction strategies for yield enhancement. In IEEE Workshop on Defect and Fault Tolerance in VLSI Systems, Nov 1992.
[6.10]Vnkat K.R.Chiluvuri, and Israel Koren, Layout-Synthesis Techniques for Yield Enhancement, IEEE Transactions On Semeconductor Manufacturing, P178～P187, Vol.8, No.2, May 1995
[6.11]C.H.Stapper. Modeling of integrated circuit deect sensitivities. IBM J.Res. Develop., 27(6):549--557, Nov 1983.
[6.12]G.A. Allan, J.P.Elliott, A.J. Walton;"EYE: A Tool for Measuring the Defect Sensitivity of IC Layout", IEE Colloquium on Improving the Eiciency of IC Manuacturing Technology,, No 1995/153,pp.5/1-5/4,12th April 1995.
[6.13]G.A. Allan, A.J.Walton;" A Defect Sensitivity Measurement Tool Enabling Comparison of IC Layout Sensitivity", VLSI Multi-Level Interconnect conference, pp. 655-657, June 1995.
[6.14]马佩军，郝跃，提高成品率的VLSI互连线线宽优化，西安电子科技(已投)
[6.15]张廷庆，张开华，朱兆宗，半导体集成电路，上海科学技术出版社，1988．
[6.16]郝跃，林锐，马佩军，VLSI成品率预测与仿真，电子学报，Vol．27，No．2，Feb 1999．