集成电路设计中针对随机缺陷的成品率研究
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摘要
半导体制造是一个复杂的过程,尤其进入纳米技术节点后,工艺步骤越来越多,其中每一步工艺都有可能引入随机缺陷,造成电路故障,引起成品率问题。集成电路的成品率是决定半导体产业经济利润的重要因素。随着集成电路制造工艺进入到纳米时代,由随机缺陷引起的成品率问题越来越严重,即使在成熟的制造环境下,成品率也不可能达到100%。这就要求在设计阶段能够准确预测成品率,给成品率提升指明方向,缩短生产周期、降低生产成本,从而提升利润。
本文首先介绍了影响芯片成品率的因素及其可能引起的故障类型,并概述了随机缺陷在芯片中的空间分布及粒径分布等特性；然后介绍目前广泛使用的成品率预测模型以及它们所采用的分布函数,分析它们的局限性和不足,同时结合随机缺陷的分布特征提出一个改进的模型。通过Matlab仿真,该模型相比于目前主流的模型确实具有更高的灵活性和准确度。同时,本文通过布图规划、时钟树综合以及布局布线等过程,得到一个版图数据。在此版图数据基础上,进行关键面积分析以及成品率的提升。我们改进了传统的优化流程,考虑芯片上不同区域缺陷密度的差异,在不同区域采用不同的提升方法,可以有效避免优化的重复迭代,大大缩短了芯片的生产周期。同时,针对不同的故障类型我们采用不同的成品率提升技术,如double via, wire spreading, wire widening等,减小设计对缺陷的敏感程度,提高成品率。
研究结果表明,本文提出的模型预测成品率的误差相对稳定且与实际成品率相近；通过提升技术的实施,成品率获得了有效的增长。本文的研究成果对于成品率的预测和提升具有重要的意义,有利于集成电路业获得更高的利润。
Semiconductor manufacturing is a complex process. When it comes into the nanometer technology era, the process steps become more and more, and every step of the process may introduce random particles resulting in circuit failure and then causing yield loss. Yield is an important factor which can determine the profits of semiconductor industry. But the yield loss caused by random particles becomes more and more serious especially in nanometer node. Even in the mature manufacturing environment, the yield can not be 100%. So it is important for us to predict yield during design phase which can give direction to yield enhancement and help to shorten the production cycle. It is also critical to reduce production costs and enhance profits.
This paper describes random defects which impact yield and the possible type of failure. And it also gives an overview of the size and spatial distribution characteristics of random particles. Then the current widely used prediction yield models and distribution functions are discussed, and then their limitations and shortcomings are analyzed. Combined with the distribution characteristics of random particles, an improved yield model is proposed. The simulation result given by Matlab shows that our model definitely has higher flexibility and accuracy.
Meanwhile, a layout is acquired through floorplan, place, cts and route. Then critical area analysis and yield enhancement is performed based on the layout. Also this paper optimizes the conventional design flow considering that the defect density is not the same in different regions on the chip. Through that, the iterative optimization can be avoided, and production cycle can be greatly reduced. This paper uses different enhancement methods for different fault types to reduce the sensitivity of the design and improve yield, such as double via, wire spreading, and wire widening.
Research results indicate that the error using the yield proposed in this paper to predict yield is relative stable, and the simulation result is similar to actual yield. Through the implementation of the enhancement, the yield increases effectively. This study has great significance and promotion for semiconductor industry and it can help manufacturing factories get more profits.
本文首先介绍了影响芯片成品率的因素及其可能引起的故障类型,并概述了随机缺陷在芯片中的空间分布及粒径分布等特性；然后介绍目前广泛使用的成品率预测模型以及它们所采用的分布函数,分析它们的局限性和不足,同时结合随机缺陷的分布特征提出一个改进的模型。通过Matlab仿真,该模型相比于目前主流的模型确实具有更高的灵活性和准确度。同时,本文通过布图规划、时钟树综合以及布局布线等过程,得到一个版图数据。在此版图数据基础上,进行关键面积分析以及成品率的提升。我们改进了传统的优化流程,考虑芯片上不同区域缺陷密度的差异,在不同区域采用不同的提升方法,可以有效避免优化的重复迭代,大大缩短了芯片的生产周期。同时,针对不同的故障类型我们采用不同的成品率提升技术,如double via, wire spreading, wire widening等,减小设计对缺陷的敏感程度,提高成品率。
研究结果表明,本文提出的模型预测成品率的误差相对稳定且与实际成品率相近；通过提升技术的实施,成品率获得了有效的增长。本文的研究成果对于成品率的预测和提升具有重要的意义,有利于集成电路业获得更高的利润。
Semiconductor manufacturing is a complex process. When it comes into the nanometer technology era, the process steps become more and more, and every step of the process may introduce random particles resulting in circuit failure and then causing yield loss. Yield is an important factor which can determine the profits of semiconductor industry. But the yield loss caused by random particles becomes more and more serious especially in nanometer node. Even in the mature manufacturing environment, the yield can not be 100%. So it is important for us to predict yield during design phase which can give direction to yield enhancement and help to shorten the production cycle. It is also critical to reduce production costs and enhance profits.
This paper describes random defects which impact yield and the possible type of failure. And it also gives an overview of the size and spatial distribution characteristics of random particles. Then the current widely used prediction yield models and distribution functions are discussed, and then their limitations and shortcomings are analyzed. Combined with the distribution characteristics of random particles, an improved yield model is proposed. The simulation result given by Matlab shows that our model definitely has higher flexibility and accuracy.
Meanwhile, a layout is acquired through floorplan, place, cts and route. Then critical area analysis and yield enhancement is performed based on the layout. Also this paper optimizes the conventional design flow considering that the defect density is not the same in different regions on the chip. Through that, the iterative optimization can be avoided, and production cycle can be greatly reduced. This paper uses different enhancement methods for different fault types to reduce the sensitivity of the design and improve yield, such as double via, wire spreading, and wire widening.
Research results indicate that the error using the yield proposed in this paper to predict yield is relative stable, and the simulation result is similar to actual yield. Through the implementation of the enhancement, the yield increases effectively. This study has great significance and promotion for semiconductor industry and it can help manufacturing factories get more profits.
引文
[1]陈春章,艾霞,王国雄.数字集成电路物理设计[M].北京：科学出版社,2008.
[2]王彬,任艳颖.数字IC系统设计[M].西安：西安电子科技大学出版社,2005.
[3]徐小田,李珂.我国IC产业全面提速[EB/OL].中国电子报社,2011.http://www.ic37.com/htm_tech/2007-8/31031_194770.htm
[4]ITRS 2009, International Technology Roadmap for Semiconductors[R]. Report International Technology Roadmap for Semiconductors,2009.
[5]RANI S GHAIDA, PAYMAN ZARKESH-HA. Estimation of Electromigration-Aggravating Narrow Interconnects Using a Layout Sensitivity Model [C].22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems,2007.
[6]纳米工艺可制造性设计EDA技术[J].中国集成电路,2007,93：31-38.
[7]张俊明.成品率估计与提升技术研究[D].西安：西安电子科技大学,2009.
[8]C. H. STAPPER. Defect Density Distribution for LSI Yield Calculations[J]. Electron Devices,1973,20:655-657.
[9]M. P-L.OOI, C. CHAN, S-L. LEE, et al. Towards Identification of Latent Defects: Yield Mining using Defect Characteristic Model and Clustering[C]. Advanced Semiconductor Manufacturing Conference,2009,7:194-199.
[10]BALASINSKI.A, PIKUS. F, BIELAWSKI. J. Yield Optimization with Model Based DFM[C]. Advanced Semiconductor Manufacturing Conference,2008,5:216-220.
[11]SINHA.S, QING SU, LINNI WEN. A New Flexible Algorithm for Random Yield Improvement[J]. Semiconductor Manufacturing,2008,2:14-21.
[12]LIU QINGHUA, TANG PUSHAN. Crosstalk Estimation and Optimization in Deep Sub-Micron VLSI[J]. Chinese Journal of Semiconductors,2002,23(5):535-542.
[13]王强,王俊平,任春丽.基于线性规划的关键面积最小化方法[J].电子科技,2008,10.
[14]杨祎巍.纳米级电路分辨率增强技术及可制造性研究[D].浙江大学,2010.
[15]中国科学院微电子研究所.微电子所可制造性设计(DFM)研究取得显著进展—自主研发的CMP工具交付中芯国际设计服务部门试用[EB/OL].2009.http://www.ime.ac.cn/xwzt/zhxw/200911/t20091130_2676867.html
[16]HIMANSHU BHATNAGAR. Chip Synthesis:Using Synopsys Design Compiler, Physical Compiler and PrimeTime[M]. New York:Kluwer Academic Publishers,2002.
[17]韩雁,韩晓霞,丁扣宝.集成电路设计CAD/EDA工具实用教程[M].北京：机械工业出版社,2010.
[18]徐敏,孙恺,潘峰.开源软核处理器OpenRisc的SOPC设计[M].北京：北京航空航天大学出版社,2008.
[19]CHIANG. C, KAWA. J. Three DFM Challenges:Random Defects, Thickness Variation, and Printability Variation[J]. Circuits and Systems,2006,12:1099-1102.
[20]Synopsys Customer Education Services. IC Compiler 1[P].2007,03-SP4.
[21]C. MATSUMOTO, Y. HAMAMURA, et al. Advanced Method for Defect Characterization using Fail Bit Analysis and Critical Area Simulation[J]. Semiconductor Manufacturing, 2011,5:151-157.
[22]ITRS 2006 Update, International Technology Roadmap for Semiconductors[R]. Report International Technology Roadmap for Semiconductors,2006.
[23]RANI S. GHAIDA, KEN DONIGER, PAYMAN ZARKESH-HA. Random Yield Prediction Based on a Stochastic Layout Sensitivity Model[J]. Semiconductor Manufacturing, 2009,8:329-337.
[24]G.A.ALLAN, A.J.WALTON. Hierarchical critical area extraction with the EYE tool [J]. Defect and Faulrt Tolerance in VLSI Systems,1995,11:13-15.
[25]C. H. STAPPER, R. J. ROSNER. Integrated circuit yield management and yield analysis: Development and implementation[J]. Semiconductor Manufacturing,1995,8:95-102.
[26]W. MALY, J. DESZEZKA. Yield estimation model for VLSI artwork evaluation[J]. Electron Lett,1983,19:226-227.
[27]A series Journal of the Chinese Physical Society[M]. Chinese Physical Society, 2006.
[28]A. V. FERRIS-PRABHU. Modeling the critical area in yield forecasts[J]. Solid-State Circuits,1985,20:874-878.
[29]B. T. MURPHY. Cost-Size optima of monolithic integrated circuits[C]. Proceedings of the IEEE,1964,52:1537-1545.
[30]R. B. SEEDS. Yield and cost analysis of bipolar LSI[J]. Electron Devices, 1968,15:409.
[31]C. H. STAPPER. Defect Density Distribution for LSI Yield Calculations [J]. Electron Devices,1973,20:655-657.
[32]YU. I. BOGDANOV, N. A. BOGDANOVA, V. L. DSHKHUNYAN. Statistical Yield Modeling for IC Manufacture:Hierarchical Fault Distributions[J]. Russian Microelectroni cs,2003,32:51-69.
[33]JAMES A. CUNNINGHAM. The Use and Evaluation of Yield Models in Integrated Circuit Manufacturing[J]. Semiconductor Manufacturing,1990,3:60-71.
[34]HANNO MELZNER. A Yield Model Incorporating Random and Systematic Yield Part I: Theory[C]. Advanced Semiconductor Manufacturing Conference,2008,5:206-215.
[35]H. G. PARKS. Yield Modeling From SRAM Failure Analysis[C]. Conference on Microelectronic Test Structures,1990,5:5-7.
[36]ALI BOUSETTA, ANDREW J. Cross. Adaptive Sampling Methodology for In-Line Defect Inspection[C]. Advanced Semiconductor Manufacturing Conference,2005,5:25-31.
[37]TSMC Concurrent CAA Optimization Presentation Synopsys ICC[R]. TSMC,2008.
[38]D. K. DE VRIES, P. L. C. SIMON. Calibration of open interconnect yield models[C]. Defect Fault Tolerance in VLSI Systems,2003.
[2]王彬,任艳颖.数字IC系统设计[M].西安：西安电子科技大学出版社,2005.
[3]徐小田,李珂.我国IC产业全面提速[EB/OL].中国电子报社,2011.http://www.ic37.com/htm_tech/2007-8/31031_194770.htm
[4]ITRS 2009, International Technology Roadmap for Semiconductors[R]. Report International Technology Roadmap for Semiconductors,2009.
[5]RANI S GHAIDA, PAYMAN ZARKESH-HA. Estimation of Electromigration-Aggravating Narrow Interconnects Using a Layout Sensitivity Model [C].22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems,2007.
[6]纳米工艺可制造性设计EDA技术[J].中国集成电路,2007,93：31-38.
[7]张俊明.成品率估计与提升技术研究[D].西安：西安电子科技大学,2009.
[8]C. H. STAPPER. Defect Density Distribution for LSI Yield Calculations[J]. Electron Devices,1973,20:655-657.
[9]M. P-L.OOI, C. CHAN, S-L. LEE, et al. Towards Identification of Latent Defects: Yield Mining using Defect Characteristic Model and Clustering[C]. Advanced Semiconductor Manufacturing Conference,2009,7:194-199.
[10]BALASINSKI.A, PIKUS. F, BIELAWSKI. J. Yield Optimization with Model Based DFM[C]. Advanced Semiconductor Manufacturing Conference,2008,5:216-220.
[11]SINHA.S, QING SU, LINNI WEN. A New Flexible Algorithm for Random Yield Improvement[J]. Semiconductor Manufacturing,2008,2:14-21.
[12]LIU QINGHUA, TANG PUSHAN. Crosstalk Estimation and Optimization in Deep Sub-Micron VLSI[J]. Chinese Journal of Semiconductors,2002,23(5):535-542.
[13]王强,王俊平,任春丽.基于线性规划的关键面积最小化方法[J].电子科技,2008,10.
[14]杨祎巍.纳米级电路分辨率增强技术及可制造性研究[D].浙江大学,2010.
[15]中国科学院微电子研究所.微电子所可制造性设计(DFM)研究取得显著进展—自主研发的CMP工具交付中芯国际设计服务部门试用[EB/OL].2009.http://www.ime.ac.cn/xwzt/zhxw/200911/t20091130_2676867.html
[16]HIMANSHU BHATNAGAR. Chip Synthesis:Using Synopsys Design Compiler, Physical Compiler and PrimeTime[M]. New York:Kluwer Academic Publishers,2002.
[17]韩雁,韩晓霞,丁扣宝.集成电路设计CAD/EDA工具实用教程[M].北京：机械工业出版社,2010.
[18]徐敏,孙恺,潘峰.开源软核处理器OpenRisc的SOPC设计[M].北京：北京航空航天大学出版社,2008.
[19]CHIANG. C, KAWA. J. Three DFM Challenges:Random Defects, Thickness Variation, and Printability Variation[J]. Circuits and Systems,2006,12:1099-1102.
[20]Synopsys Customer Education Services. IC Compiler 1[P].2007,03-SP4.
[21]C. MATSUMOTO, Y. HAMAMURA, et al. Advanced Method for Defect Characterization using Fail Bit Analysis and Critical Area Simulation[J]. Semiconductor Manufacturing, 2011,5:151-157.
[22]ITRS 2006 Update, International Technology Roadmap for Semiconductors[R]. Report International Technology Roadmap for Semiconductors,2006.
[23]RANI S. GHAIDA, KEN DONIGER, PAYMAN ZARKESH-HA. Random Yield Prediction Based on a Stochastic Layout Sensitivity Model[J]. Semiconductor Manufacturing, 2009,8:329-337.
[24]G.A.ALLAN, A.J.WALTON. Hierarchical critical area extraction with the EYE tool [J]. Defect and Faulrt Tolerance in VLSI Systems,1995,11:13-15.
[25]C. H. STAPPER, R. J. ROSNER. Integrated circuit yield management and yield analysis: Development and implementation[J]. Semiconductor Manufacturing,1995,8:95-102.
[26]W. MALY, J. DESZEZKA. Yield estimation model for VLSI artwork evaluation[J]. Electron Lett,1983,19:226-227.
[27]A series Journal of the Chinese Physical Society[M]. Chinese Physical Society, 2006.
[28]A. V. FERRIS-PRABHU. Modeling the critical area in yield forecasts[J]. Solid-State Circuits,1985,20:874-878.
[29]B. T. MURPHY. Cost-Size optima of monolithic integrated circuits[C]. Proceedings of the IEEE,1964,52:1537-1545.
[30]R. B. SEEDS. Yield and cost analysis of bipolar LSI[J]. Electron Devices, 1968,15:409.
[31]C. H. STAPPER. Defect Density Distribution for LSI Yield Calculations [J]. Electron Devices,1973,20:655-657.
[32]YU. I. BOGDANOV, N. A. BOGDANOVA, V. L. DSHKHUNYAN. Statistical Yield Modeling for IC Manufacture:Hierarchical Fault Distributions[J]. Russian Microelectroni cs,2003,32:51-69.
[33]JAMES A. CUNNINGHAM. The Use and Evaluation of Yield Models in Integrated Circuit Manufacturing[J]. Semiconductor Manufacturing,1990,3:60-71.
[34]HANNO MELZNER. A Yield Model Incorporating Random and Systematic Yield Part I: Theory[C]. Advanced Semiconductor Manufacturing Conference,2008,5:206-215.
[35]H. G. PARKS. Yield Modeling From SRAM Failure Analysis[C]. Conference on Microelectronic Test Structures,1990,5:5-7.
[36]ALI BOUSETTA, ANDREW J. Cross. Adaptive Sampling Methodology for In-Line Defect Inspection[C]. Advanced Semiconductor Manufacturing Conference,2005,5:25-31.
[37]TSMC Concurrent CAA Optimization Presentation Synopsys ICC[R]. TSMC,2008.
[38]D. K. DE VRIES, P. L. C. SIMON. Calibration of open interconnect yield models[C]. Defect Fault Tolerance in VLSI Systems,2003.