基于FPGA的TOFD超声焊缝探伤数据采集系统设计
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摘要
超声波TOFD (Time Of Flight Diffraction)法,即超声衍射时差探伤法,是利用衍射回波信号进行缺陷判别的一种非常有效的无损检测方法,在现今国内外已成为研究的热点。它具有检测速度快、精度高、缺陷检出率高、尺寸与定位准确、经济方便等优点。
     本文就是针对在TOFD超声焊缝探伤的背景下,设计了一种数据采集系统。该设计基于FPGA,并在USB2.0Slave FIFO传输模式下,对前端检测的数据进行A/D转换,并将数据传输到PC机中。同时还搭建了基于Olympus(奥林巴斯)公司的Focus-LT设备的另一个实验平台,与本设计所采集到的数据进行了对比。
     首先,在详细调研了TOFD关键技术与数据采集方式的基础上,确定了总体方案。包括硬件电路总体方案和数据的传输和处理流程,
     其次,概述了USB技术原理。基于CY7C68013芯片,采用USB2.0高速传输模式,利用USB Slvae FIFO传输方式,编写了其固件程序,配置了控制芯片的通道、端点、中断等参数。
     第三,设计硬件电路,A/D采样电路,和在FPGA中利用VHDL语言设计了各时序逻辑模块,如时钟模块、控制模块、FIFO缓冲模块以及Slave FIFO时序控制模块等。
     最后,进行了实验系统的测试,对FPGA配置芯片、USB控制器、超声探头、编码器器件选型,实现了速度基本为40M/s的数据传输速率。并利用Focus-LT设备搭建了另一个TOFD检测试验平台,进行焊缝缺陷的检测与数据采集,得到了检测的A扫和D扫图像,并对比分析了两组实验的数据。
TOFD (Time of flight diffraction) is one of the most advanced technologies in the industry field of ultrasonic nondestructive detecting. Sizes and locations of flaws could be gotten according to the difference between the time-intervals of return diffraction signals from the tips of flaw. It has been widely used in weld flaw detecting currently at home and abroad. There are many remarkable advantages such as highly detecting speed, precision, detectable rate, accurately locating flaws and convenience, etc.
     It designed a data collection system based on the TOFD ultrasonic weld flaw detecting. It collects analog data and transforms them to digital, using Slave FIFO transportation model in USB and FPGA to transport them to PC. Meanwhile, another experiment platform is set up with Focus-LT equipment which is made by Olympus Company, getting data and images to compare with this design.
     Firstly, the overall implementation scheme of the data collection system is presented, including hardware circuit plan, way of transportation and processing data, and the type of FPGA chip, USB controller, probe, encoder, etc.
     Secondly, USB theory is summarized firmware program in USB Slvae FIFO model based on CY7C68013is composed. Parameters like pipes, interfaces and interrupts are set.
     Thirdly, A/D data sampling circuit and modules based on FPGA which used VHDL language is designed, including clock module, controlling module, FIFO and Slave sequence controlling module.
     At last, after the debug of hardware&software is completed, components and chips are chose, transmitting speed is above40M/S. Meanwhile, another detecting experiment platform is set up with Focus-LT, data from two suits of experiment platform are compared. As expected, results demonstrate the correctness and applicability.
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