折叠内插模数转换器的高精度设计研究与实现
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摘要
研究和发展高速、高精度、低功耗的模数转换器对于应用于无线通讯系统和高清数字视频设备等数字信号处理的系统级芯片设计来说，具有非常重要的意义。基于非线性模拟预处理的折叠技术显著减少了比较器的数目，同时保留了快闪型结构的速度优势，但由于工艺失配和非线性的影响，其精度仍限制于6-8位。折叠内插模数转换器的高精度实现成为近年来的一个研究热点。
基于折叠内插转换器的传输特性，采用MATLAB构造了10位折叠内插模数转换器的整体模型。针对折叠带宽限制、折叠增益失配、内插增益误差和比较器失调等非理想效应所带来的转换器动态性能退化分别进行了行为级仿真、分析和讨论。针对10位转换目标，设计了两种直接折叠内插的两级转换结构。基于折叠内插的精度限制，采用将折叠结构与子区间结构相结合的方法设计实现了高精度三级流水折叠转换结构，并以此为基础提出了如下精度优化设计技术：
采用单位增益采样结构、增益提高的折叠共源共栅运算放大器和轨到轨的输入级设计实现了高精度的输入级采样保持电路，有利于克服低电源电压下共模电压降低对模数转换器的影响。
提出了并联和级联混合的折叠结构设计，以减小折叠非线性影响，抑制倍频效应所带来的带宽限制；采用级间分布式采样保持电路实现了流水折叠工作模式，缓解了每级折叠建立时间的要求，抑制高频折叠电压平移的误差。
提出了一种失调抵消预放大器电路，采用中和技术减小了回踢噪声，失调存储抵消的时序逻辑与流水折叠结构的级间采样保持完全兼容，有效地减小了预放大器的失调电压。
提出了级联内插电阻平均结构，将高精度所需的高倍内插系数分散到每级转换和折叠间进行，有效地提高了过零点的线性度的同时也避免由高倍内插引起的插值误差。采用梅比斯环平均网络消除了边界效应。
采用将子区间转换与内插技术相结合，设计实现了子区间选择交叠内插的方式，既扩大了插值范围，有利于将内插误差最小化，又提高了插值网络的利用率，节约面积，降低功耗。
采用奇偶校验算法实现了位同步校正技术，将三级转换结果校正后同步输出，避免了因分级转换不同步造成输出误差。
基于上述结构和电路的精度优化设计，采用SMIC0.18μm1P6M CMOS工艺设计实现了一种10位100MS/s折叠内插模数转换器。测试结果如下：INL和DNL的峰值分别为±0.48LSB和±0.33LSB。1.8V电源电压下，功耗仅为95mW，输入电压范围VP-P为1.0V，芯片面积2.29mm2。在100MS/s采样速率，20MHz输入信号下，ENOB为9.59位，SNDR为59.5dB，SFDR为82.49dB，FOM为1.23pJ/Conv，已达到同类设计的优秀水平。
The research and development of analog-to-digital converters (ADCs) with highspeed, high precision and low power consumption are very significant in the design ofSOC applied in DSP such as wireless communication system and high-definition digitalvideo display. Based on nonlinear analog signal preprocessing, the folding techniquegreatly reduces the number of comparators and keeps such high speed as flash structure,but its resolution is limited to usually6-8bits due to process mismatch and nonlinearity.The folding and interpolating ADC with high resolution become a hot research in recentyears.
Based on the transfer characteristics of the folding and interpolating circuits, abehavioral model of a10-bit folding and interpolating ADC is built in MATLAB.Performance degradation due to the nonideal effects such as limited bandwidth, gainmismatch, interpolation gain error and comparator offset are simulated and analyzed.Two two-stage-conversion architectures are designed for10-bit object. Consideringresolution limitation of folding and interpolation, a three-stage-conversion architecturewith pipelined folding is realized by the combination of folding and subranging. Themain contributions of precision optimization are followed:
A high-performance sample-and-hold circuit is designed by unity-gain-samplestructure, a gain-enhance folded-cascode operational amplifier and rail-to-rail input toimprove the common-mode input range at low supply.
A combined topology of parallel and cascaded folding is designed to reducenonlinearity and restrain the frequency-multiplier effect. Distributed interstagetrack/hold circuits realize the pipeline folding, relieve the settling requirement of eachstage, and make suitable folded signals without dc level shifting at high frequency.
A offset-cancellation preamplifier eliminates the input offset voltage. Its kickbacknoise is alleviated effectually by neutralization technique. Its control logic is compatiblewith distributed interstage track/holds for pipelined folding.
A cascaded resistive averaging interpolation is proposed to disperse highinterpolating rate to every stage for converting and folding. The linearity is improved,and the interpolating error of high rate is avoided. The boundary effect is eliminated byMoebius-band averaging network.
A subraging-selected-crossing interpolation is designed. It extend the interpolatingrange, minimize interpolating error and use interpolating network more effectually for saving area and power.
A bit-synchronized correction is implemented by odd-even parity algorithm. Thecorrected three-stage converted results output to avoid the error for multi-stageconversion.
Based on above designs, a10-bit100-MS/s folding and interpolating ADC isrealized in SMIC0.18μm1P6M CMOS. The measured result is: the peak INL and DNLare±0.48LSB and±0.33LSB, respectively. The dissipation power is only95mW at1.8V power supply. Input range is1.0VP-Pwith2.29mm~2active area. At20MHzinput@100MS/s,9.59ENOB,59.5dB of SNDR and82.49dB of SFDR are achieved.A superior FOM of1.23pJ/Conv is acquired, which is the advanced level in thisdirection.
基于折叠内插转换器的传输特性，采用MATLAB构造了10位折叠内插模数转换器的整体模型。针对折叠带宽限制、折叠增益失配、内插增益误差和比较器失调等非理想效应所带来的转换器动态性能退化分别进行了行为级仿真、分析和讨论。针对10位转换目标，设计了两种直接折叠内插的两级转换结构。基于折叠内插的精度限制，采用将折叠结构与子区间结构相结合的方法设计实现了高精度三级流水折叠转换结构，并以此为基础提出了如下精度优化设计技术：
采用单位增益采样结构、增益提高的折叠共源共栅运算放大器和轨到轨的输入级设计实现了高精度的输入级采样保持电路，有利于克服低电源电压下共模电压降低对模数转换器的影响。
提出了并联和级联混合的折叠结构设计，以减小折叠非线性影响，抑制倍频效应所带来的带宽限制；采用级间分布式采样保持电路实现了流水折叠工作模式，缓解了每级折叠建立时间的要求，抑制高频折叠电压平移的误差。
提出了一种失调抵消预放大器电路，采用中和技术减小了回踢噪声，失调存储抵消的时序逻辑与流水折叠结构的级间采样保持完全兼容，有效地减小了预放大器的失调电压。
提出了级联内插电阻平均结构，将高精度所需的高倍内插系数分散到每级转换和折叠间进行，有效地提高了过零点的线性度的同时也避免由高倍内插引起的插值误差。采用梅比斯环平均网络消除了边界效应。
采用将子区间转换与内插技术相结合，设计实现了子区间选择交叠内插的方式，既扩大了插值范围，有利于将内插误差最小化，又提高了插值网络的利用率，节约面积，降低功耗。
采用奇偶校验算法实现了位同步校正技术，将三级转换结果校正后同步输出，避免了因分级转换不同步造成输出误差。
基于上述结构和电路的精度优化设计，采用SMIC0.18μm1P6M CMOS工艺设计实现了一种10位100MS/s折叠内插模数转换器。测试结果如下：INL和DNL的峰值分别为±0.48LSB和±0.33LSB。1.8V电源电压下，功耗仅为95mW，输入电压范围VP-P为1.0V，芯片面积2.29mm2。在100MS/s采样速率，20MHz输入信号下，ENOB为9.59位，SNDR为59.5dB，SFDR为82.49dB，FOM为1.23pJ/Conv，已达到同类设计的优秀水平。
The research and development of analog-to-digital converters (ADCs) with highspeed, high precision and low power consumption are very significant in the design ofSOC applied in DSP such as wireless communication system and high-definition digitalvideo display. Based on nonlinear analog signal preprocessing, the folding techniquegreatly reduces the number of comparators and keeps such high speed as flash structure,but its resolution is limited to usually6-8bits due to process mismatch and nonlinearity.The folding and interpolating ADC with high resolution become a hot research in recentyears.
Based on the transfer characteristics of the folding and interpolating circuits, abehavioral model of a10-bit folding and interpolating ADC is built in MATLAB.Performance degradation due to the nonideal effects such as limited bandwidth, gainmismatch, interpolation gain error and comparator offset are simulated and analyzed.Two two-stage-conversion architectures are designed for10-bit object. Consideringresolution limitation of folding and interpolation, a three-stage-conversion architecturewith pipelined folding is realized by the combination of folding and subranging. Themain contributions of precision optimization are followed:
A high-performance sample-and-hold circuit is designed by unity-gain-samplestructure, a gain-enhance folded-cascode operational amplifier and rail-to-rail input toimprove the common-mode input range at low supply.
A combined topology of parallel and cascaded folding is designed to reducenonlinearity and restrain the frequency-multiplier effect. Distributed interstagetrack/hold circuits realize the pipeline folding, relieve the settling requirement of eachstage, and make suitable folded signals without dc level shifting at high frequency.
A offset-cancellation preamplifier eliminates the input offset voltage. Its kickbacknoise is alleviated effectually by neutralization technique. Its control logic is compatiblewith distributed interstage track/holds for pipelined folding.
A cascaded resistive averaging interpolation is proposed to disperse highinterpolating rate to every stage for converting and folding. The linearity is improved,and the interpolating error of high rate is avoided. The boundary effect is eliminated byMoebius-band averaging network.
A subraging-selected-crossing interpolation is designed. It extend the interpolatingrange, minimize interpolating error and use interpolating network more effectually for saving area and power.
A bit-synchronized correction is implemented by odd-even parity algorithm. Thecorrected three-stage converted results output to avoid the error for multi-stageconversion.
Based on above designs, a10-bit100-MS/s folding and interpolating ADC isrealized in SMIC0.18μm1P6M CMOS. The measured result is: the peak INL and DNLare±0.48LSB and±0.33LSB, respectively. The dissipation power is only95mW at1.8V power supply. Input range is1.0VP-Pwith2.29mm~2active area. At20MHzinput@100MS/s,9.59ENOB,59.5dB of SNDR and82.49dB of SFDR are achieved.A superior FOM of1.23pJ/Conv is acquired, which is the advanced level in thisdirection.
引文
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