高速低功耗A/D转换器及相关技术研究
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摘要
随着CMOS制造工艺的不断进步,越来越多的信号处理功能在数字领域内完成,以较低的成本实现高速、低功耗。而现实世界的信号大多是模拟的,需要模数(A/D)转换器将模拟信号转化成数字信号进行处理。A/D转换器的速度和功耗已经成为评价其性能指标的关键因素,是衡量其是否可以在通讯网络、便携式视频设备中应用的重要指标。
本文首先实现了一种高速、低功耗的流水插值A/D转换器,分析了并指出了该A/D转换器输出特性受电源变化影响比较大的缺点。在该流水插值A/D转换器中引入了片上的LDO稳压器,以改善其电源抑制,并对应用在该流水插值A/D转换器中的带隙基准源和LDO稳压器等相关电路技术进行了研究。本论文主要包括以下几个方面内容:
实现了一种流水插值的A/D转换器。该A/D转换器应用三级流水的斩波反相放大器、电容插值结构和预平衡的比较器,以实现高速、低功耗。给出了时钟产生电路和输出编码电路等数字电路结构,对该流水插值A/D转换器进行了投片测试。分析了电源噪声对该A/D转换器性能的影响,给出了低电源电压下该流水插值A/D转换器的性能仿真结果。
研究了低压曲率校正带隙基准源设计技术。基于温度相关电阻比技术,提出了分段非线性曲率校正电流产生电路。在低温度段,该校正电流为零,中温段与温度成指数关系,高温段与温度的平方成正比。将该非线性曲率校正电流应用在了一个低压电流模式带隙基准源中,设计了一个1V电压、低温度系数曲率校正带隙基准源。将非线性曲率校正电流产生电路应用在了一个电压模式带隙基准源中,实现了一个带有负反馈的曲率校正带隙基准源。其主要特点是曲率校正电流产生电路在输出回路上形成了一个负反馈,只用一个电路模块实现了降低温度系数、改善基准源的电源抑制与线性调整率等功能。该负反馈电路结构简单,需要面积和功耗非常小。实验结果验证了设计思想的正确性。
研究了片上应用的低噪声LDO稳压器实现技术。简单分析了应用预稳压电路的LDO稳压器线性调整率和负载调整率与电路参数的关系,实现了一种片上应用的CMOS低噪声、高电源抑制LDO稳压器。提出了一种可以应用于LDO稳压器和带隙基准源之间的共享预稳压电路,该共享预稳压电路基于电流负反馈原理设计,可以显著降低其基准源性能随工艺阈值电压变化的敏感度,提高参考源的电源抑制,降低LDO稳压器的输出噪声。该共享的预稳压电路结构已经申请发明专利。
设计了一种应用片上LDO稳压器的高速、低功耗A/D转换器。该A/D转换器包括参考电压产生电路、低噪声LDO稳压器和流水插值A/D转换器三个模块。应用1V曲率校正带隙基准源产生基准电压,这个基准电压经过电平移位电路和缓冲电路为A/D转换器提供高精度的顶部和底部参考电压。电平移位电路的另一路输出形成了一个预稳压电路,预稳压电路与其后的两个功率驱动电路形成了一个低噪声、双路输出LDO稳压器。这个双路输出的LDO稳压器为A/D转换器提供模拟和数字的电源电压。对流水放大器的电路参数进行了优化,以降低噪声改善信噪比,在低压下实现高速低功耗。仿真结果表明该应用LDO稳压器的A/D转换器具有工作电压范围大、功耗低等优点。
With the rapid development of CMOS process, more and more singnal processing is processed in digital domain to achieve high speed and low power with low cost. While most of the signal in our reality world is anglog, analog-to-digital (A/D) converters are required to tansform analog signal into digital signal for processing. The speed and power have become the key factors to evaluate its performance, which are important factors to determine whether they can be used in communication network and portable video equipment.
A high speed low power pipelined interpolating A/D converter is implemented; the disadvantage of its performance easily affected by the supply variation is analyzed and given. In order to improve its power supply rejection, an on-chip LDO regulator is applied in the high speed, low power pipelined interpolating A/D converter. The related techniques of bandgap refereance and LDO regulator applied in the pipelined interpolating A/D converter are investigated. The thesis includes the following aspects:
A high speed pipelined interpolating A/D converter is implemented. A three-stage pipeline chopper inverter phase amplifier, capacitive interpolation and pre-equalized comparator are utilized to achieve high speed and low power. The clock generator and output encode circuit is given. The pipeined interpolating A/D converter is fabricated and measured. The affection of supply ripple on the performance of the A/D converter is analyzed and the simulaton result of the A/D convter in low voltage is given.
Low voltage curvature corrected bandgap references are designed. A piecewise nonlinear curvature corrected current generator based on temperature related ratio is proposed. In the low, middle and high temperature range, the curvature-corrected current is zero, proportion to expontial and squared with temperature respectively. The nonlinear curvature corrteded current generator is utilized in a low voltage current-mode bandgap reference to design a 1V curvature corrected bandgap reference with low temperature coefficient. Applying the nonlinear curvature corrected current generator in a voltage-mode bandgap reference, a curvature corrtected bandgap reference with negative is designed and implemented. The distinguish feature is a negative is formed between the curvature corrected current generator and the output circuit. The two objects of decreaseing the temperature coefficient, improveing power supply rejection (PSR) and line regulation are achieved with only one circuit module. The negative is simple, which needs little extra chip area and power consumption. Experiment results shows the design consideration is correct.
The implementation technique of low noise LDO regulator for on-chip application is investigated. The relation of line regulation and load regulation with circuit parameters for the LDO regulator with pre-regulator is analyzed briefly. A CMOS low noise, high PSR LDO regulators for on-chip application is implemented. A sharing pre-regulator for LDO regulator is proposed. The pre-regulator is designed based on current negative feedback, which dramatically decreases the sentivity of its bandgap reference performance with the variation of threshold, increases the PSR of its bandgap reference, and decreases the output noise of the LDO regulator. The architecture of the sharing pre-regulator is applied in an invention patent.
A high speed low power A/D converter with on-chip LDO regulatos is designed, which includes reference generator, low noise LDO regulator and a pipelined interpolating A/D converter. The 1V curvature corrected bandgap reference is utilized in the A/D converters, which is followed by a level shifter and two buffers to provide the top and bottom references for the A/D converter. Another output of level shifter forms a pre-regulator. The pre-regulator and the followed two power drive stages form a dual output low noise LDO regulator, which provides supply for the analog and digital module. The circuit parameters of the pipelined interpolating are optimized to achieve high speed, low voltage and low power. Simulated results show the designed A/D converter has the advantages of high speed, low power and large operating volateg range.
本文首先实现了一种高速、低功耗的流水插值A/D转换器,分析了并指出了该A/D转换器输出特性受电源变化影响比较大的缺点。在该流水插值A/D转换器中引入了片上的LDO稳压器,以改善其电源抑制,并对应用在该流水插值A/D转换器中的带隙基准源和LDO稳压器等相关电路技术进行了研究。本论文主要包括以下几个方面内容:
实现了一种流水插值的A/D转换器。该A/D转换器应用三级流水的斩波反相放大器、电容插值结构和预平衡的比较器,以实现高速、低功耗。给出了时钟产生电路和输出编码电路等数字电路结构,对该流水插值A/D转换器进行了投片测试。分析了电源噪声对该A/D转换器性能的影响,给出了低电源电压下该流水插值A/D转换器的性能仿真结果。
研究了低压曲率校正带隙基准源设计技术。基于温度相关电阻比技术,提出了分段非线性曲率校正电流产生电路。在低温度段,该校正电流为零,中温段与温度成指数关系,高温段与温度的平方成正比。将该非线性曲率校正电流应用在了一个低压电流模式带隙基准源中,设计了一个1V电压、低温度系数曲率校正带隙基准源。将非线性曲率校正电流产生电路应用在了一个电压模式带隙基准源中,实现了一个带有负反馈的曲率校正带隙基准源。其主要特点是曲率校正电流产生电路在输出回路上形成了一个负反馈,只用一个电路模块实现了降低温度系数、改善基准源的电源抑制与线性调整率等功能。该负反馈电路结构简单,需要面积和功耗非常小。实验结果验证了设计思想的正确性。
研究了片上应用的低噪声LDO稳压器实现技术。简单分析了应用预稳压电路的LDO稳压器线性调整率和负载调整率与电路参数的关系,实现了一种片上应用的CMOS低噪声、高电源抑制LDO稳压器。提出了一种可以应用于LDO稳压器和带隙基准源之间的共享预稳压电路,该共享预稳压电路基于电流负反馈原理设计,可以显著降低其基准源性能随工艺阈值电压变化的敏感度,提高参考源的电源抑制,降低LDO稳压器的输出噪声。该共享的预稳压电路结构已经申请发明专利。
设计了一种应用片上LDO稳压器的高速、低功耗A/D转换器。该A/D转换器包括参考电压产生电路、低噪声LDO稳压器和流水插值A/D转换器三个模块。应用1V曲率校正带隙基准源产生基准电压,这个基准电压经过电平移位电路和缓冲电路为A/D转换器提供高精度的顶部和底部参考电压。电平移位电路的另一路输出形成了一个预稳压电路,预稳压电路与其后的两个功率驱动电路形成了一个低噪声、双路输出LDO稳压器。这个双路输出的LDO稳压器为A/D转换器提供模拟和数字的电源电压。对流水放大器的电路参数进行了优化,以降低噪声改善信噪比,在低压下实现高速低功耗。仿真结果表明该应用LDO稳压器的A/D转换器具有工作电压范围大、功耗低等优点。
With the rapid development of CMOS process, more and more singnal processing is processed in digital domain to achieve high speed and low power with low cost. While most of the signal in our reality world is anglog, analog-to-digital (A/D) converters are required to tansform analog signal into digital signal for processing. The speed and power have become the key factors to evaluate its performance, which are important factors to determine whether they can be used in communication network and portable video equipment.
A high speed low power pipelined interpolating A/D converter is implemented; the disadvantage of its performance easily affected by the supply variation is analyzed and given. In order to improve its power supply rejection, an on-chip LDO regulator is applied in the high speed, low power pipelined interpolating A/D converter. The related techniques of bandgap refereance and LDO regulator applied in the pipelined interpolating A/D converter are investigated. The thesis includes the following aspects:
A high speed pipelined interpolating A/D converter is implemented. A three-stage pipeline chopper inverter phase amplifier, capacitive interpolation and pre-equalized comparator are utilized to achieve high speed and low power. The clock generator and output encode circuit is given. The pipeined interpolating A/D converter is fabricated and measured. The affection of supply ripple on the performance of the A/D converter is analyzed and the simulaton result of the A/D convter in low voltage is given.
Low voltage curvature corrected bandgap references are designed. A piecewise nonlinear curvature corrected current generator based on temperature related ratio is proposed. In the low, middle and high temperature range, the curvature-corrected current is zero, proportion to expontial and squared with temperature respectively. The nonlinear curvature corrteded current generator is utilized in a low voltage current-mode bandgap reference to design a 1V curvature corrected bandgap reference with low temperature coefficient. Applying the nonlinear curvature corrected current generator in a voltage-mode bandgap reference, a curvature corrtected bandgap reference with negative is designed and implemented. The distinguish feature is a negative is formed between the curvature corrected current generator and the output circuit. The two objects of decreaseing the temperature coefficient, improveing power supply rejection (PSR) and line regulation are achieved with only one circuit module. The negative is simple, which needs little extra chip area and power consumption. Experiment results shows the design consideration is correct.
The implementation technique of low noise LDO regulator for on-chip application is investigated. The relation of line regulation and load regulation with circuit parameters for the LDO regulator with pre-regulator is analyzed briefly. A CMOS low noise, high PSR LDO regulators for on-chip application is implemented. A sharing pre-regulator for LDO regulator is proposed. The pre-regulator is designed based on current negative feedback, which dramatically decreases the sentivity of its bandgap reference performance with the variation of threshold, increases the PSR of its bandgap reference, and decreases the output noise of the LDO regulator. The architecture of the sharing pre-regulator is applied in an invention patent.
A high speed low power A/D converter with on-chip LDO regulatos is designed, which includes reference generator, low noise LDO regulator and a pipelined interpolating A/D converter. The 1V curvature corrected bandgap reference is utilized in the A/D converters, which is followed by a level shifter and two buffers to provide the top and bottom references for the A/D converter. Another output of level shifter forms a pre-regulator. The pre-regulator and the followed two power drive stages form a dual output low noise LDO regulator, which provides supply for the analog and digital module. The circuit parameters of the pipelined interpolating are optimized to achieve high speed, low voltage and low power. Simulated results show the designed A/D converter has the advantages of high speed, low power and large operating volateg range.
引文
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