基于动态指令集的自适应处理器的关键技术研究
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摘要
专用指令集处理器(ASIP)既继承了通用处理器(GPP)的编程灵活、上市时间短等优点,又集成了专用集成电路(ASIC)的功耗低、执行高效等特性,它的出现给系统开发、设计等不同层次的人员带来了许多益处,因此越来越受到学术界和工业界的欢迎和关注。但是,ASIP的设计实现难度较大,其中难度最大的是快速的工具链实现和验证。如何降低或避免ASIP工具链开发所带来的额外开销,是ASIP应用中一个重要的问题。
新技术领域的兴起对程序与计算提出了更严格的要求,频繁变化的用户需求使处理器执行的任务具有高度的动态性。传统的基于静态指令集设计的处理器已经无法够满足这些应用的需求。如何设计新的架构来满足用户动态变化的需求,是处理器设计中的重要问题。
本文针对上述两个问题,提出了一种基于自适应ASIP处理器(ApplicationSpecific Adaptive Processor,ASAP)的解决方案。ASAP将ASIP技术与可重构技术结合到一起,让处理器能够动态的扩展自定义指令以适应变化的应用需求;同时保证底层硬件的重构对上层软件透明,使自定义指令能够动态的映射而不改变对应用程序的接口,以重用原有工具链,从而减少开发者负担并缩短研发周期。
本文开展的主要研究工作和创新特色如下:
(1)本文首先分析研究了目前ASIP的典型开发流程,指出了其中的关键问题,然后针对其中的问题来寻找相应的解决方案。首先,针对工具链中验证难的问题,本文结合目前常见的基于体系结构描述语言(ADL)工具的设计流程,提出了一种基于ADL的指令集规范验证方法,协同验证了指令集规范,处理器模型及工具链。然后,针对工具链开发负担大和用户需求动态变化大的问题,本文提出了一个基于动态指令集的自适应处理器架构ASAP的方案,该方案能避免工具链的问题并适应用户的动态需求。
(2)本文详细分析研究了应用的特征和已有的剖析技术,结合ASAP处理器架构,设计并实现了一个可配置的硬件剖析器CHP,使之能够与微处理器低耦合的工作,并在占用较少硬件资源的情况下,正确的找出目标应用的热点路径。本文通过详尽的实验确定了剖析器各个部件中关键参数的设置。实验表明,对于适合优化的应用,CHP找出的热点路径的覆盖率都能够达到80%以上,为指令集优化工作奠定了很好的基础。
(3)本文详细分析了常见的指令集扩展技术,对其中的自定义指令生成和自定义指令选择问题进行了深入的研究。首先结合ASAP处理器架构给出了一个自定义指令生成算法,通过数据流分析、指令簇标记、子图枚举、子图合并的方法,找出了符合自定义扩展指令多约束要求的候选指令集合。实验数据表明,该算法能够高效的找出目标应用的所有非平凡自定义指令集合。然后,针对目前自定义指令选择问题中,常见的启发式算法无法找到最优解的情况,给出了一种贪心的启发式算法GreedyHeur和一种结合贪心策略和差分进化思想的ISDE算法。实验表明,GreedyHeur算法能快速的选择比原有启发式算法更优的候选指令集合,而ISDE算法在指令数目约束较强时能在较低的时间复杂度下选出性能提升值远远超过其他启发式算法的候选指令组合。
本文还分析研究了常见的可重构阵列架构。结合ASAP处理器架构,描述了一种实用的可重构阵列架构的设计与实现,然后针对这种架构,给出了一种利用硬件表格来分析指令间寄存器的生产者-消费者关系,从而实现自定义指令自动映射的方法。
Application Specific Adaptive Processors (ASIPs) combine the flexibility and competitive time-to-market of embedded processors with the computational performance and energy-efficiency of dedicated VLSI hardware implementations. As they bring several advantages to different kinds of developers, they are becoming more and more popular. But the cost of developing ASIPs is large, especially for the time consuming of provision and verification of the tool chains. The problem of eliminating tool chain related cost poses a significant challenge.
With the emergence of new technologies and varying user requirements, the requirements to processors become more and more challenging. ASIPs that designed with static instruction set are hard to meet all those requirements. So the research of brand new processor architecture is becoming more and more important.
This dissertation presents the framework of an adaptive ASIP based on dynamic instruction-set to solve the problems. The adaptive ASIP mean to avoid the tool chain problems in ASIP development and to meet the varying user requirements. It intergrates reconfigurable technology with ASIP to support dynamic instruction set extension; it also keep the application binary interface unchanged during dynamic reconfiguration of hardware, in order to reuse the toolchain.
This dissertation's key researches and contributions focus on follow aspects:
(1) ASIP toolchain problem and its soultion: we analysis the typical ASIP design flow, point out the exsiting problems, and propose two solutions. First, we introduce an ADL-based verification methodology for co-verification of tools, instruction set specification and CPU model. Second, we describe the framework of Application Specific Adaptive Processor (ASAP) to avoid the toolchain problem and meet the varying user requirements.
(2) Application characteristics and configurable profiler design: we first analysis the characteristics of application benchmarks, then design a configurable hardware profiler(CHP). CHP could work loosely with embedded processors, spot hot paths efficiently without too much hardware resources. We determine the crucial parameters with extensive experiments.Empirial experiments on path profiling show that the coverage of hot paths found by CHP are usually above 80%, providing great opptunities for instruction set optimization.
(3) Instruction set extension and candidates selection algorithm: we first propose a custom instruction set extension algorithm for ASAP, including data flow analysis, instruction clustering, sub-graph enumerating and sub-graph merging. Experiments show that the algorithm could enmuerate all the non-trival candicates efficiently. Then we analysis the existing candidate selection algorithm and propose two new algorithms: as heuristic algorithms usually omit the difference between instruction and instruction instance, we improved one existing heuristic algorithm to GreedyHeur algorithm. It calculates custom instructions' weights from their instruction instances, then select custom instruction instances with greedy strategy according to their instructions' weights. To find better custom instruction than heuristic algorithms, we introduced an algorithm (ISDE) integrating greedy strategy with differential evolution algorithm. Simple encoding and efficient fitness evaluation help ISDE find the best combination of custom instructions quickly. Experiments show that our algorithms can find better custom instruction candidates more quickly and efficiently than heuristic algorithm.
This dissertation also discusses about reconfigurable array architecture and dynamic techniques, and decribes a practical reconfigurable array architecture and its dynamic mapping mechanism based on hardware table.
新技术领域的兴起对程序与计算提出了更严格的要求,频繁变化的用户需求使处理器执行的任务具有高度的动态性。传统的基于静态指令集设计的处理器已经无法够满足这些应用的需求。如何设计新的架构来满足用户动态变化的需求,是处理器设计中的重要问题。
本文针对上述两个问题,提出了一种基于自适应ASIP处理器(ApplicationSpecific Adaptive Processor,ASAP)的解决方案。ASAP将ASIP技术与可重构技术结合到一起,让处理器能够动态的扩展自定义指令以适应变化的应用需求;同时保证底层硬件的重构对上层软件透明,使自定义指令能够动态的映射而不改变对应用程序的接口,以重用原有工具链,从而减少开发者负担并缩短研发周期。
本文开展的主要研究工作和创新特色如下:
(1)本文首先分析研究了目前ASIP的典型开发流程,指出了其中的关键问题,然后针对其中的问题来寻找相应的解决方案。首先,针对工具链中验证难的问题,本文结合目前常见的基于体系结构描述语言(ADL)工具的设计流程,提出了一种基于ADL的指令集规范验证方法,协同验证了指令集规范,处理器模型及工具链。然后,针对工具链开发负担大和用户需求动态变化大的问题,本文提出了一个基于动态指令集的自适应处理器架构ASAP的方案,该方案能避免工具链的问题并适应用户的动态需求。
(2)本文详细分析研究了应用的特征和已有的剖析技术,结合ASAP处理器架构,设计并实现了一个可配置的硬件剖析器CHP,使之能够与微处理器低耦合的工作,并在占用较少硬件资源的情况下,正确的找出目标应用的热点路径。本文通过详尽的实验确定了剖析器各个部件中关键参数的设置。实验表明,对于适合优化的应用,CHP找出的热点路径的覆盖率都能够达到80%以上,为指令集优化工作奠定了很好的基础。
(3)本文详细分析了常见的指令集扩展技术,对其中的自定义指令生成和自定义指令选择问题进行了深入的研究。首先结合ASAP处理器架构给出了一个自定义指令生成算法,通过数据流分析、指令簇标记、子图枚举、子图合并的方法,找出了符合自定义扩展指令多约束要求的候选指令集合。实验数据表明,该算法能够高效的找出目标应用的所有非平凡自定义指令集合。然后,针对目前自定义指令选择问题中,常见的启发式算法无法找到最优解的情况,给出了一种贪心的启发式算法GreedyHeur和一种结合贪心策略和差分进化思想的ISDE算法。实验表明,GreedyHeur算法能快速的选择比原有启发式算法更优的候选指令集合,而ISDE算法在指令数目约束较强时能在较低的时间复杂度下选出性能提升值远远超过其他启发式算法的候选指令组合。
本文还分析研究了常见的可重构阵列架构。结合ASAP处理器架构,描述了一种实用的可重构阵列架构的设计与实现,然后针对这种架构,给出了一种利用硬件表格来分析指令间寄存器的生产者-消费者关系,从而实现自定义指令自动映射的方法。
Application Specific Adaptive Processors (ASIPs) combine the flexibility and competitive time-to-market of embedded processors with the computational performance and energy-efficiency of dedicated VLSI hardware implementations. As they bring several advantages to different kinds of developers, they are becoming more and more popular. But the cost of developing ASIPs is large, especially for the time consuming of provision and verification of the tool chains. The problem of eliminating tool chain related cost poses a significant challenge.
With the emergence of new technologies and varying user requirements, the requirements to processors become more and more challenging. ASIPs that designed with static instruction set are hard to meet all those requirements. So the research of brand new processor architecture is becoming more and more important.
This dissertation presents the framework of an adaptive ASIP based on dynamic instruction-set to solve the problems. The adaptive ASIP mean to avoid the tool chain problems in ASIP development and to meet the varying user requirements. It intergrates reconfigurable technology with ASIP to support dynamic instruction set extension; it also keep the application binary interface unchanged during dynamic reconfiguration of hardware, in order to reuse the toolchain.
This dissertation's key researches and contributions focus on follow aspects:
(1) ASIP toolchain problem and its soultion: we analysis the typical ASIP design flow, point out the exsiting problems, and propose two solutions. First, we introduce an ADL-based verification methodology for co-verification of tools, instruction set specification and CPU model. Second, we describe the framework of Application Specific Adaptive Processor (ASAP) to avoid the toolchain problem and meet the varying user requirements.
(2) Application characteristics and configurable profiler design: we first analysis the characteristics of application benchmarks, then design a configurable hardware profiler(CHP). CHP could work loosely with embedded processors, spot hot paths efficiently without too much hardware resources. We determine the crucial parameters with extensive experiments.Empirial experiments on path profiling show that the coverage of hot paths found by CHP are usually above 80%, providing great opptunities for instruction set optimization.
(3) Instruction set extension and candidates selection algorithm: we first propose a custom instruction set extension algorithm for ASAP, including data flow analysis, instruction clustering, sub-graph enumerating and sub-graph merging. Experiments show that the algorithm could enmuerate all the non-trival candicates efficiently. Then we analysis the existing candidate selection algorithm and propose two new algorithms: as heuristic algorithms usually omit the difference between instruction and instruction instance, we improved one existing heuristic algorithm to GreedyHeur algorithm. It calculates custom instructions' weights from their instruction instances, then select custom instruction instances with greedy strategy according to their instructions' weights. To find better custom instruction than heuristic algorithms, we introduced an algorithm (ISDE) integrating greedy strategy with differential evolution algorithm. Simple encoding and efficient fitness evaluation help ISDE find the best combination of custom instructions quickly. Experiments show that our algorithms can find better custom instruction candidates more quickly and efficiently than heuristic algorithm.
This dissertation also discusses about reconfigurable array architecture and dynamic techniques, and decribes a practical reconfigurable array architecture and its dynamic mapping mechanism based on hardware table.
引文
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