DVB-C接收芯片中数据同步的设计及实现
摘要
数字高清晰度电视(Digital HDTV)作为第三代电视标准，已成为当今世界
高技术竞争的焦点，对世界的政治、经济和文化将产生巨大而深远的影响。本文
着重于有线视频广播系统(DVB-C)传输系统中符号的同步定时原理及其在专
用集成电路芯片(ASIC)上的实现。
本文第一章首先概述了高清晰度电视的发展历史，接着重点介绍了DVB-C有
线电视传输系统，并对专用集成电路(ASIC)设计的发展、将来的设计趋势等作了
概述。
第二章叙述同步定时算法的理论基础。主要讨论了基于内插思想的同步恢复
的理论；在此理论的基础上对整个内插环路做了理论分析。
第三章讲述了基于内插思想的同步环路设计。在此章中，首先是详细地讨论
了环路中各个参数的计算；接着是对各种参数和结构进行了性能仿真，并由此决
定了环路的结构。
第四章主要是结合芯片设计的流程，详细介绍了内插环路的ASIC实现，并
给出了设计过程中的一些思想和方法。
本文的主要贡献在与根据锁相环的思想，对同步内插环路做了具体的分析，
确定了环路结构、并给出了整个环路的参数计算方法。
Digital High Definition Television (HDTV) utilizes several most advanced practical technologies in the world,such as advanced compression coding technologies and audio & video technologies. It is representative of the third generation television,and will have an important influence on the lives of people in the future. This thesis deals with the algorithm of synchronization and its DVB-C (Digital Vision Broadcasting - Cable) implementation. The synchronization is used in the DVB receiver of HDTV Cable Broadcasting Transmission System.
The main contents of this thesis are at a glance:
Chapter 1 serves as an introduction to the subject. After an overview of Digital HDTV,DVB-C system is discussed in detail. EDA design method is also introduced at last.
Chapter 2 discusses the principle of synchronization. The emphasis is placed on the analysis of timing loop based on interpolation.
Chapter 3 treats the design of the timing synchronization loop. At first,it introduces the method of loop parameters,including gain of phase detecting,gain of loop filter and frequency sensitivity,then simulations are done under different structures and parameters. According to the results of simulation,loop structure is decided.
Chapter 4 illuminates the ASIC project of synchronization. In the same time,the flow of ASIC front-end design is introduced;it also lists some skills and ideas in the work.
The main contributions of this paper are proposing the algorithm and realization of synchronization in DVB-C,and calculating the technical parameters of synchronization loop.
高技术竞争的焦点，对世界的政治、经济和文化将产生巨大而深远的影响。本文
着重于有线视频广播系统(DVB-C)传输系统中符号的同步定时原理及其在专
用集成电路芯片(ASIC)上的实现。
本文第一章首先概述了高清晰度电视的发展历史，接着重点介绍了DVB-C有
线电视传输系统，并对专用集成电路(ASIC)设计的发展、将来的设计趋势等作了
概述。
第二章叙述同步定时算法的理论基础。主要讨论了基于内插思想的同步恢复
的理论；在此理论的基础上对整个内插环路做了理论分析。
第三章讲述了基于内插思想的同步环路设计。在此章中，首先是详细地讨论
了环路中各个参数的计算；接着是对各种参数和结构进行了性能仿真，并由此决
定了环路的结构。
第四章主要是结合芯片设计的流程，详细介绍了内插环路的ASIC实现，并
给出了设计过程中的一些思想和方法。
本文的主要贡献在与根据锁相环的思想，对同步内插环路做了具体的分析，
确定了环路结构、并给出了整个环路的参数计算方法。
Digital High Definition Television (HDTV) utilizes several most advanced practical technologies in the world,such as advanced compression coding technologies and audio & video technologies. It is representative of the third generation television,and will have an important influence on the lives of people in the future. This thesis deals with the algorithm of synchronization and its DVB-C (Digital Vision Broadcasting - Cable) implementation. The synchronization is used in the DVB receiver of HDTV Cable Broadcasting Transmission System.
The main contents of this thesis are at a glance:
Chapter 1 serves as an introduction to the subject. After an overview of Digital HDTV,DVB-C system is discussed in detail. EDA design method is also introduced at last.
Chapter 2 discusses the principle of synchronization. The emphasis is placed on the analysis of timing loop based on interpolation.
Chapter 3 treats the design of the timing synchronization loop. At first,it introduces the method of loop parameters,including gain of phase detecting,gain of loop filter and frequency sensitivity,then simulations are done under different structures and parameters. According to the results of simulation,loop structure is decided.
Chapter 4 illuminates the ASIC project of synchronization. In the same time,the flow of ASIC front-end design is introduced;it also lists some skills and ideas in the work.
The main contributions of this paper are proposing the algorithm and realization of synchronization in DVB-C,and calculating the technical parameters of synchronization loop.
引文
[1] F.M.Gardner, "Interpolation in digital modems--Parti: Fundamentals", IEEE Trans. Commun, vol.41, pp.502-508, Mar.1993
[2] Lars, F.M.Gardner, "Interpolation in Digital Modems--Part H: Implementation and Performance" , IEEE Trans.Commum, vol.41, June 1993
[3] F.M.Gardner, "A BPSK/QPSK timing-error detector for sampled receivers" , IEEE Trans.Commum., vol. COM-34, pp.423-429, May 1986．
[4] R.W.Schafer and L.R.Rabiner, "A digital signal processing approach to interpolation" , Proc. IEEE, v.61, pp. 692-702, June 1973．
[5] N.A.D'Andrea and M.Luise, "Design and analysis of a jittter-free clock recovery scheme for QAM systems", IEEE Trans.Commun., vol.41, pp.1296-1299, Sept.1993．
[6] N.A.D'Andrea and M.Luise, "Optimization of symbol timing recovery for QAM data demodulators" , IEEE Trans.Commun, vol.44, Mar.1996．
[7] 樊平毅、冯重熙，“全数字接收机中插值滤波器的设计--全响应线性调制信号的插 值问题”，电子科学学刊，vol．19，Mar．1997．
[8] 《SDH数字微波传输系统》，人民邮电出版社，1998． 8
[9] 《数字信号处理教程》，清华大学出版社， 1997． 1
[10] 姚庆栋等，《数字无线传输》， 浙江大学出版社， 1992． 11
[11] HIKMET SARI,SAIDMORIDI, "New Phase and Frequency Detectors for Carrier Recovery in PSK and QAM Systems", IEEE Trans Commun, vol.36,Sept,l988
[12] Georges Karam, Isabelle Jeanclaude and Hikmet Sari, "A Reduced-Complexity Frequency Detector Derived from the Maximum-Likelihood Principle", IEEE Trans Commun, vol.43, OCT, 1995
[13] Jerry Whitaker著，邱绪环，乐，徐孟侠，张风超等译。数字技术：数字电视原理 与应用；DTV：The Revolution in Electronic Imaging，电子工业出版社，2000。
[14] 张明，《Verilog HDL实用教程》，电子科技大学出版社，1999。
[15] Digital Video Broadcasting(DVB);Framing structure,channel coding and modulation for cable systems,EN 300 429 V1． 2． 1 European Broadcasting Union.April.1998．
[16] 《中国集成电路大全》编委会，专用集成电路和集成系统设计自动化设计方法，北 京：国防工业出版社，1997。
[17] Bhatnagar, Himanshu. Advanced ASIC Chip Synthesis: Using Synopsys Designer Compiler and PrimeTime, Kluwer Academic Publishers, 2000．
[18] Nekoogar, Fazard. Timing Verification of Application-Specific Integrated Circuits, Prentice Hall, 1999．
[19] “半导体集成化芯片系统基础研究科学论坛纪要”，国家自然科学基金委员会21世 纪核心科学问题论坛，2001。
[20] 姚庆栋，张朝阳，刘鹏等，“系统集成芯片综述”，计算机自动测量与控制， 2000年第3期。
[21] Jason cong，“纳米工艺IC设计的挑战和机遇“，集成电路设计，1998年第4期。
[22] Jim Turley. "CPU and DSP cores vie for ASIC designer's attention", Computer Design, pp.75-86, Jan. 1997．
c[23] 袁寿财，朱长纯，“集成电路技术：过去与未来”，半导体杂志，1998． 23(2) ，
[24] Bejoy G Oommann，“系统级芯片的内置式洲试新技术“，CEO of Genesys Testware Inc，1999。
[25] 段新东，“深亚微米集成电路设计方法学与EDA技术”，集成电路设计，1997年第4 期。
[26] 樊昌信等，《通信原理》，国防工业出版社，1995。
[27] 闻懋生等，《信息传输基础》，西安交通大学出版社，1993。
[28] AJ.Viterbi and J.K.Omura,Principles of digital communication and coding, New York:McGraw-Hill, 1979．
[29] GA.Sai-Halasz, "Performance Trends in High-End Processor". Proc of IEEE,83(1) , 20-36,1995．
[30] G.C.Clark,Jr.and J.B.Cain, Error-Correction Coding for Digital Communication, Plenum Press. New York 1981．
[31] ATSC Digital Television Standard, Advanced Television Systems Committee, DOC. A/53, Sep. 16, 1995．
[32] Proakis,J.G.,Digital Communications.Third Edition.New York:McGraw-Hill, 1995: pp.468-470．
[33] 杨之廉、申明，超大规模集成电路设计方法学导论，清华大学出版社，1999。
[34] V.Agrawal and S.Seth,Eds.TestGeneration for VLSI Chips,IEEE Computer Society Press, 1988．
[35] Jan M.Rabaey, Digital Integrated Circuits: A Design Perspective, 1996．
[36] Warren Savage, "Developments Process for Creating Reusable Designs",DesignCon'98 Conference, Santa Clara, California, USA 1998．
[37] 何小艇，数字电路，浙江大学出版社，1997
[38] 张厥盛，郑继禹，万心平，锁相技术，西安电子科技大学出版社，2000． 1
[39] Alan V．Oppenheim，Signals and Systems，西安交通大学出版社，刘树棠译，2001． 5
[40] 张贤达，现代信号处理， 清华大学出版社，1999． 7
[2] Lars, F.M.Gardner, "Interpolation in Digital Modems--Part H: Implementation and Performance" , IEEE Trans.Commum, vol.41, June 1993
[3] F.M.Gardner, "A BPSK/QPSK timing-error detector for sampled receivers" , IEEE Trans.Commum., vol. COM-34, pp.423-429, May 1986．
[4] R.W.Schafer and L.R.Rabiner, "A digital signal processing approach to interpolation" , Proc. IEEE, v.61, pp. 692-702, June 1973．
[5] N.A.D'Andrea and M.Luise, "Design and analysis of a jittter-free clock recovery scheme for QAM systems", IEEE Trans.Commun., vol.41, pp.1296-1299, Sept.1993．
[6] N.A.D'Andrea and M.Luise, "Optimization of symbol timing recovery for QAM data demodulators" , IEEE Trans.Commun, vol.44, Mar.1996．
[7] 樊平毅、冯重熙，“全数字接收机中插值滤波器的设计--全响应线性调制信号的插 值问题”，电子科学学刊，vol．19，Mar．1997．
[8] 《SDH数字微波传输系统》，人民邮电出版社，1998． 8
[9] 《数字信号处理教程》，清华大学出版社， 1997． 1
[10] 姚庆栋等，《数字无线传输》， 浙江大学出版社， 1992． 11
[11] HIKMET SARI,SAIDMORIDI, "New Phase and Frequency Detectors for Carrier Recovery in PSK and QAM Systems", IEEE Trans Commun, vol.36,Sept,l988
[12] Georges Karam, Isabelle Jeanclaude and Hikmet Sari, "A Reduced-Complexity Frequency Detector Derived from the Maximum-Likelihood Principle", IEEE Trans Commun, vol.43, OCT, 1995
[13] Jerry Whitaker著，邱绪环，乐，徐孟侠，张风超等译。数字技术：数字电视原理 与应用；DTV：The Revolution in Electronic Imaging，电子工业出版社，2000。
[14] 张明，《Verilog HDL实用教程》，电子科技大学出版社，1999。
[15] Digital Video Broadcasting(DVB);Framing structure,channel coding and modulation for cable systems,EN 300 429 V1． 2． 1 European Broadcasting Union.April.1998．
[16] 《中国集成电路大全》编委会，专用集成电路和集成系统设计自动化设计方法，北 京：国防工业出版社，1997。
[17] Bhatnagar, Himanshu. Advanced ASIC Chip Synthesis: Using Synopsys Designer Compiler and PrimeTime, Kluwer Academic Publishers, 2000．
[18] Nekoogar, Fazard. Timing Verification of Application-Specific Integrated Circuits, Prentice Hall, 1999．
[19] “半导体集成化芯片系统基础研究科学论坛纪要”，国家自然科学基金委员会21世 纪核心科学问题论坛，2001。
[20] 姚庆栋，张朝阳，刘鹏等，“系统集成芯片综述”，计算机自动测量与控制， 2000年第3期。
[21] Jason cong，“纳米工艺IC设计的挑战和机遇“，集成电路设计，1998年第4期。
[22] Jim Turley. "CPU and DSP cores vie for ASIC designer's attention", Computer Design, pp.75-86, Jan. 1997．
c[23] 袁寿财，朱长纯，“集成电路技术：过去与未来”，半导体杂志，1998． 23(2) ，
[24] Bejoy G Oommann，“系统级芯片的内置式洲试新技术“，CEO of Genesys Testware Inc，1999。
[25] 段新东，“深亚微米集成电路设计方法学与EDA技术”，集成电路设计，1997年第4 期。
[26] 樊昌信等，《通信原理》，国防工业出版社，1995。
[27] 闻懋生等，《信息传输基础》，西安交通大学出版社，1993。
[28] AJ.Viterbi and J.K.Omura,Principles of digital communication and coding, New York:McGraw-Hill, 1979．
[29] GA.Sai-Halasz, "Performance Trends in High-End Processor". Proc of IEEE,83(1) , 20-36,1995．
[30] G.C.Clark,Jr.and J.B.Cain, Error-Correction Coding for Digital Communication, Plenum Press. New York 1981．
[31] ATSC Digital Television Standard, Advanced Television Systems Committee, DOC. A/53, Sep. 16, 1995．
[32] Proakis,J.G.,Digital Communications.Third Edition.New York:McGraw-Hill, 1995: pp.468-470．
[33] 杨之廉、申明，超大规模集成电路设计方法学导论，清华大学出版社，1999。
[34] V.Agrawal and S.Seth,Eds.TestGeneration for VLSI Chips,IEEE Computer Society Press, 1988．
[35] Jan M.Rabaey, Digital Integrated Circuits: A Design Perspective, 1996．
[36] Warren Savage, "Developments Process for Creating Reusable Designs",DesignCon'98 Conference, Santa Clara, California, USA 1998．
[37] 何小艇，数字电路，浙江大学出版社，1997
[38] 张厥盛，郑继禹，万心平，锁相技术，西安电子科技大学出版社，2000． 1
[39] Alan V．Oppenheim，Signals and Systems，西安交通大学出版社，刘树棠译，2001． 5
[40] 张贤达，现代信号处理， 清华大学出版社，1999． 7