基于CMOS工艺的高速CAN总线收发器的设计与研究
摘要
CAN总线属于现场总线,由于其良好的性能及独特的设计,其应用范围已由最开始的汽车行业,迅速地向其它众多的领域拓展。CAN总线日益广泛的应用造就了其接口器件的巨大市场,因而,积极设计、开发出具有自主知识产权的CAN总线收发器在我国具有巨大的社会和经济意义。
本文设计了一种满足ISO11898标准,基于标准N阱CMOS工艺的高速CAN总线收发器。设计的收发器主要由驱动电路、输出级电路、斜率控制电路、带隙基准、热保护电路和接收电路等模块构成,文中采用了Hspice对各个模块电路进行了仿真。芯片中利用可变微电流源充放电的原理,能够通过外部引脚连续地调节收发器输出信号的压摆率,以应用于不同的工作模式和速度下;文中的带隙基准采用了自偏置共源共栅结构,具有很小的温度系数和较好的电源抑制比,既能为收发器提供稳定的直流偏置,又确保了过热保护电路在关断阈值点的准确性;设计中还考虑到了发送电路模块的过压保护、短路保护,带隙基准和过热保护电路对温度、电源和工艺参数的无关性,接收电路的热稳定性等,增强了整个系统的稳定性和可靠性。
经过用Hspice仿真结果表明,收发器的性能和功能都基本都达到了预定目标,部分模块甚至超过了原定的参数。
CAN bus is a popular field bus, and it is one of the serial communication networks, which supports the distributed controlling and real time controlling system. Now its application spreads rapidly from the automobile industry initially to automation, aerospace, marine, machinery industry, robotics, CNC machine tools, medical equipment, sensors and other fields. CAN bus ICs have formed a huge market. It is monopolized by foreign multinational semiconductor companies.There are very few domestic papers published on CAN bus chip design. Thus, it is very significant for us to develop our own CAN bus transceiver with independent intellectual property. In this paper, a high-speed CAN transceiver fully compatible with the ISO11898 standard based on standard N-well CMOS process is achieved.
According to the ISO11898 standard and CAN2.0 protocol, the block diagram of the CAN transceiver is shaped firstly. It includes Driver Control Circuit, Output Circuit, Slope Control Circuit, Bandgap Reference, Thermal Protection Circuit and Receiver Circuit. Each module and the whole circuit are simulated by Hspice using CSMC 0.5μm N-well CMOS process. The results show that, the operating parameters of the chip are fully compatible with the ISO11898 standard. Its performance and functionality reach the intended objectives, and some modules even exceed the original parameters.
Compared to most of the CAN transceiver chips fabricated by bipolar or BiCMOS process in the market, the transceiver in this paper is designed based on standard N-well CMOS process is not only an innovation, but also a useful experiment. Low cost CMOS process is the main trend in low voltage-low power consumption design.
In the transmitter part, a chain of cascaded inverters is used to drive two large size complementary MOSFETs. The total propagation delay of the driving circuit is approximately 5 ns, and the biggest drive current is 420 mA. Coupled with two gate resistors, the output waveform on the bus is symmetrical without spikes. In dominant state, the differential voltage on the bus is 2.6V (CANH=3.75V, CANL=1.15V).In recessive state, the differential voltage on the bus is 0V (CANH=CANL=2.5V). This not only meets the requirements of a high-speed operation, but also ensures sufficient drive capacity to the bus.
The slope control circuit is realized by four variable micro current sources, which can control the gate capacitances of the output MOSFETs to charge or discharge.The slew rate of output signal could be adjusted by external pin, so it is very convenient to be used in different transfer rate and mode. Chip manufacturer just need to make very simple changes to introduce several models of different chips according to the market demands.
This paper introduces a voltage bandgap reference circuit which uses a self-bias cascoded current mirror. This structure uses tow resistors to replace bias circuit. The output voltage range is wider. With a very small temperature coefficient and an excellent ability of power rejection, it could provide a stable DC bias for the transceiver and ensure an accurate shutdown threshold point for the thermal protection circuit. Double BE junctions are used to enhance the thermal sensitivity of the thermal protection circuit. The thermal oscillation is solved effectively by a positive feedback.
In the receiver part,a 0.4V hysteresis voltage comparator eliminates the differential mode noise interference effectively. When in the dominant state (CANH-CANL> 0.9V), the receiver shifts to a low logic voltage. When in a recessive state (CANH-CANL <0.5V), the receiver shifts to a high logic voltage.
Several harsh operating conditions are also took into account, such as over-voltage protection, short circuit protection, thermal protection and the thermal stability of the receiver circuit. The output waveform of the transmitter has very high symmetry, which reduces greatly its external electromagnetic radiation and brings the chip high stability and reliability.
本文设计了一种满足ISO11898标准,基于标准N阱CMOS工艺的高速CAN总线收发器。设计的收发器主要由驱动电路、输出级电路、斜率控制电路、带隙基准、热保护电路和接收电路等模块构成,文中采用了Hspice对各个模块电路进行了仿真。芯片中利用可变微电流源充放电的原理,能够通过外部引脚连续地调节收发器输出信号的压摆率,以应用于不同的工作模式和速度下;文中的带隙基准采用了自偏置共源共栅结构,具有很小的温度系数和较好的电源抑制比,既能为收发器提供稳定的直流偏置,又确保了过热保护电路在关断阈值点的准确性;设计中还考虑到了发送电路模块的过压保护、短路保护,带隙基准和过热保护电路对温度、电源和工艺参数的无关性,接收电路的热稳定性等,增强了整个系统的稳定性和可靠性。
经过用Hspice仿真结果表明,收发器的性能和功能都基本都达到了预定目标,部分模块甚至超过了原定的参数。
CAN bus is a popular field bus, and it is one of the serial communication networks, which supports the distributed controlling and real time controlling system. Now its application spreads rapidly from the automobile industry initially to automation, aerospace, marine, machinery industry, robotics, CNC machine tools, medical equipment, sensors and other fields. CAN bus ICs have formed a huge market. It is monopolized by foreign multinational semiconductor companies.There are very few domestic papers published on CAN bus chip design. Thus, it is very significant for us to develop our own CAN bus transceiver with independent intellectual property. In this paper, a high-speed CAN transceiver fully compatible with the ISO11898 standard based on standard N-well CMOS process is achieved.
According to the ISO11898 standard and CAN2.0 protocol, the block diagram of the CAN transceiver is shaped firstly. It includes Driver Control Circuit, Output Circuit, Slope Control Circuit, Bandgap Reference, Thermal Protection Circuit and Receiver Circuit. Each module and the whole circuit are simulated by Hspice using CSMC 0.5μm N-well CMOS process. The results show that, the operating parameters of the chip are fully compatible with the ISO11898 standard. Its performance and functionality reach the intended objectives, and some modules even exceed the original parameters.
Compared to most of the CAN transceiver chips fabricated by bipolar or BiCMOS process in the market, the transceiver in this paper is designed based on standard N-well CMOS process is not only an innovation, but also a useful experiment. Low cost CMOS process is the main trend in low voltage-low power consumption design.
In the transmitter part, a chain of cascaded inverters is used to drive two large size complementary MOSFETs. The total propagation delay of the driving circuit is approximately 5 ns, and the biggest drive current is 420 mA. Coupled with two gate resistors, the output waveform on the bus is symmetrical without spikes. In dominant state, the differential voltage on the bus is 2.6V (CANH=3.75V, CANL=1.15V).In recessive state, the differential voltage on the bus is 0V (CANH=CANL=2.5V). This not only meets the requirements of a high-speed operation, but also ensures sufficient drive capacity to the bus.
The slope control circuit is realized by four variable micro current sources, which can control the gate capacitances of the output MOSFETs to charge or discharge.The slew rate of output signal could be adjusted by external pin, so it is very convenient to be used in different transfer rate and mode. Chip manufacturer just need to make very simple changes to introduce several models of different chips according to the market demands.
This paper introduces a voltage bandgap reference circuit which uses a self-bias cascoded current mirror. This structure uses tow resistors to replace bias circuit. The output voltage range is wider. With a very small temperature coefficient and an excellent ability of power rejection, it could provide a stable DC bias for the transceiver and ensure an accurate shutdown threshold point for the thermal protection circuit. Double BE junctions are used to enhance the thermal sensitivity of the thermal protection circuit. The thermal oscillation is solved effectively by a positive feedback.
In the receiver part,a 0.4V hysteresis voltage comparator eliminates the differential mode noise interference effectively. When in the dominant state (CANH-CANL> 0.9V), the receiver shifts to a low logic voltage. When in a recessive state (CANH-CANL <0.5V), the receiver shifts to a high logic voltage.
Several harsh operating conditions are also took into account, such as over-voltage protection, short circuit protection, thermal protection and the thermal stability of the receiver circuit. The output waveform of the transmitter has very high symmetry, which reduces greatly its external electromagnetic radiation and brings the chip high stability and reliability.
引文
[1] TJA1050高速CAN收发器数据手册,Philips,2000.05.
[2] MCP2551 高速 CAN 收发器数据手册,Microchip,2005.
[3] 邬宽明 编著 《CAN 总线原理和应用系统设计》 北京航空航天大学 出版社,2002.
[4] 王焕硕士论文,基于 FPGA 的 CAN 总线控制器芯片及其测试系统研究,吉林大学,2007.
[5] CAN-bus 规范 V2.0 版本 http://www.zlgmcu.com.
[6] 夏继强 邢春香 工业现场总线技术的新进展 北京航空航天大学学报第30卷第4期,358-362页,2004年4月.
[7] TJA1050 CAN高速收发器应用指南,http://www.zlgmcu.com.
[8] Sagar Digwalekar, Master thesis, “CONTROLLER AREA NETWORK INTERFACE DESIGN”, Texas Tech University.
[9] Armando Gomes,Edevaldo Pereira S. Júnior and Ivan Nascimento,“EMC-EMI Optimized High Speed CAN Line Driver”,Integrated Circuits and Systems Design,Sept. 2005.
[10] Andrew Rusek and Barbara Oakley,“Computer Modeling of CAN Automotive Bus Transceivers”,Oakland University.
[11] Ricky D.Jordanger and Anton M.Antonsen,“Controller area network transceiver having capacitive balancing circuit for improved receiver common-mode rejection” United States Patent 7,113,759 B2,2006.
[12] Timothy P.Pauletti and John H.Carpenter, “Common mode stabilization circuit for differential bus networks” ,United States Patent 7,242,227B2,2007.
[13] 应建华,郭艳,RS-485全工收发器芯片的设计,华中科技大学学报,第34卷第10期,8-10页,2006.10.
[14] Ross E.Teggatz and David J.Baldwin,“Driver for controller area network”,United States Paten 6,324,044 B1,2001.
[15] John P.Uyemura,周润德译,超大规模集成电路与系统导论,北京:电子工业出版社,2006.
[16] Stephan Bolz,“Protective circuit for protection against over-voltage for a CAN bus transceiver” ,United States Patent 7,218,497 B2,2007.
[17] Jiri Langer,“Circuit with overvoltage protection” ,United States Patent 5,966,038,1999.
[18] Hao-Ping Hong,Jiin-Chuan Wu,“A Reverse-Voltage Protection Circuit for MOSFET Power Switches”,IEEE Journal of Solid-State Circuits, Volume 36,Issue 1,2001,Page(s):152 – 155.
[19] Bruun,E,“Reverse-voltage protection methods for CMOS circuits”, IEEE Journal of Solid-State Circuits, Volume 24,Issue 1,1989, Page(s):100 – 103.
[20] Jeffrey B.Davis,“Overvoltage tolerant output buffer circuit” ,United States Patent 5,381,061,1995.
[21] Seiichi Watarai,“Output circuit with overvoltage protection” ,United States Patent 5,864,245,1999.
[22] C.S.Choy,M.H.Ku,C.F.Chan,“A low power-noise output driver with an adaptive characteristicapplicable to a wide range of loading conditions”, IEEE Journal of Solid-State Circuits, Volume 32,Issue 6,Jun 1997, Page(s):913 – 917.
[23] K.Furutani,H.Miyamoto,Y.Morooka,M.Suwa,H.Ozaki,“An adjustable output driver with a self-recovering Vpp generator for a 4M×16 DRAM”, IEEE Journal of Solid-State Circuits, Volume 29,Issue 3, 1994 Page(s):308 – 310.
[24] 奚剑雄,硕士论文,高性能收发器的研究与设计,浙江大学.
[25] Leung K,“Controlled slew rate output buffer”,Custom Integrated Circuits Conference,1998.
[26] F.Garcia P.Coll and D.Anvergne,“Design of a slew rate controlled output buffer”,ASIC Conference 1998. Proceedings. Eleventh Annual IEEE International.
[27] 刘正,游轶雄,王健,CMOS线驱动器输出信号压摆率控制的研究,微电子学,第33卷第4期,276-279页,2003.08.
[28] 黎海明,硕士论文,高性能CMOS带隙电压基准源的研究与设计,电子科技大学.
[29] 张昊,硕士论文,基准电压源和比较器的设计与实现,哈尔滨工业大学.
[30] 闫新强,张玉明,林智,CMOS带隙基准电压源的设计,电子元器件应用,第9卷第8期,54-56页,2007.08.
[31] 冯勇建,胡洪平,一种低功耗CMOS 带隙基准电压源的实现,微电子学,37卷第2期,2007.04,231-233.
[32] 毕查德.拉扎维著,陈贵灿 程军等译,模拟CMOS集成电路设计,西安交通大学出版社,2003.
[33] H.Banba et al..A CMOS Bandgap Reference Circuit with Sub-1-V Operation. IEEE Journal of Solid-State Circuits, Volume 34,Issue5,1999 ,Page(s):670 – 674.
[34] T.Books and A.L.Westwisk, A Low-Power Differential CMOS Bandgap Reference, ISSCC Dig.of Tec.Papers,pp.248-249,1994.
[35] 贾宏,硕士论文,电子镇流器驱动控制芯片中部分子电路的设计,电子科技大学.
[36] 刘振丰, 冯全源,一种BiCMOS过热保护电路,微电子学,第35卷第6期,655-657页,2005.12.
[37] 潘飞蹊,俞铁刚,郭超,陈卫东,一种高精度带隙基准源和过温保护电路,微电子学,第 35 卷第 2 期,192-195 页,2005.04.
[38] 石伟韬,蒋国平,一种高稳定低功耗CMOS 过热保护电路的设计,电子器件,第29卷第2期,330-334页,2006.06.
[39] Narasimhan R.Trichy and Wayne Tien-Feng Chen,“High speed controller area network receiver having improved EMI immunity” United States Patent 2006/0160511 A1,2006.
[40] Wei-Shang Chu and K.Wayne Current,“A CMOS Voltage Comparator with Rail-to-Rail Input-Range”,Analog Integrated Circuits and Signal Processing (1999),145-149,1999.
[41] Jeannie Han Kosiec,“CMOS comparator output circuit with high gain and hysteresis”,United States Patent,1999.
[42] Joseph E.Varrientos and Edgar Sanchez-Sinencio,“A 4-D chaotic oscillator based on a differential hysteresis comparator”,Fundamental Theory and Applications,Volume 45,Issue 1,Jan 1998 ,Page(s):3 – 10.
[43] 幸萌萌,马灵芝,RS-485接口芯片中的迟滞比较器的设计,现代电子技术,48-50页,2008年第2期.
[44] Phillip E A,Douglas R H,冯军,李智群译,CMOS模拟集成电路设计,北京:电子工业出版社,2005.
[45] 陈贵灿,CMOS集成电路设计,西安交通大学出版社,2002.
[2] MCP2551 高速 CAN 收发器数据手册,Microchip,2005.
[3] 邬宽明 编著 《CAN 总线原理和应用系统设计》 北京航空航天大学 出版社,2002.
[4] 王焕硕士论文,基于 FPGA 的 CAN 总线控制器芯片及其测试系统研究,吉林大学,2007.
[5] CAN-bus 规范 V2.0 版本 http://www.zlgmcu.com.
[6] 夏继强 邢春香 工业现场总线技术的新进展 北京航空航天大学学报第30卷第4期,358-362页,2004年4月.
[7] TJA1050 CAN高速收发器应用指南,http://www.zlgmcu.com.
[8] Sagar Digwalekar, Master thesis, “CONTROLLER AREA NETWORK INTERFACE DESIGN”, Texas Tech University.
[9] Armando Gomes,Edevaldo Pereira S. Júnior and Ivan Nascimento,“EMC-EMI Optimized High Speed CAN Line Driver”,Integrated Circuits and Systems Design,Sept. 2005.
[10] Andrew Rusek and Barbara Oakley,“Computer Modeling of CAN Automotive Bus Transceivers”,Oakland University.
[11] Ricky D.Jordanger and Anton M.Antonsen,“Controller area network transceiver having capacitive balancing circuit for improved receiver common-mode rejection” United States Patent 7,113,759 B2,2006.
[12] Timothy P.Pauletti and John H.Carpenter, “Common mode stabilization circuit for differential bus networks” ,United States Patent 7,242,227B2,2007.
[13] 应建华,郭艳,RS-485全工收发器芯片的设计,华中科技大学学报,第34卷第10期,8-10页,2006.10.
[14] Ross E.Teggatz and David J.Baldwin,“Driver for controller area network”,United States Paten 6,324,044 B1,2001.
[15] John P.Uyemura,周润德译,超大规模集成电路与系统导论,北京:电子工业出版社,2006.
[16] Stephan Bolz,“Protective circuit for protection against over-voltage for a CAN bus transceiver” ,United States Patent 7,218,497 B2,2007.
[17] Jiri Langer,“Circuit with overvoltage protection” ,United States Patent 5,966,038,1999.
[18] Hao-Ping Hong,Jiin-Chuan Wu,“A Reverse-Voltage Protection Circuit for MOSFET Power Switches”,IEEE Journal of Solid-State Circuits, Volume 36,Issue 1,2001,Page(s):152 – 155.
[19] Bruun,E,“Reverse-voltage protection methods for CMOS circuits”, IEEE Journal of Solid-State Circuits, Volume 24,Issue 1,1989, Page(s):100 – 103.
[20] Jeffrey B.Davis,“Overvoltage tolerant output buffer circuit” ,United States Patent 5,381,061,1995.
[21] Seiichi Watarai,“Output circuit with overvoltage protection” ,United States Patent 5,864,245,1999.
[22] C.S.Choy,M.H.Ku,C.F.Chan,“A low power-noise output driver with an adaptive characteristicapplicable to a wide range of loading conditions”, IEEE Journal of Solid-State Circuits, Volume 32,Issue 6,Jun 1997, Page(s):913 – 917.
[23] K.Furutani,H.Miyamoto,Y.Morooka,M.Suwa,H.Ozaki,“An adjustable output driver with a self-recovering Vpp generator for a 4M×16 DRAM”, IEEE Journal of Solid-State Circuits, Volume 29,Issue 3, 1994 Page(s):308 – 310.
[24] 奚剑雄,硕士论文,高性能收发器的研究与设计,浙江大学.
[25] Leung K,“Controlled slew rate output buffer”,Custom Integrated Circuits Conference,1998.
[26] F.Garcia P.Coll and D.Anvergne,“Design of a slew rate controlled output buffer”,ASIC Conference 1998. Proceedings. Eleventh Annual IEEE International.
[27] 刘正,游轶雄,王健,CMOS线驱动器输出信号压摆率控制的研究,微电子学,第33卷第4期,276-279页,2003.08.
[28] 黎海明,硕士论文,高性能CMOS带隙电压基准源的研究与设计,电子科技大学.
[29] 张昊,硕士论文,基准电压源和比较器的设计与实现,哈尔滨工业大学.
[30] 闫新强,张玉明,林智,CMOS带隙基准电压源的设计,电子元器件应用,第9卷第8期,54-56页,2007.08.
[31] 冯勇建,胡洪平,一种低功耗CMOS 带隙基准电压源的实现,微电子学,37卷第2期,2007.04,231-233.
[32] 毕查德.拉扎维著,陈贵灿 程军等译,模拟CMOS集成电路设计,西安交通大学出版社,2003.
[33] H.Banba et al..A CMOS Bandgap Reference Circuit with Sub-1-V Operation. IEEE Journal of Solid-State Circuits, Volume 34,Issue5,1999 ,Page(s):670 – 674.
[34] T.Books and A.L.Westwisk, A Low-Power Differential CMOS Bandgap Reference, ISSCC Dig.of Tec.Papers,pp.248-249,1994.
[35] 贾宏,硕士论文,电子镇流器驱动控制芯片中部分子电路的设计,电子科技大学.
[36] 刘振丰, 冯全源,一种BiCMOS过热保护电路,微电子学,第35卷第6期,655-657页,2005.12.
[37] 潘飞蹊,俞铁刚,郭超,陈卫东,一种高精度带隙基准源和过温保护电路,微电子学,第 35 卷第 2 期,192-195 页,2005.04.
[38] 石伟韬,蒋国平,一种高稳定低功耗CMOS 过热保护电路的设计,电子器件,第29卷第2期,330-334页,2006.06.
[39] Narasimhan R.Trichy and Wayne Tien-Feng Chen,“High speed controller area network receiver having improved EMI immunity” United States Patent 2006/0160511 A1,2006.
[40] Wei-Shang Chu and K.Wayne Current,“A CMOS Voltage Comparator with Rail-to-Rail Input-Range”,Analog Integrated Circuits and Signal Processing (1999),145-149,1999.
[41] Jeannie Han Kosiec,“CMOS comparator output circuit with high gain and hysteresis”,United States Patent,1999.
[42] Joseph E.Varrientos and Edgar Sanchez-Sinencio,“A 4-D chaotic oscillator based on a differential hysteresis comparator”,Fundamental Theory and Applications,Volume 45,Issue 1,Jan 1998 ,Page(s):3 – 10.
[43] 幸萌萌,马灵芝,RS-485接口芯片中的迟滞比较器的设计,现代电子技术,48-50页,2008年第2期.
[44] Phillip E A,Douglas R H,冯军,李智群译,CMOS模拟集成电路设计,北京:电子工业出版社,2005.
[45] 陈贵灿,CMOS集成电路设计,西安交通大学出版社,2002.