基于两级扫描结构路径延迟故障的低功耗测试
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摘要
随着集成电路的快速发展,电路的时钟频率和密度不断上升,使得功耗问题成为电路设计和测试中的一个重要研究课题。已有的研究表明电路的功耗与电路中逻辑单元的跳变数目成正比,而测试时电路产生的跳变动作比正常工作时多得多,从而产生更多的功耗,有可能导致电路因过热而失效。降低电路的测试功耗具有重要的意义,不但可以提高芯片的可靠性,而且可以使用更小尺寸的芯片,减少手提设备的重量并延长电池的寿命。从另一方面来说,降低测试功耗,就可以增加同时测试的模块数量,或者以更高的速度进行测试,最终减少电路测试时间和测试成本。
为了降低路径延迟测试的测试功耗,本文提出了一种改进的两级扫描测试结构。所做的工作如下:根据电路结构信息对扫描触发器进行分组,同组的扫描触发器在测试生成电路中共享同一个伪原始输入;在两级扫描结构的第一级加入一个信号保持单元,使得改进的两级扫描结构能够应用于路径延迟测试;将扫描触发器划分到不同的时钟域,在测试向量的移入过程中只有很小一部分扫描触发器发生逻辑值的跳变;提出了一种新的测试施加策略,测试向量只需移入两级扫描结构的第一级,无需再移入第二级;引入了新的异或网络结构,消除了故障屏蔽效应。实验结果表明,改进的两级扫描测试结构与以往的方法相比,在保证故障覆盖率的同时,不但大幅度降低了测试功耗,最高降低了99%以上,而且测试时间和测试数据量也有明显改善。
Along with fast development of very large scale integration (VLSI) circuits, the growing transistor density and the increasing operation frequency have made power dissipation an important issue in both design and test. Previous work has pointed out power dissipation in CMOS circuits is proportional to the amount of switching that takes place, and switching activity in an integrated circuit can be much greater during test than during normal operation, then test may generate more heat and damage the chip. Minimizing power dissipation is significant in improving the reliability of chip, and reduction of power dissipation permits the use of smaller package size, this can reduce weight of portable products and prolong battery life. On the other hand, reduction of power dissipation limits the number of modules that can be tested simultaneously or the speed at which the tests can be applied, this in turn impacts test time and test cost.
In this paper, an improved two-stage scan architecture of path delay faults is proposed for low power scan testing. Scan flip-flops are grouped based on structural analysis, scan flip-flops in the same group share the same pseudo primary input in the test generation circuit; a signal hold unit is added to the first stage of the two-stage scan architecture, then two-stage architecture can be applied to path delay testing; scan flip-flops are divided into different clock domain, only a small number of them are activated when applying test vectors; a new scan apply method is proposed to reduce test time and test power, test vectors only scan in first stage, not scan in second stage any longer; a new XOR network architecture is proposed to compact test response, which avoid any aliasing faults. Experimental results demonstrate that using the improved two-stage scan architecture, not only test power reduced greatly, up to 99% mostly, but also test time and test data volume decreased evidently.
为了降低路径延迟测试的测试功耗,本文提出了一种改进的两级扫描测试结构。所做的工作如下:根据电路结构信息对扫描触发器进行分组,同组的扫描触发器在测试生成电路中共享同一个伪原始输入;在两级扫描结构的第一级加入一个信号保持单元,使得改进的两级扫描结构能够应用于路径延迟测试;将扫描触发器划分到不同的时钟域,在测试向量的移入过程中只有很小一部分扫描触发器发生逻辑值的跳变;提出了一种新的测试施加策略,测试向量只需移入两级扫描结构的第一级,无需再移入第二级;引入了新的异或网络结构,消除了故障屏蔽效应。实验结果表明,改进的两级扫描测试结构与以往的方法相比,在保证故障覆盖率的同时,不但大幅度降低了测试功耗,最高降低了99%以上,而且测试时间和测试数据量也有明显改善。
Along with fast development of very large scale integration (VLSI) circuits, the growing transistor density and the increasing operation frequency have made power dissipation an important issue in both design and test. Previous work has pointed out power dissipation in CMOS circuits is proportional to the amount of switching that takes place, and switching activity in an integrated circuit can be much greater during test than during normal operation, then test may generate more heat and damage the chip. Minimizing power dissipation is significant in improving the reliability of chip, and reduction of power dissipation permits the use of smaller package size, this can reduce weight of portable products and prolong battery life. On the other hand, reduction of power dissipation limits the number of modules that can be tested simultaneously or the speed at which the tests can be applied, this in turn impacts test time and test cost.
In this paper, an improved two-stage scan architecture of path delay faults is proposed for low power scan testing. Scan flip-flops are grouped based on structural analysis, scan flip-flops in the same group share the same pseudo primary input in the test generation circuit; a signal hold unit is added to the first stage of the two-stage scan architecture, then two-stage architecture can be applied to path delay testing; scan flip-flops are divided into different clock domain, only a small number of them are activated when applying test vectors; a new scan apply method is proposed to reduce test time and test power, test vectors only scan in first stage, not scan in second stage any longer; a new XOR network architecture is proposed to compact test response, which avoid any aliasing faults. Experimental results demonstrate that using the improved two-stage scan architecture, not only test power reduced greatly, up to 99% mostly, but also test time and test data volume decreased evidently.
引文
[1] S. Wang, S. K. Gupta, “ATPG for Heat Dissipation Minimization during Scan Testing,” Proc. of IEEE/ACM Design Automation Conference, 1997, 614-619
[2] P. Rosinger, B. M. Al-Hashimi and N. Nicolici, “Scan Architecture with Mutually Exclusive Scan Segment Activation for Shift- and Capture- Power Reduction,” IEEE Trans. Computer-Aided Design, 2004, 23(7): 1142–1153
[3] C. Small. “Shrinking Devices Put the Squeeze on System Packaging,” EDN, 1994, 39(4): .41-46
[4] N. Nicolici and B. M. Al-Hashimi, “Multiple scan chains for power minimization during test application in sequential circuits,” IEEE Transactions on Computers, 2002, 51,(6): 721–734
[5] V. Dabholkar, S. Chakravarty, I. Pomeranz, and S. M. Reddy, “Techniques for minimizing power dissipation in scan and combinational circuits during test application,” IEEE Trans. Computer-Aided Design, 1998, 17(12): 1325–1333
[6] R. Sankaralingam, R. Oruganti, and N. Touba, “Static Compaction Techniques to Control Scan Vector Power Dissipation,” Proc. of 18th IEEE VLSI Test Symp., 2000, 35-40
[7] M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI Circuits. Norwell, MA: Kluwer, 2000
[8] S. Wang, S. K. Gupta, “ATPG for Heat Dissipation Minimization during Test Application,” IEEE Transactions on Computers, 1998, 47(2): 256-262
[9] P. Goel, “An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits”, IEEE Trans. on Computers, 1981, 30(3): 145-151
[10] A. Chandra and K. Chakrabarty, “Low-Power Scan Testing and Test Data Compression for System-on-a-Chip,” IEEE Trans. Computer-Aided Design, 2002, 21(5): 597–604
[11] A. Chandra and K. Chakrabarty, “Test Data Compression and Test Resource Partitioning for System-on-a-Chip Using Frequency-Directed Run-Length (FDR) Codes,” IEEE Trans. on Comp., 2003, 52(8): 1076–1088
[12] A. Chandra and K. Chakrabarty, “Combining Low-Power Scan Testing and Test Data Compression for System-On-a-Chip,” Proc. of IEEE/ACM Design Automation Conf. (DAC), 2001, 166-169
[13] T.-C. Huang and K-J. Lee, “Reduction of Power Consumption in Scan-Based Circuits during Test Application by an Input Control Technique,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 2001, 20(7): 911-917
[14] J-J. Chen, C-K. Yang and K-J. Lee, “Test Pattern Generation and Clock Disabling for Simultaneous Test Time and Power Reduction,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 2001, 22(3): 363-370
[15] I. Bayraktaroglu and A. Orailoglu, “Concurrent Application of Compaction and Compression for Test Time and Data Volume Reduction in Scan Designs”, IEEE TCOW, 2003, 52,(11): 1480-1489
[16] T-C. Huang and K-J. Lee, “An Input Control Technique for Power Reduction in Scan Circuits During Test Application,” Proc. of IEEE 8th Asian Test Symp. (ATS '99), 1999, 315-320
[17] D. Xiang, K. W. Li, H. Fujiwara, “Design for Cost-Effective Scan Testing By Reconstructing Scan Flip-Flops” Proc. of IEEE 14th Asian Test Symp. (ATS ‘05), 2005, 243-247
[18] 李开伟,向东. 改进的扫描森林测试结构. 清华大学学报(自然科学版). 2006,46(1): 98-101
[19] 向东,李开伟. 低成本的两级扫描测试结构. 计算机学报. 2006, 29(5): 786-791
[20] D. Xiang, K.W. Li, “Localizing Test Power Consumption for Scan Testing” Journal of Donghua University (English Edition), 2005, 29(5): 37-43
[21] R. Rajsuman, System-on a-chip: Design and Test. Artech House, 2000
[22] 陈治国. 集成电路低功耗测试方法研究:[硕士学位论文]。成都:电子科技大学检测技术与自动化装置系,2004
[23] K. Roy, T. M. Mak and K. T. Cheng. Test consideration for nanometer scale CMOS circuits. VTS’03, 2003, 313- 315
[24] V. D. Agrawal, C. R. Kime, and K. K. Saluja. “A tutorial on built-in self test - part 1:Principles,” IEEE Design and Test of Computers, 1993, 10(1): 73–82
[25] V. D. Agrawal, C. R. Kime, and K. K. Saluja. “A tutorial on built-in self test - part 2:Applications,” IEEE Design and Test of Computers, 1993, 10(1): 69–77
[26] 陈明静. 面向数字系统的基于扫描的内建自测试新技术:[硕士学位论文]。北京:清华大学微电子研究所,2005
[27] A. Benso, S.Cataldo, S. Chiusano, P. Prinetto, Y. Zorrian, “HD-BIST: a Hierarchical Framework for BIST Scheduling and Diagnosis in SOCs”, Proc. of IEEE International Test Conference (ITC’99), 1999, 993-1000
[28] I. Bayraktaroglu and A. Orailoglu, “Concurrent Application of Compaction and Compression for Test Time and Data Volume Reduction in Scan Designs”, IEEE TCOW, 2003, 52,(11): 1480-1489
[29] A. R. Pandey, J. H. Patel, “Reconfiguration technique for reducing test time and test data volume in Illinois scan architecture based design”, Proc. of IEEE VLSI Test Symp., 2002, 9-15
[30] I. Bayraktaroglu, A. Orailoglu, “Concurrent application of compaction and compression for test time and test volume reduction in scan designs”, IEEE Trans. on Comp., 2003, 52(11): . 1480–1489
[31] J. Saxena, K. M. Butler, and L. Whetsel, “An Analysis of Power Reduction Techniques in Scan Testing”, Proc. of IEEE International Test Conference (ITC), 2001, 670-677
[32] K-J. Lee, T-C. Huang and J-J. Chen, “Peak-Power Reduction for Multiple-Scan Circuits during Test Application,” Proc. of IEEE 9th Asian Test Symp. (ATS ‘00), 2000, 453-458
[33] A. Chandra and K. Chakrabarty, “Test data compression for system-on-a-chip using Golomb codes,” in Proc. of IEEE VLSI Test Symp., 2000, 113–120
[34] 向东,数字系统测试及可测试性设计,北京:科学出版社,1997
[35] 杨杰. 路径延迟故障的冗余识别:[硕士学位论文]。北京:清华大学软件学院,2006
[36] R. Datta, R. Gupta, A. Sebastine and J. A. Abraham, “Tri-Scan: A Novel DFT Technique for CMOS Path Delay Fault Testing”, Proc. of IEEE International Test Conference (ITC), 2004, 1118-1127
[37] S. Adham, et al, “Preliminary Outline of the IEEE P1500 Scalable Architecture for Testing Embededded Cores”, IEEE Trans. on Comp., 1999, 400–483
[38] B. Dervisoglu and G. Strong, “Design for Testability: Using ScanPath Techniques for Path-Delay Test and Measurement”, Proc. of IEEE International Test Conference (ITC), 1991, 365-374
[39] 李开伟. 低成本、高效率的扫描测试:[硕士学位论文]。北京:清华大学软件学院,2005
[40] D. Xiang, K.W. Li, J. Sun and H. Fujiwara, “Reconfigured Scan Forest for Test Application Cost, Test data Volume, and Test Powwer Reduction” IEEE Trans. on Comp., 2007, 56(4): 557–562
[41] H. Fujiware, A. Yamamoto, “Parity scan design to reduce the cost of test application,” IEEE Trans on CAD, 1993, 12(10): 1604-1611
[42] D. Xiang, K. Chakrabarty, D. W. Hu, H. Fujiwara, “Scan Testing for Complete Coverage of Path Delay Faults with Reduced Test Data Volume, Test Application Time, and Hardware Cost,” Proc. of IEEE 16th Asian Test Symp. (ATS ‘07), 2007
[43] D. Xiang, Y. Zhao, K.W. Li, and H. Fujiwara, “Fast Fault Simulation for Path Delay Faults Based on Logic Simulation and Selected Testable Paths,” Proc. of IEEE International Test Conference (ITC), 2007
[44] D. Xiang, K.W. Li, H. Fujiwara and J. Sun, “Generating compact robust and non-robust tests for complete coverage of path delay faults based on stuck-at tests,” Proc. Of ICCD, 2007, 446–451
[2] P. Rosinger, B. M. Al-Hashimi and N. Nicolici, “Scan Architecture with Mutually Exclusive Scan Segment Activation for Shift- and Capture- Power Reduction,” IEEE Trans. Computer-Aided Design, 2004, 23(7): 1142–1153
[3] C. Small. “Shrinking Devices Put the Squeeze on System Packaging,” EDN, 1994, 39(4): .41-46
[4] N. Nicolici and B. M. Al-Hashimi, “Multiple scan chains for power minimization during test application in sequential circuits,” IEEE Transactions on Computers, 2002, 51,(6): 721–734
[5] V. Dabholkar, S. Chakravarty, I. Pomeranz, and S. M. Reddy, “Techniques for minimizing power dissipation in scan and combinational circuits during test application,” IEEE Trans. Computer-Aided Design, 1998, 17(12): 1325–1333
[6] R. Sankaralingam, R. Oruganti, and N. Touba, “Static Compaction Techniques to Control Scan Vector Power Dissipation,” Proc. of 18th IEEE VLSI Test Symp., 2000, 35-40
[7] M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI Circuits. Norwell, MA: Kluwer, 2000
[8] S. Wang, S. K. Gupta, “ATPG for Heat Dissipation Minimization during Test Application,” IEEE Transactions on Computers, 1998, 47(2): 256-262
[9] P. Goel, “An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits”, IEEE Trans. on Computers, 1981, 30(3): 145-151
[10] A. Chandra and K. Chakrabarty, “Low-Power Scan Testing and Test Data Compression for System-on-a-Chip,” IEEE Trans. Computer-Aided Design, 2002, 21(5): 597–604
[11] A. Chandra and K. Chakrabarty, “Test Data Compression and Test Resource Partitioning for System-on-a-Chip Using Frequency-Directed Run-Length (FDR) Codes,” IEEE Trans. on Comp., 2003, 52(8): 1076–1088
[12] A. Chandra and K. Chakrabarty, “Combining Low-Power Scan Testing and Test Data Compression for System-On-a-Chip,” Proc. of IEEE/ACM Design Automation Conf. (DAC), 2001, 166-169
[13] T.-C. Huang and K-J. Lee, “Reduction of Power Consumption in Scan-Based Circuits during Test Application by an Input Control Technique,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 2001, 20(7): 911-917
[14] J-J. Chen, C-K. Yang and K-J. Lee, “Test Pattern Generation and Clock Disabling for Simultaneous Test Time and Power Reduction,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 2001, 22(3): 363-370
[15] I. Bayraktaroglu and A. Orailoglu, “Concurrent Application of Compaction and Compression for Test Time and Data Volume Reduction in Scan Designs”, IEEE TCOW, 2003, 52,(11): 1480-1489
[16] T-C. Huang and K-J. Lee, “An Input Control Technique for Power Reduction in Scan Circuits During Test Application,” Proc. of IEEE 8th Asian Test Symp. (ATS '99), 1999, 315-320
[17] D. Xiang, K. W. Li, H. Fujiwara, “Design for Cost-Effective Scan Testing By Reconstructing Scan Flip-Flops” Proc. of IEEE 14th Asian Test Symp. (ATS ‘05), 2005, 243-247
[18] 李开伟,向东. 改进的扫描森林测试结构. 清华大学学报(自然科学版). 2006,46(1): 98-101
[19] 向东,李开伟. 低成本的两级扫描测试结构. 计算机学报. 2006, 29(5): 786-791
[20] D. Xiang, K.W. Li, “Localizing Test Power Consumption for Scan Testing” Journal of Donghua University (English Edition), 2005, 29(5): 37-43
[21] R. Rajsuman, System-on a-chip: Design and Test. Artech House, 2000
[22] 陈治国. 集成电路低功耗测试方法研究:[硕士学位论文]。成都:电子科技大学检测技术与自动化装置系,2004
[23] K. Roy, T. M. Mak and K. T. Cheng. Test consideration for nanometer scale CMOS circuits. VTS’03, 2003, 313- 315
[24] V. D. Agrawal, C. R. Kime, and K. K. Saluja. “A tutorial on built-in self test - part 1:Principles,” IEEE Design and Test of Computers, 1993, 10(1): 73–82
[25] V. D. Agrawal, C. R. Kime, and K. K. Saluja. “A tutorial on built-in self test - part 2:Applications,” IEEE Design and Test of Computers, 1993, 10(1): 69–77
[26] 陈明静. 面向数字系统的基于扫描的内建自测试新技术:[硕士学位论文]。北京:清华大学微电子研究所,2005
[27] A. Benso, S.Cataldo, S. Chiusano, P. Prinetto, Y. Zorrian, “HD-BIST: a Hierarchical Framework for BIST Scheduling and Diagnosis in SOCs”, Proc. of IEEE International Test Conference (ITC’99), 1999, 993-1000
[28] I. Bayraktaroglu and A. Orailoglu, “Concurrent Application of Compaction and Compression for Test Time and Data Volume Reduction in Scan Designs”, IEEE TCOW, 2003, 52,(11): 1480-1489
[29] A. R. Pandey, J. H. Patel, “Reconfiguration technique for reducing test time and test data volume in Illinois scan architecture based design”, Proc. of IEEE VLSI Test Symp., 2002, 9-15
[30] I. Bayraktaroglu, A. Orailoglu, “Concurrent application of compaction and compression for test time and test volume reduction in scan designs”, IEEE Trans. on Comp., 2003, 52(11): . 1480–1489
[31] J. Saxena, K. M. Butler, and L. Whetsel, “An Analysis of Power Reduction Techniques in Scan Testing”, Proc. of IEEE International Test Conference (ITC), 2001, 670-677
[32] K-J. Lee, T-C. Huang and J-J. Chen, “Peak-Power Reduction for Multiple-Scan Circuits during Test Application,” Proc. of IEEE 9th Asian Test Symp. (ATS ‘00), 2000, 453-458
[33] A. Chandra and K. Chakrabarty, “Test data compression for system-on-a-chip using Golomb codes,” in Proc. of IEEE VLSI Test Symp., 2000, 113–120
[34] 向东,数字系统测试及可测试性设计,北京:科学出版社,1997
[35] 杨杰. 路径延迟故障的冗余识别:[硕士学位论文]。北京:清华大学软件学院,2006
[36] R. Datta, R. Gupta, A. Sebastine and J. A. Abraham, “Tri-Scan: A Novel DFT Technique for CMOS Path Delay Fault Testing”, Proc. of IEEE International Test Conference (ITC), 2004, 1118-1127
[37] S. Adham, et al, “Preliminary Outline of the IEEE P1500 Scalable Architecture for Testing Embededded Cores”, IEEE Trans. on Comp., 1999, 400–483
[38] B. Dervisoglu and G. Strong, “Design for Testability: Using ScanPath Techniques for Path-Delay Test and Measurement”, Proc. of IEEE International Test Conference (ITC), 1991, 365-374
[39] 李开伟. 低成本、高效率的扫描测试:[硕士学位论文]。北京:清华大学软件学院,2005
[40] D. Xiang, K.W. Li, J. Sun and H. Fujiwara, “Reconfigured Scan Forest for Test Application Cost, Test data Volume, and Test Powwer Reduction” IEEE Trans. on Comp., 2007, 56(4): 557–562
[41] H. Fujiware, A. Yamamoto, “Parity scan design to reduce the cost of test application,” IEEE Trans on CAD, 1993, 12(10): 1604-1611
[42] D. Xiang, K. Chakrabarty, D. W. Hu, H. Fujiwara, “Scan Testing for Complete Coverage of Path Delay Faults with Reduced Test Data Volume, Test Application Time, and Hardware Cost,” Proc. of IEEE 16th Asian Test Symp. (ATS ‘07), 2007
[43] D. Xiang, Y. Zhao, K.W. Li, and H. Fujiwara, “Fast Fault Simulation for Path Delay Faults Based on Logic Simulation and Selected Testable Paths,” Proc. of IEEE International Test Conference (ITC), 2007
[44] D. Xiang, K.W. Li, H. Fujiwara and J. Sun, “Generating compact robust and non-robust tests for complete coverage of path delay faults based on stuck-at tests,” Proc. Of ICCD, 2007, 446–451