基于多相滤波的超宽带接收机研究及FPGA实现
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摘要
随着现代雷达技术的不断发展,电子侦察接收机面临的电磁环境日益复杂多变,发展宽带化、数字化、多功能、软件化的电子侦察接收机是一项重要的任务。数字信道化接收机具有大监视带宽、高灵敏度、大动态、高频率分辨率、高截获概率和多信号处理能力等诸多优势,是应用广泛的一类电子战接收机。本文给出了一种基于多相滤波的宽带数字信道化结构,在一定信噪比的条件下,利用该结构的信道化接收机处理ADC输出数据,检测信号、测频并给出脉冲描述字。
首先,本文在信道化基本结构基础上,推导出一种基于多相滤波的数字信道化的高效结构,分析了数字滤波器组特征,合理设计滤波器带宽和信道化抽取比,可完成监视带宽内无缝连接,并较好地抑制兔耳效应,以确保全概率接收。针对该结构进行了计算机仿真,对其性能进行了深入分析。
然后,讨论了几种常见的信号检测方法和测频方法。结合具体的硬件平台,提出一种幅度检测加双谱线测频的编码方法,可以很好地解决相邻信道间虚假信号输出问题,同时提高测频精度。
最后,研究了在单片FPGA上实现信道化接收机的方案,系统的处理带宽为1GHz,解决了高速ADC与低速信号处理器FPGA之间的矛盾,并在Xilinx的XC4VSX55芯片上实现了对两个同时到达信号的检测,实现了对脉冲流的脉冲到达时间、脉冲宽度和信号瞬时频率等参数的实时高精度测量,以脉冲描述字的形式输出。该设计是针对FPGA的硬件实现方法,其系统结构简单,测量速度快、精度高,满足对脉冲参数测量高精度、实时性的要求。
The continuous developments of modern radar technology and the consequent more complicated electromagnetic environment have made it crucial to design wideband, digital, multifunctional software electronic reconnaissance receiver. Digital channelized receiver is an EW receiver that provides wideband frequency coverage, high sensitivity and dynamic range, high intercept probability and simultaneous signal detection and fine frequency resolution. In this dissertation, a structure based on polyphase decomposition is introduced, and how to detect signal and get PDW under the conditions of certain signal to noise rate when adopting the data output of the ADC is mainly discussed.
First of all, one of the efficient architecture of digital channelized receiver based on polyphase filters is built in comparison with the basic architecture. The characteristics of polyphase filters are analyzed and the rabbit ear effect is preferably restrained as well. In order to have continuous coverage across of the IBW, adjacent channel responses are overlapped. The computer simulations experiments were done, and then the performances were analyzed deeply.
Secondly, two kinds of signal detection and frequency measurement methods are discussed. Then one simple method based on amplitude comparison and Rife method is proposed. The false outputs can be eliminated and frequency-measurement accuracy can be highly improved by using this operation.
Finally, a realization of channelized receivers based on poplyphase filtering on one FPGA chip is given in this paper. This design covers 1GHz bandwidth .This method resolves the contradiction between the high-speed ADC and low-speed digital signal processor (FPGA). The design can deal with both real-time signals and we introduce how to get the TOA, PW and IF based on Xilinx XC4VSX55. This method refers to performance on FPGA,and the system is simple, high speed and precision.
首先,本文在信道化基本结构基础上,推导出一种基于多相滤波的数字信道化的高效结构,分析了数字滤波器组特征,合理设计滤波器带宽和信道化抽取比,可完成监视带宽内无缝连接,并较好地抑制兔耳效应,以确保全概率接收。针对该结构进行了计算机仿真,对其性能进行了深入分析。
然后,讨论了几种常见的信号检测方法和测频方法。结合具体的硬件平台,提出一种幅度检测加双谱线测频的编码方法,可以很好地解决相邻信道间虚假信号输出问题,同时提高测频精度。
最后,研究了在单片FPGA上实现信道化接收机的方案,系统的处理带宽为1GHz,解决了高速ADC与低速信号处理器FPGA之间的矛盾,并在Xilinx的XC4VSX55芯片上实现了对两个同时到达信号的检测,实现了对脉冲流的脉冲到达时间、脉冲宽度和信号瞬时频率等参数的实时高精度测量,以脉冲描述字的形式输出。该设计是针对FPGA的硬件实现方法,其系统结构简单,测量速度快、精度高,满足对脉冲参数测量高精度、实时性的要求。
The continuous developments of modern radar technology and the consequent more complicated electromagnetic environment have made it crucial to design wideband, digital, multifunctional software electronic reconnaissance receiver. Digital channelized receiver is an EW receiver that provides wideband frequency coverage, high sensitivity and dynamic range, high intercept probability and simultaneous signal detection and fine frequency resolution. In this dissertation, a structure based on polyphase decomposition is introduced, and how to detect signal and get PDW under the conditions of certain signal to noise rate when adopting the data output of the ADC is mainly discussed.
First of all, one of the efficient architecture of digital channelized receiver based on polyphase filters is built in comparison with the basic architecture. The characteristics of polyphase filters are analyzed and the rabbit ear effect is preferably restrained as well. In order to have continuous coverage across of the IBW, adjacent channel responses are overlapped. The computer simulations experiments were done, and then the performances were analyzed deeply.
Secondly, two kinds of signal detection and frequency measurement methods are discussed. Then one simple method based on amplitude comparison and Rife method is proposed. The false outputs can be eliminated and frequency-measurement accuracy can be highly improved by using this operation.
Finally, a realization of channelized receivers based on poplyphase filtering on one FPGA chip is given in this paper. This design covers 1GHz bandwidth .This method resolves the contradiction between the high-speed ADC and low-speed digital signal processor (FPGA). The design can deal with both real-time signals and we introduce how to get the TOA, PW and IF based on Xilinx XC4VSX55. This method refers to performance on FPGA,and the system is simple, high speed and precision.
引文
[1] Schroer R. Electronic warfare [J]. IEEE Aerospace and Electronic Systems Magazine, July 2003, Vol.18 (7):49 ~ 54.
[2] JamesTusi.宽带数字接收机[M](杨小牛译).北京:电子工业出版社, 2002.
[3]肖庆.宽带数字侦察接收机的实现[J].电子对抗, 2003,(6): 16 ~ 20.
[4] Tsui JB, StePhens JRSr. Digital Microwave Receiver Technology [J]. IEEE Trans on Microwave Theory and Techniques, March 2002, Vol.50 (3):699 ~ 705.
[5]叶斌.对传统超外差接收机的数字化改进[J].电子对抗技术, 2001, 16(5): 11 ~ 16.
[6]殷旭东,王伟,陈曾平.压缩接收机及其在电子战中的应用[J].船舶电子对抗, 2005, 28(4): 21 ~ 24.
[7] J.Mitola. Software Radios: Survey, Critical Evaluation and Future Directions[C]. Proceedings of National Telesystem Conference, NY: Press, 1992.5.
[8] Chen C-I H, George K, McCormick W. Design and Performance Evaluation of 2.5-GSPS Digital Receiver [J]. IEEE Transactions on Instrumentation and Measurement, June 2005, vol.54 (3): 1089 ~ 1099.
[9]董晖,顾善秋.电子战接收机的发展历程及其面临的挑战[J].电子对抗, 2006, (5):43 ~ 48.
[10]殷兆伟,戴国宪.不断发展的现代电子战接收机[J].船舶电子对抗, 2002, 25(5):6 ~ 9.
[11]曹鹏,戴国宪.一种基于软件无线电的电子侦察干扰机[J].电子对抗技术, 2004, 19(6):14 ~ 18.
[12]吴伟,唐斌,张鹏.基于多相滤波高效结构的宽带DDC及其FPGA实现[J].数据采集与处理, 2004, 19(2): 210 ~214.
[13] Fred Harris, Chris Dick, Michael Rice. Digital Receivers and Transmitters Using Polyphase Filter Banks for Wireless Communications [J]. IEEE Transactions on Microwave Theory and Techniques, Vol.51 (4), April 2003: 1395 ~ 1412.
[14]杨小牛,楼才义,徐建良.软件无线电原理与应用[M].北京:电子工业出版社, 2006.
[15] Fields TW, Sharpin DL, Tsui JB. Digital channelized IFM receiver [J], IEEE MTT-S international, Vol.51 , May 1994:1667 ~ 1670.
[16] Zahirniak DR, Sharpin DL, Fields TW. A Hardware-efficient, Multirate, Digital Channelized Receiver Architecture [J]. IEEE Trans. Aerospace and Electronic Systems, 1998, 34(1):137 ~ 152.
[17]宋民,张琦,高梅国.一种大带宽高分辨力数字信道化接收机[J].电子信息对抗技术, 2006, 21(1):14 ~ 17.
[18]杨静,吕幼新.高效数字信道化IFM接收机的研究[J].电子科技大学学报, 2005, 34(4):444 ~ 447.
[19]周欣,吴瑛.基于多相滤波的宽带接收机信道化算法研究[J].现代雷达, 2006, 28(11): 71 ~ 74.
[20]栾文彬,唐丽.高速高效信道化接收机及其FPGA实现[J].应用科技,2008, 35(2),13 ~ 16.
[21]王鑫,赵春晖,戎建刚.一种宽带数字信道化接收机的设计[J].哈尔滨理工大学学报, 2006, 11(6): 125 ~ 128.
[22]付永庆,李裕.基于多相滤波器的信道化接收机及其应用研究[J].信号处理, 2004,20(5):517 ~ 520.
[23]宗孔德.多抽样率信号处理[M].北京:电子工业出版社,2002.
[24]李晓鸣.信道化接收机中暂态效应的处理技术[J].电子对抗, 2000, 15(4):31 ~ 36.
[25] Whalen AD, McDonough RN. Detection of Signals in Noise [M].北京:电子工业出版社, 2006.
[26]姚亚峰,付东兵,杨晓非.基于CORDIC改进算法的高速DDS电路设计[J].华中科技大学学报,2009, (2),25 ~ 27.
[27] Yu Hen Hu. CORDIC-based VLSI Architectures for digital signal processing [J]. IEEE signal processing, 1992, (7): 16 ~ 35.
[28]朱荣新,耿富录.复信号求模近似计算及硬件实现[J].火控雷达技术, 1992, (1):31-36.
[29]王旭东,刘渝.多通道自相关信号检测算法及其FPGA实现[J].仪器仪表学报, 2007,28(5):875 ~ 881.
[30]席轶敏,刘渝.电子侦察信号实时检测算法及性能分析[J].南京航空航天大学学报, 2001, 33(3): 277 ~ 281.
[31]王鑫,赵春晖,戎建刚.数字信道化接收机编码器的研究[J].弹箭与制导学报,2006, 26(3): 195 ~ 197.
[32]郑立岗,吕幼新,向敬成.一种基于CORDIC算法的数字鉴频方法[J].信号处理, 2003 ,19 (1) :6 ~ 10.
[33] A.J.Weiss, B.Friendlander. Simultaneous Signals in IFM Receivers [J]. IEE proceedings online, IEE 1997,(4): 117 ~ 122.
[34] D.C.Rife, G.A.Vincent. Use of The Discrete Fourier Transform in The Measurement of Frequencies and Levels of Tones [J]. Bell Syst. Tech. J., Vol.49, 1970: 197 ~ 228.
[35]刘渝.快速高精度正弦波频率估计综合算法[J].电子学报, 1999,27(6):126 ~ 128.
[36]邓振淼,刘渝,王志忠.正弦波频率估计的修正Rife算法[J].数据采集与处理, 2006(4): 473 ~ 477.
[37] Maxfield Clive. The Design Warrior's Guide to FPGAs [M], Newnes, 2004.
[38] Steve Kilts. Advanced FPGA Design [M], Wiley, 2007.
[39]彭乡琳,唐建. FPGA设计的优化方法[J].测控技术, 2005, 24(5): 102 ~106.
[40] Joshi CV, Anuse AD. Use of VHDL in Rapid Prototyping [J]. WSEAS Transactions on Circuits and Systems, 2004,(5): 1085 ~ 1090.
[41] Uwe Meyer-Baese. Digital Signal Processing with Field Programmable Gate Arrays [M].NY: Springer, 2003.
[42]王旭东,刘渝.全并行结构FFT的FPGA实现[J].南京航空航天大学学报, 2006, 38(1):96 ~ 100.
[43] Xilinx Corporation, Virtex-5 Family Overview [Z]. 2008,5.
[44] Xilinx Corporation, Virtex-5 FPGA User Guide [Z].2008, 12.
[45] Xilinx Corporation, Achieving Higher System Performance with the Virtex-5 Family of FPGAs [Z]. 2006, 5.
[46]李和平,王岩飞.高速高精度ADC系统研究[J].数据采集与处理, 2008, 23(B09): 208 ~ 211.
[47] Elbornsson J, Gustafsson F, Eklund JE. Analysis of mismatch effects in a randomly interleaved A/D converter system[J].IEEE Transactions on Circuits and Systems I: Regular Papers, 2005, 52(3): 465 ~ 476.
[48]彭安金,陈向东,古天祥.软件无线电直接射频采样的高速ADC系统研究[J].电波科学学报, 2003,18(2): 184 ~ 188.
[49]张立,王丽,蓝翱华.高速双通道采样芯片AT84AD001B及其应用[J].电子元器件应用, 2009,11(5): 13 ~ 15.
[50] Xilinx Corporation, Virtex-4 Family Overview [Z].2006, 6.
[51] Xilinx Corporation, Virtex-4 FPGA User Guide [Z]. 2008,10.
[2] JamesTusi.宽带数字接收机[M](杨小牛译).北京:电子工业出版社, 2002.
[3]肖庆.宽带数字侦察接收机的实现[J].电子对抗, 2003,(6): 16 ~ 20.
[4] Tsui JB, StePhens JRSr. Digital Microwave Receiver Technology [J]. IEEE Trans on Microwave Theory and Techniques, March 2002, Vol.50 (3):699 ~ 705.
[5]叶斌.对传统超外差接收机的数字化改进[J].电子对抗技术, 2001, 16(5): 11 ~ 16.
[6]殷旭东,王伟,陈曾平.压缩接收机及其在电子战中的应用[J].船舶电子对抗, 2005, 28(4): 21 ~ 24.
[7] J.Mitola. Software Radios: Survey, Critical Evaluation and Future Directions[C]. Proceedings of National Telesystem Conference, NY: Press, 1992.5.
[8] Chen C-I H, George K, McCormick W. Design and Performance Evaluation of 2.5-GSPS Digital Receiver [J]. IEEE Transactions on Instrumentation and Measurement, June 2005, vol.54 (3): 1089 ~ 1099.
[9]董晖,顾善秋.电子战接收机的发展历程及其面临的挑战[J].电子对抗, 2006, (5):43 ~ 48.
[10]殷兆伟,戴国宪.不断发展的现代电子战接收机[J].船舶电子对抗, 2002, 25(5):6 ~ 9.
[11]曹鹏,戴国宪.一种基于软件无线电的电子侦察干扰机[J].电子对抗技术, 2004, 19(6):14 ~ 18.
[12]吴伟,唐斌,张鹏.基于多相滤波高效结构的宽带DDC及其FPGA实现[J].数据采集与处理, 2004, 19(2): 210 ~214.
[13] Fred Harris, Chris Dick, Michael Rice. Digital Receivers and Transmitters Using Polyphase Filter Banks for Wireless Communications [J]. IEEE Transactions on Microwave Theory and Techniques, Vol.51 (4), April 2003: 1395 ~ 1412.
[14]杨小牛,楼才义,徐建良.软件无线电原理与应用[M].北京:电子工业出版社, 2006.
[15] Fields TW, Sharpin DL, Tsui JB. Digital channelized IFM receiver [J], IEEE MTT-S international, Vol.51 , May 1994:1667 ~ 1670.
[16] Zahirniak DR, Sharpin DL, Fields TW. A Hardware-efficient, Multirate, Digital Channelized Receiver Architecture [J]. IEEE Trans. Aerospace and Electronic Systems, 1998, 34(1):137 ~ 152.
[17]宋民,张琦,高梅国.一种大带宽高分辨力数字信道化接收机[J].电子信息对抗技术, 2006, 21(1):14 ~ 17.
[18]杨静,吕幼新.高效数字信道化IFM接收机的研究[J].电子科技大学学报, 2005, 34(4):444 ~ 447.
[19]周欣,吴瑛.基于多相滤波的宽带接收机信道化算法研究[J].现代雷达, 2006, 28(11): 71 ~ 74.
[20]栾文彬,唐丽.高速高效信道化接收机及其FPGA实现[J].应用科技,2008, 35(2),13 ~ 16.
[21]王鑫,赵春晖,戎建刚.一种宽带数字信道化接收机的设计[J].哈尔滨理工大学学报, 2006, 11(6): 125 ~ 128.
[22]付永庆,李裕.基于多相滤波器的信道化接收机及其应用研究[J].信号处理, 2004,20(5):517 ~ 520.
[23]宗孔德.多抽样率信号处理[M].北京:电子工业出版社,2002.
[24]李晓鸣.信道化接收机中暂态效应的处理技术[J].电子对抗, 2000, 15(4):31 ~ 36.
[25] Whalen AD, McDonough RN. Detection of Signals in Noise [M].北京:电子工业出版社, 2006.
[26]姚亚峰,付东兵,杨晓非.基于CORDIC改进算法的高速DDS电路设计[J].华中科技大学学报,2009, (2),25 ~ 27.
[27] Yu Hen Hu. CORDIC-based VLSI Architectures for digital signal processing [J]. IEEE signal processing, 1992, (7): 16 ~ 35.
[28]朱荣新,耿富录.复信号求模近似计算及硬件实现[J].火控雷达技术, 1992, (1):31-36.
[29]王旭东,刘渝.多通道自相关信号检测算法及其FPGA实现[J].仪器仪表学报, 2007,28(5):875 ~ 881.
[30]席轶敏,刘渝.电子侦察信号实时检测算法及性能分析[J].南京航空航天大学学报, 2001, 33(3): 277 ~ 281.
[31]王鑫,赵春晖,戎建刚.数字信道化接收机编码器的研究[J].弹箭与制导学报,2006, 26(3): 195 ~ 197.
[32]郑立岗,吕幼新,向敬成.一种基于CORDIC算法的数字鉴频方法[J].信号处理, 2003 ,19 (1) :6 ~ 10.
[33] A.J.Weiss, B.Friendlander. Simultaneous Signals in IFM Receivers [J]. IEE proceedings online, IEE 1997,(4): 117 ~ 122.
[34] D.C.Rife, G.A.Vincent. Use of The Discrete Fourier Transform in The Measurement of Frequencies and Levels of Tones [J]. Bell Syst. Tech. J., Vol.49, 1970: 197 ~ 228.
[35]刘渝.快速高精度正弦波频率估计综合算法[J].电子学报, 1999,27(6):126 ~ 128.
[36]邓振淼,刘渝,王志忠.正弦波频率估计的修正Rife算法[J].数据采集与处理, 2006(4): 473 ~ 477.
[37] Maxfield Clive. The Design Warrior's Guide to FPGAs [M], Newnes, 2004.
[38] Steve Kilts. Advanced FPGA Design [M], Wiley, 2007.
[39]彭乡琳,唐建. FPGA设计的优化方法[J].测控技术, 2005, 24(5): 102 ~106.
[40] Joshi CV, Anuse AD. Use of VHDL in Rapid Prototyping [J]. WSEAS Transactions on Circuits and Systems, 2004,(5): 1085 ~ 1090.
[41] Uwe Meyer-Baese. Digital Signal Processing with Field Programmable Gate Arrays [M].NY: Springer, 2003.
[42]王旭东,刘渝.全并行结构FFT的FPGA实现[J].南京航空航天大学学报, 2006, 38(1):96 ~ 100.
[43] Xilinx Corporation, Virtex-5 Family Overview [Z]. 2008,5.
[44] Xilinx Corporation, Virtex-5 FPGA User Guide [Z].2008, 12.
[45] Xilinx Corporation, Achieving Higher System Performance with the Virtex-5 Family of FPGAs [Z]. 2006, 5.
[46]李和平,王岩飞.高速高精度ADC系统研究[J].数据采集与处理, 2008, 23(B09): 208 ~ 211.
[47] Elbornsson J, Gustafsson F, Eklund JE. Analysis of mismatch effects in a randomly interleaved A/D converter system[J].IEEE Transactions on Circuits and Systems I: Regular Papers, 2005, 52(3): 465 ~ 476.
[48]彭安金,陈向东,古天祥.软件无线电直接射频采样的高速ADC系统研究[J].电波科学学报, 2003,18(2): 184 ~ 188.
[49]张立,王丽,蓝翱华.高速双通道采样芯片AT84AD001B及其应用[J].电子元器件应用, 2009,11(5): 13 ~ 15.
[50] Xilinx Corporation, Virtex-4 Family Overview [Z].2006, 6.
[51] Xilinx Corporation, Virtex-4 FPGA User Guide [Z]. 2008,10.