宽带数字阵雷达分数延时测量与实现技术研究
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摘要
数字阵列雷达是一种接收和发射波束都以数字方式实现的全数字相控阵雷达。本文针对如何精确测量宽带数字阵雷达通道延时,如何对通道延时进行补偿也就是实现宽带信号的延时,从而提高数字波束形成的精度这些尚待解决的难题,进行了分数延时测量方法、分数延时实现方法的研究,主要内容为:
1.研究宽带线性调频信号的延时测量。数字相控阵雷达各个阵元通道之间由于通道一致性会产生微小延时,本文用差拍法、插值相关法以及自适应法测量宽带LFM信号的延时并进行了仿真。结果表明差拍法能够较准确的测量出整数延时和小数延时;相关法能够精确的测量出整数延时,但是对于小数延时,存在着较大的误差,只能精确到小数的整数部分;自适应法在测量宽带LFM信号时存在着较大的误差。因而,可用差拍法测量宽带LFM信号的微小延时。
2.对分数延时方法的研究。包括对各种基本分数延时方法的特点和优缺点以及实现方法的研究。并对IIR和FIR分数延时滤波器的设计方法、性能、硬件实现的复杂度和稳定度进行了分析和比较。
3.研究了一种适用于相控阵雷达波束形成的分数延时滤波器的优化算法。采用多速率处理的方法来实现分数延时,其分支滤波器用频域加权最小二乘(WLS)逼近方法优化。与现有的方法进行比较,优点主要在于频域优化的范围小,可以大大减少运算时间,降低了滤波器的阶数和运算量;可以通过适当增加半带滤波器的通带范围,以HBF增加十几阶为代价,避免了繁琐的加权系数的计算;在确定了通带范围和纹波波动的情况下,只需要输入需要延时的数据,就能实现可变的延时,有利于FPGA的硬件实现。仿真验证了其正确性。
4.基于FPGA的分数延时数字滤波器的实现研究。包括利用FPGA实现数字延时的关键技术,涉及到对系数的处理和误差分析,分布式算法和流水线技术,并以FPGA的IP核的方式实现了分数延时滤波器。
Digital Array Radar(DAR) is a fully digitized phased array radar in which digital beamforming techniques is used both in receiving and transmitting. In order to improve the accuracy of digital beamforming, the problems of how to accurately measure and compensate the channel delay in the broadband DAR are yet to be resolved. This dissertation is to address the problems of fractional delay measurement and implementation methods. The main work can be summarized as follows:
1. The delay measurements of broadband LFM signal are researched. Minimal delay among channels of digital phased array radar is produced due to channel difference. Broadband LFM signal delay is measured by the methods of frequency beat, correlation and adaptive. Simulation results show that frequency beat method can approximately measure integer delay and decimal delay, the correlation method can precisely measure integer delay but fractional delay, while there is biggish error using adaptive method. As a result, frequency beat method can be used to measure the small delay of broadband LFM signal.
2. The methods of fractional delay are researched, including characteristics, advantages and disadvantages of the basic fractional delay methods and their implementation. The design methods of existing fractional delay filters are analyzed and summarized. The design methods, performance, complexity of hardware implementation and stability of FIR and IIR fractional delay filter are analyzed and compared in this dissertation.
3.An optimization algorithm of fractional delay filter for beamforming in phased array radar is researched. A multi-rate processing method is used to achieve fractional delay, using weighted least squares (WLS) approximation optimization in frequency domain for its branch filters. With the existing methods of comparison, the main advantage of this optimization algorithm is that the range of frequency-domain optimization is small, which can greatly reduce the computing time, the order of the filter and the computation. The tedious weighted coefficient calculation can be avoided at the cost of increasing a dozen of orders of HBF. Once the passband and ripple are determined, we only need to import the delay data to achieve variable delay, which is easy for the FPGA hardware implementation. MATLAB simulation is done.
4. The implementation of FPGA-based fractional delay is researched. This study is about the key technologies of using FPGA to implement digital delay, related to the coefficient processing and error analysis, distributed algorithm and pipeline technology. Then the fractional delay filter is implemented by means of FPGA IP core.
1.研究宽带线性调频信号的延时测量。数字相控阵雷达各个阵元通道之间由于通道一致性会产生微小延时,本文用差拍法、插值相关法以及自适应法测量宽带LFM信号的延时并进行了仿真。结果表明差拍法能够较准确的测量出整数延时和小数延时;相关法能够精确的测量出整数延时,但是对于小数延时,存在着较大的误差,只能精确到小数的整数部分;自适应法在测量宽带LFM信号时存在着较大的误差。因而,可用差拍法测量宽带LFM信号的微小延时。
2.对分数延时方法的研究。包括对各种基本分数延时方法的特点和优缺点以及实现方法的研究。并对IIR和FIR分数延时滤波器的设计方法、性能、硬件实现的复杂度和稳定度进行了分析和比较。
3.研究了一种适用于相控阵雷达波束形成的分数延时滤波器的优化算法。采用多速率处理的方法来实现分数延时,其分支滤波器用频域加权最小二乘(WLS)逼近方法优化。与现有的方法进行比较,优点主要在于频域优化的范围小,可以大大减少运算时间,降低了滤波器的阶数和运算量;可以通过适当增加半带滤波器的通带范围,以HBF增加十几阶为代价,避免了繁琐的加权系数的计算;在确定了通带范围和纹波波动的情况下,只需要输入需要延时的数据,就能实现可变的延时,有利于FPGA的硬件实现。仿真验证了其正确性。
4.基于FPGA的分数延时数字滤波器的实现研究。包括利用FPGA实现数字延时的关键技术,涉及到对系数的处理和误差分析,分布式算法和流水线技术,并以FPGA的IP核的方式实现了分数延时滤波器。
Digital Array Radar(DAR) is a fully digitized phased array radar in which digital beamforming techniques is used both in receiving and transmitting. In order to improve the accuracy of digital beamforming, the problems of how to accurately measure and compensate the channel delay in the broadband DAR are yet to be resolved. This dissertation is to address the problems of fractional delay measurement and implementation methods. The main work can be summarized as follows:
1. The delay measurements of broadband LFM signal are researched. Minimal delay among channels of digital phased array radar is produced due to channel difference. Broadband LFM signal delay is measured by the methods of frequency beat, correlation and adaptive. Simulation results show that frequency beat method can approximately measure integer delay and decimal delay, the correlation method can precisely measure integer delay but fractional delay, while there is biggish error using adaptive method. As a result, frequency beat method can be used to measure the small delay of broadband LFM signal.
2. The methods of fractional delay are researched, including characteristics, advantages and disadvantages of the basic fractional delay methods and their implementation. The design methods of existing fractional delay filters are analyzed and summarized. The design methods, performance, complexity of hardware implementation and stability of FIR and IIR fractional delay filter are analyzed and compared in this dissertation.
3.An optimization algorithm of fractional delay filter for beamforming in phased array radar is researched. A multi-rate processing method is used to achieve fractional delay, using weighted least squares (WLS) approximation optimization in frequency domain for its branch filters. With the existing methods of comparison, the main advantage of this optimization algorithm is that the range of frequency-domain optimization is small, which can greatly reduce the computing time, the order of the filter and the computation. The tedious weighted coefficient calculation can be avoided at the cost of increasing a dozen of orders of HBF. Once the passband and ripple are determined, we only need to import the delay data to achieve variable delay, which is easy for the FPGA hardware implementation. MATLAB simulation is done.
4. The implementation of FPGA-based fractional delay is researched. This study is about the key technologies of using FPGA to implement digital delay, related to the coefficient processing and error analysis, distributed algorithm and pipeline technology. Then the fractional delay filter is implemented by means of FPGA IP core.
引文
[1]李正,孙雨南.应用在相控阵雷达上的光学实时延迟线. 2006,Vol.32(3):381-384
[2]陈祝明.软件无线电技术基础.北京:高等教育出版社,2007,145
[3]吴曼青.数字阵列雷达及其进展.中国电子科学研究院学报.2006,11-16
[4] T. I. Laakso, V. Valimdki, Karjalainen, et al. splitting the unit delay: Tools for fractional delay filter design. IEEE Signal Processing Mag.,1996 ,vol. 13: 30-60
[5] T.-B. Deng. Symmetry-based low-complexity variable fractional-delay FIR filters.IEEE International Symposium on Communications and Information Technologies, 2004, 194-199
[6] T.-B. Deng. Weighted-Least-Squares Design of Variable Fractional-Delay FIR Filters Using Coefficient Symmetry.Transactions on Signal Processing, 2006, Vol. 54( 8): 3023-3038
[7] T.-B. Deng. Coefficient symmetry and efficient implementation of Lagrange-type variable fractional-delay filters. Proc. IEEE ICICS 2005, 555-558
[8] T.-B. Deng. Weighted least-squares method for designing arbitrarily variable 1-D FIR digital filters. Signal Process., 2000,vol. 80(4): 597–613
[9] A. Tarczynski, G. D. Cain, E. Hermanowicz, et al. WLS design of variable frequency response FIR filters. IEEE Int. Symp. Circuits and Systems, 1997, 2244–2247
[10] W.-S. Lu, T.-B. Deng. An improved weighted least-squares design for variable fractional delay FIR filters. IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process.,1999, vol. 46(8): 1035–1040
[11] T.-B. Deng. Discretization-free design of variable fractional-delay FIR digital filters. IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process.,2001, vol. 48(6): 637–644
[12] Jussi Vesma, Tapio Saramaki. Design and properties of polynomial-based fractional delay filters. IEEE International Symposium on Circuits and Systems, 2000, v 1: I-104–I-107
[13] H?kan Johansson, Oscar Gustafsson, Kenny Johansson, Lars Wanhammar. Adjustable Fractional-Delay FIR Filters Using the Farrow Structure and Multirate Techniques. APCCAS 2006,1055-1058
[14] C.-C. Tseng. Design of variable fractional delay FIR filters using symmetry. IEEE Int. Symp. Circuits and Systems. Vancouver, Canada, 2004, vol. III: 477–480
[15] J. Vesma, T. Saram?ki. Optimization and efficient implementation of FIR filters with adjustable fractional delay. IEEE Int. Symp.Circuits Syst., 1997, vol. IV: 2256–2259
[16] J. Vesma, T. Saramaki. Design and properties of polynomial-based fractional delay filters. Int. Symp. Circuits and Systems, 2000, I-104–I-107
[17] E. Hermanowicz. On Designing a Wideband Fractional Delay Filter using the Farrow Approach. Proc. of XII. European Signal Processing Conference, 2004, 961-964
[18] T.-B.Deng, Y. Nakagawa. SVD-based design and new structures for variable fractional-delay digital filters. IEEE Trans. Signal rocessing,2004,vol. 52: 2513-2527
[19] T.-B. Deng. Design of arbitrary-phase variable digital filters using SVD-based vector-array decomposition. IEEE Trans. Circuits Syst, 2005,vol. 52: 148-167
[20] H.Zhao, J.B. Yu. A novel neural network-based approach for designing digital filters. IEEE Int. Symp. Circuits and Systems, 1997, 2272-2275
[21] H.Zhao, J.B. Yu. A novel neural network-based approach for designing 2-D FIR filters. IEEE Trans. on Circuits and Systems-I, 1997,Vol. 44( 11): 1095-1099
[22] Hui Zhao, Juebang Yu. A Simple and Efficient Design of Variable Fractional Delay FIR Filters. IEEE Transactions on Circuits and Systems II: Express Briefs, 2006,v 53(2):157-160
[23] Cagatay Candan. An Efficient Filtering Structure for Lagrange Interpolation. IEEE Signal Processing Letters, 2007,v 14(1):17-19
[24] Soo-Chang Pe, Chien-Cheng Tseng. An efficient design of a variable fractional delay filter using a first-order differentiator. IEEE Signal Processing Letters,2003, Vol. 10:307– 310
[25] Xiang-Gen Xia . Fractional delay filter design when sampling rate higher than Nyquist rate. Electronics Letters, 1997,v 33( 3):199-201
[26] A. G. Dempster, N. P. Murphy. Efficient Interpolators and Filter Banks using Multiplier Blocks. IEEE Transactions On Signal Processing, 2000,Vol. 48(1): 257-261
[27] M. Potkonjak, M. B. Shrivasta, A. P. Chandrakasan. Multiple constant multiplication: Efficient and versatile framework and algorithms for exploring common subexpression elimination. IEEE Trans. Computer-Aided Design, 1996,vol. 15:151–161
[28] Y. Voronenko, M. Püschel. Multiplierless multiple constant multiplication. ACM Transactions on Algorithms, 2007,v 3(2):1240234
[29] A. G. Dempster, N. P. Murphy. Efficient interpolators and filter banks using multiplier blocks. IEEE Trans. Signal Processing,2000, vol. 48(1): 257–261
[30] C. H. Knapp,G.C. Cater. The generalized correlation method for estimation of time delay.IEEE Trans. ASSP , 1976,vol. 24(4):320-327
[31] A. G. Piersol. Time delay estimation using phase data. IEEE Trans. ASSP, 1981,vol. 29: 471-477
[32] K. C. Ho,Y. T. Chan and P. C. Ching. Adaptive time delay estimation in nonstationary signal and/or noise power environments. IEEE Trans. Signal Processing, 1993,vol. 41(7):2289-2299
[33] Z. Cheng, T. T. Tjhuang. A new time delay estimator based on ETDE. IEEE Trans. Signal Processing,2003, vol.51(7):1859-1869
[34]李从英,王建英,尹忠科,等.基于四阶累积量自适应时延估计的改进.铁道学报,2006,Vol.28(6):55-58
[35]何焰兰,苏勇.雷达中时延估计的新方法.信号处理,1999,Vo1.15(2):176-181
[36]魏永豪,袁晓,滕旭东,等.广义希尔伯特变换及其数字实现.电子科技大学学报,2005,(02)
[37]李冬文,贾春燕,叶莉华,崔一平.光控相控阵雷达中的真延时技术. 2006,Vo1.43(3):37-42
[38]张光义,赵玉洁.相控阵雷达技术.北京:电子工业出版社,2006,397-398
[39]程佩青.数字信号处理教程.北京:清华大学出版社,2000
[40] N.P.Murphy, A.Krukowski, I.Kale. Implementation of a wide-band integer and fractional delay element. Electronics letters, 1994,vol.30(20):1658-1659
[41] JOVANOVIC D G, DIAZ C J. One Structure for Wide-Bandwidth and High-Resolution Fractional Delay Filter. IEEE International Conference on Electronics Circuits and Systems, 2002,899-902
[42]潘松,黄继业,王国栋.现代DSP技术.西安:西安电子科技大学出版社,2004,4-18
[43]李玉林.基于FPGA的直接型FIR滤波器实现.现代电子技术,2006,Vol.10
[44] A.V.奥本海姆, R.W.谢弗, J.R.巴克.离散时间信号处理(刘树棠,黄建国译).西安:西安交通大学出版社
[45]刘凌,胡永生.数字信号处理的FPGA实现.北京:清华大学出版社,2004,54
[46]杨君,王景存.基于VerilogHDL的流水线的设计方法及应用.武汉科技大学学报(自然科学版),2002,Vol.25(4):394-397
[47] Michael D.Ciletti. Verilog HDL高级数字设计(张雅绮,李锵,等译).北京:电子工业出版社,2005,570-579
[2]陈祝明.软件无线电技术基础.北京:高等教育出版社,2007,145
[3]吴曼青.数字阵列雷达及其进展.中国电子科学研究院学报.2006,11-16
[4] T. I. Laakso, V. Valimdki, Karjalainen, et al. splitting the unit delay: Tools for fractional delay filter design. IEEE Signal Processing Mag.,1996 ,vol. 13: 30-60
[5] T.-B. Deng. Symmetry-based low-complexity variable fractional-delay FIR filters.IEEE International Symposium on Communications and Information Technologies, 2004, 194-199
[6] T.-B. Deng. Weighted-Least-Squares Design of Variable Fractional-Delay FIR Filters Using Coefficient Symmetry.Transactions on Signal Processing, 2006, Vol. 54( 8): 3023-3038
[7] T.-B. Deng. Coefficient symmetry and efficient implementation of Lagrange-type variable fractional-delay filters. Proc. IEEE ICICS 2005, 555-558
[8] T.-B. Deng. Weighted least-squares method for designing arbitrarily variable 1-D FIR digital filters. Signal Process., 2000,vol. 80(4): 597–613
[9] A. Tarczynski, G. D. Cain, E. Hermanowicz, et al. WLS design of variable frequency response FIR filters. IEEE Int. Symp. Circuits and Systems, 1997, 2244–2247
[10] W.-S. Lu, T.-B. Deng. An improved weighted least-squares design for variable fractional delay FIR filters. IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process.,1999, vol. 46(8): 1035–1040
[11] T.-B. Deng. Discretization-free design of variable fractional-delay FIR digital filters. IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process.,2001, vol. 48(6): 637–644
[12] Jussi Vesma, Tapio Saramaki. Design and properties of polynomial-based fractional delay filters. IEEE International Symposium on Circuits and Systems, 2000, v 1: I-104–I-107
[13] H?kan Johansson, Oscar Gustafsson, Kenny Johansson, Lars Wanhammar. Adjustable Fractional-Delay FIR Filters Using the Farrow Structure and Multirate Techniques. APCCAS 2006,1055-1058
[14] C.-C. Tseng. Design of variable fractional delay FIR filters using symmetry. IEEE Int. Symp. Circuits and Systems. Vancouver, Canada, 2004, vol. III: 477–480
[15] J. Vesma, T. Saram?ki. Optimization and efficient implementation of FIR filters with adjustable fractional delay. IEEE Int. Symp.Circuits Syst., 1997, vol. IV: 2256–2259
[16] J. Vesma, T. Saramaki. Design and properties of polynomial-based fractional delay filters. Int. Symp. Circuits and Systems, 2000, I-104–I-107
[17] E. Hermanowicz. On Designing a Wideband Fractional Delay Filter using the Farrow Approach. Proc. of XII. European Signal Processing Conference, 2004, 961-964
[18] T.-B.Deng, Y. Nakagawa. SVD-based design and new structures for variable fractional-delay digital filters. IEEE Trans. Signal rocessing,2004,vol. 52: 2513-2527
[19] T.-B. Deng. Design of arbitrary-phase variable digital filters using SVD-based vector-array decomposition. IEEE Trans. Circuits Syst, 2005,vol. 52: 148-167
[20] H.Zhao, J.B. Yu. A novel neural network-based approach for designing digital filters. IEEE Int. Symp. Circuits and Systems, 1997, 2272-2275
[21] H.Zhao, J.B. Yu. A novel neural network-based approach for designing 2-D FIR filters. IEEE Trans. on Circuits and Systems-I, 1997,Vol. 44( 11): 1095-1099
[22] Hui Zhao, Juebang Yu. A Simple and Efficient Design of Variable Fractional Delay FIR Filters. IEEE Transactions on Circuits and Systems II: Express Briefs, 2006,v 53(2):157-160
[23] Cagatay Candan. An Efficient Filtering Structure for Lagrange Interpolation. IEEE Signal Processing Letters, 2007,v 14(1):17-19
[24] Soo-Chang Pe, Chien-Cheng Tseng. An efficient design of a variable fractional delay filter using a first-order differentiator. IEEE Signal Processing Letters,2003, Vol. 10:307– 310
[25] Xiang-Gen Xia . Fractional delay filter design when sampling rate higher than Nyquist rate. Electronics Letters, 1997,v 33( 3):199-201
[26] A. G. Dempster, N. P. Murphy. Efficient Interpolators and Filter Banks using Multiplier Blocks. IEEE Transactions On Signal Processing, 2000,Vol. 48(1): 257-261
[27] M. Potkonjak, M. B. Shrivasta, A. P. Chandrakasan. Multiple constant multiplication: Efficient and versatile framework and algorithms for exploring common subexpression elimination. IEEE Trans. Computer-Aided Design, 1996,vol. 15:151–161
[28] Y. Voronenko, M. Püschel. Multiplierless multiple constant multiplication. ACM Transactions on Algorithms, 2007,v 3(2):1240234
[29] A. G. Dempster, N. P. Murphy. Efficient interpolators and filter banks using multiplier blocks. IEEE Trans. Signal Processing,2000, vol. 48(1): 257–261
[30] C. H. Knapp,G.C. Cater. The generalized correlation method for estimation of time delay.IEEE Trans. ASSP , 1976,vol. 24(4):320-327
[31] A. G. Piersol. Time delay estimation using phase data. IEEE Trans. ASSP, 1981,vol. 29: 471-477
[32] K. C. Ho,Y. T. Chan and P. C. Ching. Adaptive time delay estimation in nonstationary signal and/or noise power environments. IEEE Trans. Signal Processing, 1993,vol. 41(7):2289-2299
[33] Z. Cheng, T. T. Tjhuang. A new time delay estimator based on ETDE. IEEE Trans. Signal Processing,2003, vol.51(7):1859-1869
[34]李从英,王建英,尹忠科,等.基于四阶累积量自适应时延估计的改进.铁道学报,2006,Vol.28(6):55-58
[35]何焰兰,苏勇.雷达中时延估计的新方法.信号处理,1999,Vo1.15(2):176-181
[36]魏永豪,袁晓,滕旭东,等.广义希尔伯特变换及其数字实现.电子科技大学学报,2005,(02)
[37]李冬文,贾春燕,叶莉华,崔一平.光控相控阵雷达中的真延时技术. 2006,Vo1.43(3):37-42
[38]张光义,赵玉洁.相控阵雷达技术.北京:电子工业出版社,2006,397-398
[39]程佩青.数字信号处理教程.北京:清华大学出版社,2000
[40] N.P.Murphy, A.Krukowski, I.Kale. Implementation of a wide-band integer and fractional delay element. Electronics letters, 1994,vol.30(20):1658-1659
[41] JOVANOVIC D G, DIAZ C J. One Structure for Wide-Bandwidth and High-Resolution Fractional Delay Filter. IEEE International Conference on Electronics Circuits and Systems, 2002,899-902
[42]潘松,黄继业,王国栋.现代DSP技术.西安:西安电子科技大学出版社,2004,4-18
[43]李玉林.基于FPGA的直接型FIR滤波器实现.现代电子技术,2006,Vol.10
[44] A.V.奥本海姆, R.W.谢弗, J.R.巴克.离散时间信号处理(刘树棠,黄建国译).西安:西安交通大学出版社
[45]刘凌,胡永生.数字信号处理的FPGA实现.北京:清华大学出版社,2004,54
[46]杨君,王景存.基于VerilogHDL的流水线的设计方法及应用.武汉科技大学学报(自然科学版),2002,Vol.25(4):394-397
[47] Michael D.Ciletti. Verilog HDL高级数字设计(张雅绮,李锵,等译).北京:电子工业出版社,2005,570-579