集成电路成品率预测技术研究
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摘要
在过去的几十年中,半导体制造技术一直沿着摩尔定律飞速发展。现今最先进集成电路设计中的关键尺寸已经达到了22nm,远低于光刻工艺中的光源波长。新工艺技术的引入以及制造环境因素开始剧烈的影响到集成电路的可靠性和成品率。研究集成电路制造中成品率损失的深层次原因和解决办法成为现代半导体产业的一个重要课题。可制造性设计和针对成品率设计的概念就是在这样一个背景下提出的。
论文即针对成品率这一问题展开,内容为集成电路成品率预测技术研究。在半导体行业,成品率定义为在一次投产中,产出满足性能要求的芯片在芯片生产总数中所占的比例。成品率关系到制造成本和收益,因此直接影响一个集成电路项目的成败。而成品率预测技术使生产者能够在生产前便对最终的成品率有所了解,从而在需求、成本和收益之间做出适当的部署,而非盲目的投产。更进一步,依靠成品率预测技术,生产者还能够分析造成成品率损失的原因,制定可行且高效的成品率优化策略。以下概括论文的主要内容和创新点。
开发了一款用于预测和分析集成电路成品率的工具平台。基于对成品率预测技术的理解,论文完成了成品率预测工具平台的研发,并就运算效率方面做了深入的研究和有效的改进。该平台在国内一家主流的集成电路制造厂商中通过了验址。
提出了一种多线程计算框架用以计算超大规模集成电路上的关键面积。在该计算框架下,关键面积的计算时间同版图的面积成线性关系,即随着版图规模的增加,程序的运行时间线性增长。同时,程序运行时所需内存也可以调节。这两点优势使得我们的工具能够应对超大规模的纳米级集成电路版图。
改进了通孔层成品率模型的计算精度。为提高电路的可靠性和降低断路故障发生的几率,设计者越来越多的使用了冗余通孔和冗余走线。因此,传统的基于单通孔计数的成品率模型因未考虑回路的情况给出的预测往往存在较大的误差。通过对版图建立连接关系图并设计一种线性时间复杂度的用于从图中搜索回路通孔算法,论文提出了一种改进的通孔层成品率计算方法。
提出了一种新的版图数据结构,其时间和空间上的性能表现均优于现有的版图数据结构。版图数据结构是本文的成品率预测平台以及其他众多的后端验证应用工具的基础。版图数据结构的新能直接影响到这些工具的性能和用户体验。EDA工具的开发者总是希望版图数据结构提供更快的操作同时占用更少的内存。同迄今为止被业界认为最优的HV/VH Tree相比,新数据结构执行区域检索的速度快出30%,并占用更少的内存。
提出了一种针对记忆体电路的成品率模型。鉴于记忆体电路中冗余单元的存在,传统的成品率模型并不适用于记忆体电路。论文提出了一种针对记忆体电路的成品率模型。除成品率预测常规的作用之外,该方法还有助于记忆体电路中冗余单元的优化设计。举例来说,在记忆体电路的设计阶段布置更多的冗余单元固然能够提高生产的成品率,但同时也增大了芯片面积进而降低了产量。一个精确的成品率模型能够帮助设计者在上述两种考虑间做出权衡。
In the past few decades, VLSI manufacturing technology has been advancing according to Moore's Law. The critical dimension of state-of-the-art chip already achieves 22nm, far below the wavelength of the light source used in lithography. The performance and reliability of integrated circuits have been negatively affected by the introduction of new processes and the manufacturing environment, and yield drops. Identification and fix of the root causes of yield losses is becoming a very important topic in semiconductor industry. Design for manufacturability and design for yield are proposed under such a circumstance.
We have focused on yield, and the content of this thesis is the yield predicting technique. In semiconductor industry, yield is defined as the ratio of the number of good units of a manufactured product that meets all the requirements in the specification to the total number of manufactured units. Yield is directly related to the profitability on semiconductor products, so it is critical to the business success of integrated circuits projects. Predictability in manufacturing yield is important for production control, material management, timely product delivery and other business factors. Furthermore, by adopting appropriate yield models in yield predicting enables fabricators to analyze the sources of yield losses, thus to establish effective moves to efficiently improve manufacturing yield. Following contents are a summarization of our main research contents and innovations:
Implemented a software platform aiming at yield prediction and analysis. Based on the knowledge of yield predicting techniques, we have accomplished the development work of the software, and made special effort to improve its calculation efficiency. The tool passed verification in a mainstream semiconductor foundry in mainland China.
Proposed a parallel computing scheme for critical area extraction on state-of-the-art chips. By employing this scheme, the extraction time of critical area is linear with respect to the chip area, the extraction time increases linearly as the chip gets larger. Meanwhile, the space requirement within our scheme is also configurable. These two factors make our tool feasible to handle nano-scale layouts.
Improved the accuracy of yield calculation for via layers. In order to increase reliability and reduce the potential for open faults, designers are introducing redundant vias and interconnects. So the single via counting method in via layer yield modeling is not sufficiently precise since it does not take loops into consideration. We come up with an improved method by modeling the problem as a geometric graph problem and an algorithm which extracts loop vias in linear time complexity.
Proposed a new layout data structure which outperforms all existing ones taking both time and space into consideration. Layout data structure is the foundation of our yield predicting software and lots of other applications used for post-layout verification. The performance of the layout data structure directly affects the performance of those applications and the user experience. EDA software designers always hope to find better data structures which provide faster access operations and use less memory space at the same time. Compared with HV/VH Tree which is considered as the best choice to date, our new data structure performs region query 30% faster, and uses much less memory.
Proposed a yield model for memory chip yield predicting. Due to the existence of redundancies, traditional yield models do not apply to memory chips. We proposed a yield model specially customized for memory layouts. In addition to the regular advantages yield predicting provides, our model enables the designer to optimize redundancy amount and scheme. For instance, designing more redundancies do help increase manufacturing yield, but it also increases the chip size thus decreases the productivity. An accurate yield model helps designer to determine that trade-off. Key words:Design for Manufacturability, Design for Yield, Yield Model, Critical Area, Yield Predicting Technique, Layout Data Structure, Concurrent Programming
论文即针对成品率这一问题展开,内容为集成电路成品率预测技术研究。在半导体行业,成品率定义为在一次投产中,产出满足性能要求的芯片在芯片生产总数中所占的比例。成品率关系到制造成本和收益,因此直接影响一个集成电路项目的成败。而成品率预测技术使生产者能够在生产前便对最终的成品率有所了解,从而在需求、成本和收益之间做出适当的部署,而非盲目的投产。更进一步,依靠成品率预测技术,生产者还能够分析造成成品率损失的原因,制定可行且高效的成品率优化策略。以下概括论文的主要内容和创新点。
开发了一款用于预测和分析集成电路成品率的工具平台。基于对成品率预测技术的理解,论文完成了成品率预测工具平台的研发,并就运算效率方面做了深入的研究和有效的改进。该平台在国内一家主流的集成电路制造厂商中通过了验址。
提出了一种多线程计算框架用以计算超大规模集成电路上的关键面积。在该计算框架下,关键面积的计算时间同版图的面积成线性关系,即随着版图规模的增加,程序的运行时间线性增长。同时,程序运行时所需内存也可以调节。这两点优势使得我们的工具能够应对超大规模的纳米级集成电路版图。
改进了通孔层成品率模型的计算精度。为提高电路的可靠性和降低断路故障发生的几率,设计者越来越多的使用了冗余通孔和冗余走线。因此,传统的基于单通孔计数的成品率模型因未考虑回路的情况给出的预测往往存在较大的误差。通过对版图建立连接关系图并设计一种线性时间复杂度的用于从图中搜索回路通孔算法,论文提出了一种改进的通孔层成品率计算方法。
提出了一种新的版图数据结构,其时间和空间上的性能表现均优于现有的版图数据结构。版图数据结构是本文的成品率预测平台以及其他众多的后端验证应用工具的基础。版图数据结构的新能直接影响到这些工具的性能和用户体验。EDA工具的开发者总是希望版图数据结构提供更快的操作同时占用更少的内存。同迄今为止被业界认为最优的HV/VH Tree相比,新数据结构执行区域检索的速度快出30%,并占用更少的内存。
提出了一种针对记忆体电路的成品率模型。鉴于记忆体电路中冗余单元的存在,传统的成品率模型并不适用于记忆体电路。论文提出了一种针对记忆体电路的成品率模型。除成品率预测常规的作用之外,该方法还有助于记忆体电路中冗余单元的优化设计。举例来说,在记忆体电路的设计阶段布置更多的冗余单元固然能够提高生产的成品率,但同时也增大了芯片面积进而降低了产量。一个精确的成品率模型能够帮助设计者在上述两种考虑间做出权衡。
In the past few decades, VLSI manufacturing technology has been advancing according to Moore's Law. The critical dimension of state-of-the-art chip already achieves 22nm, far below the wavelength of the light source used in lithography. The performance and reliability of integrated circuits have been negatively affected by the introduction of new processes and the manufacturing environment, and yield drops. Identification and fix of the root causes of yield losses is becoming a very important topic in semiconductor industry. Design for manufacturability and design for yield are proposed under such a circumstance.
We have focused on yield, and the content of this thesis is the yield predicting technique. In semiconductor industry, yield is defined as the ratio of the number of good units of a manufactured product that meets all the requirements in the specification to the total number of manufactured units. Yield is directly related to the profitability on semiconductor products, so it is critical to the business success of integrated circuits projects. Predictability in manufacturing yield is important for production control, material management, timely product delivery and other business factors. Furthermore, by adopting appropriate yield models in yield predicting enables fabricators to analyze the sources of yield losses, thus to establish effective moves to efficiently improve manufacturing yield. Following contents are a summarization of our main research contents and innovations:
Implemented a software platform aiming at yield prediction and analysis. Based on the knowledge of yield predicting techniques, we have accomplished the development work of the software, and made special effort to improve its calculation efficiency. The tool passed verification in a mainstream semiconductor foundry in mainland China.
Proposed a parallel computing scheme for critical area extraction on state-of-the-art chips. By employing this scheme, the extraction time of critical area is linear with respect to the chip area, the extraction time increases linearly as the chip gets larger. Meanwhile, the space requirement within our scheme is also configurable. These two factors make our tool feasible to handle nano-scale layouts.
Improved the accuracy of yield calculation for via layers. In order to increase reliability and reduce the potential for open faults, designers are introducing redundant vias and interconnects. So the single via counting method in via layer yield modeling is not sufficiently precise since it does not take loops into consideration. We come up with an improved method by modeling the problem as a geometric graph problem and an algorithm which extracts loop vias in linear time complexity.
Proposed a new layout data structure which outperforms all existing ones taking both time and space into consideration. Layout data structure is the foundation of our yield predicting software and lots of other applications used for post-layout verification. The performance of the layout data structure directly affects the performance of those applications and the user experience. EDA software designers always hope to find better data structures which provide faster access operations and use less memory space at the same time. Compared with HV/VH Tree which is considered as the best choice to date, our new data structure performs region query 30% faster, and uses much less memory.
Proposed a yield model for memory chip yield predicting. Due to the existence of redundancies, traditional yield models do not apply to memory chips. We proposed a yield model specially customized for memory layouts. In addition to the regular advantages yield predicting provides, our model enables the designer to optimize redundancy amount and scheme. For instance, designing more redundancies do help increase manufacturing yield, but it also increases the chip size thus decreases the productivity. An accurate yield model helps designer to determine that trade-off. Key words:Design for Manufacturability, Design for Yield, Yield Model, Critical Area, Yield Predicting Technique, Layout Data Structure, Concurrent Programming
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