基于SOPC的动态脑电系统的研制
摘要
脑电检测是了解脑功能状况、辅助诊断脑疾病、评估各种治疗方法的重要手段。利用常规脑电设备进行检测,由于时间和环境的限制,往往得不到有确切意义的结果。为此,人们一直致力于在非医院环境中进行长程脑电检测的动态脑电系统(AEEG)的研制工作。
SOPC系统是一种基于FPGA的灵活、高效的SOC解决方案,是一种软硬件协同设计的系统设计技术。它将处理器、存储器、I/O口等系统设计需要的功能模块集成到一个可编程器件上,构成一个可编程的片上系统。SOPC是未来半导体的发展趋势。本论文设计了一个基于SOPC的脑电信号采集系统。由头皮电极采集脑电信号,并对其进行放大、滤波等预处理,再经过一个多通道模/数转换器,将其转换为数字信号。为了完成各项控制、数字滤波和数据存储,我们定制了一个SOPC系统。最终将处理过的数据保存在SD卡中供计算机进一步分析。本系统的硬件平台为DE2开发板,软件部分以NiosⅡ软核处理器为核心。功能模块以IP核的形式添加到系统中,Altera为大部分通用接口提供了IP核,因此开发周期短,调试方便,体现了SOPC的灵活高效优势。
该设计主要从以下四个方面展开。对头皮电极采集的脑电信号进行了放大、滤波等预处理,以便开展后续的数字处理和存储工作。其二,利用SOPC开发工具实现了对模/数转换器的控制,编制了相应的硬件描述语言程序。其三,利用Matlab/DSP Builder进行DSP模块的设计,实现基于NiosⅡ32位CPU核的脑电信号数字FIR滤波器功能。其四,进行了FPGA外围接口的设计,包括ADC、SD卡、SDRAM等。
由于SOPC系统具有的可剪裁、调试方便、开发周期短的优势,在日后的工作中,可以再对这个系统进行扩展,添加多种功能模块,如网络和无限通讯模块,为远程医疗、家庭监护系统提供了一个新的技术方案。
EEG detection is an important method to know the brain status, assist in diagnosing brain disease, and evaluate therapy plan. Because of the time and environment constraints, using conventional EEG equipment to detect EEG signals often do not get the significative results in clinic. For this reason, researchers has been developing ambulatory electroencephalography system (AEEGs).
SOPC system is a flexible, efficient SOC solution based on FPGA, which is a system techniques co-design hardware and software. SOPC is the trend of semiconductor development. Functional modules such as processor, memory, I / O interfaces and so on are integrated into a programmable device,to compose a programmable SOC.
In this paper, we introduce a design scheme of AEEGS based on SOPC, EEG signals from scalp are amplified and filtered, and than convert EEG from analog signal to digital signal by means of a multi-channel ADC. We customize a SOPC system to create functional control signals, complete digital filtering and data storage in a SD card. We use DE2 development board as the hardware platform of the system, NiosⅡsoft-core as the processor in software part. Functional modules are integrated in the system in form of IP core. Altera provides common interface for most of the IP core, therefore, it costs a short development cycle, possesses the advantages of debugging convenience, flexibility and efficiency . The development is primarily unfolded by the following four aspects: first, we design amplifier and filter; Second, customize a SOPC system to create functional control signals, complete digital filtering and data storage; Third, design DSP module by use of Matlab / DSP Builder to realize FIR digital filter function of EEG based on NiosⅡ32 bit CPU core; Fourth, design the external interfaces of the FPGA, including the ADC, SD Card, SDRAM, etc.
Due to the advantages of cutting resistance, debugging convenience and short development cycle, in the future work, SOPC system could be extended, added multiple functional modules such as network and wireless communication modules. This provides a new technology solution for telemedicion and telecare as a family monitor system.
SOPC系统是一种基于FPGA的灵活、高效的SOC解决方案,是一种软硬件协同设计的系统设计技术。它将处理器、存储器、I/O口等系统设计需要的功能模块集成到一个可编程器件上,构成一个可编程的片上系统。SOPC是未来半导体的发展趋势。本论文设计了一个基于SOPC的脑电信号采集系统。由头皮电极采集脑电信号,并对其进行放大、滤波等预处理,再经过一个多通道模/数转换器,将其转换为数字信号。为了完成各项控制、数字滤波和数据存储,我们定制了一个SOPC系统。最终将处理过的数据保存在SD卡中供计算机进一步分析。本系统的硬件平台为DE2开发板,软件部分以NiosⅡ软核处理器为核心。功能模块以IP核的形式添加到系统中,Altera为大部分通用接口提供了IP核,因此开发周期短,调试方便,体现了SOPC的灵活高效优势。
该设计主要从以下四个方面展开。对头皮电极采集的脑电信号进行了放大、滤波等预处理,以便开展后续的数字处理和存储工作。其二,利用SOPC开发工具实现了对模/数转换器的控制,编制了相应的硬件描述语言程序。其三,利用Matlab/DSP Builder进行DSP模块的设计,实现基于NiosⅡ32位CPU核的脑电信号数字FIR滤波器功能。其四,进行了FPGA外围接口的设计,包括ADC、SD卡、SDRAM等。
由于SOPC系统具有的可剪裁、调试方便、开发周期短的优势,在日后的工作中,可以再对这个系统进行扩展,添加多种功能模块,如网络和无限通讯模块,为远程医疗、家庭监护系统提供了一个新的技术方案。
EEG detection is an important method to know the brain status, assist in diagnosing brain disease, and evaluate therapy plan. Because of the time and environment constraints, using conventional EEG equipment to detect EEG signals often do not get the significative results in clinic. For this reason, researchers has been developing ambulatory electroencephalography system (AEEGs).
SOPC system is a flexible, efficient SOC solution based on FPGA, which is a system techniques co-design hardware and software. SOPC is the trend of semiconductor development. Functional modules such as processor, memory, I / O interfaces and so on are integrated into a programmable device,to compose a programmable SOC.
In this paper, we introduce a design scheme of AEEGS based on SOPC, EEG signals from scalp are amplified and filtered, and than convert EEG from analog signal to digital signal by means of a multi-channel ADC. We customize a SOPC system to create functional control signals, complete digital filtering and data storage in a SD card. We use DE2 development board as the hardware platform of the system, NiosⅡsoft-core as the processor in software part. Functional modules are integrated in the system in form of IP core. Altera provides common interface for most of the IP core, therefore, it costs a short development cycle, possesses the advantages of debugging convenience, flexibility and efficiency . The development is primarily unfolded by the following four aspects: first, we design amplifier and filter; Second, customize a SOPC system to create functional control signals, complete digital filtering and data storage; Third, design DSP module by use of Matlab / DSP Builder to realize FIR digital filter function of EEG based on NiosⅡ32 bit CPU core; Fourth, design the external interfaces of the FPGA, including the ADC, SD Card, SDRAM, etc.
Due to the advantages of cutting resistance, debugging convenience and short development cycle, in the future work, SOPC system could be extended, added multiple functional modules such as network and wireless communication modules. This provides a new technology solution for telemedicion and telecare as a family monitor system.
引文
[1]余学飞.医学电子仪器原理与设计[M].广州:华南理工大学出版社,2000:104-105
[2]官金安,林家瑞.脑-机接口技术进展与挑战.中国医疗器械杂志[J],2004,28(3):157-164
[3]孟飞,黄军友,高小榕.基于脑机接口技术的上肢康复训练系统.中国康复医学杂志[J],2004,19(5):327-329
[4] P. R. Kennedy et al. Direct control of a computer from the human central nervous system, IEEE Trans. Rehab. Eng[J]., 2000,1(8):198-202
[5]邓亲恺.现代医学仪器设计原理[M].北京:科学出版社,2004:126-346
[6] Ferree,T.C.,P.L. Luu,G.S. Russell and D.M.Tucker. Scalp-electrode impedance and EEG infection risk Submitted to electroencephalography and Clinical Neurophysiology[J], 2001 20(4):35-37
[7] Xinbo Qian, Youngling Xu, Xiaoping Li.A CMOS Continuous-Time Low-Pass Notch Filter for EEG Systems[J],Analog Integrated Circuits and Signal Processing, 2005, 44:231-238
[8] Calvagno G,Ermani M,Rinaldo R et a1.A multire solution approach to spike detection in EEG.IEEE international Conference on Acoustica Speechand Singnal Processing, Turkey, 2000,128-133
[9] Cincotti F,Mattia D,Babiloni C,et al. The use of EEG modifrcations due to motor imagery for brain computer interfaces.IEEE Trans Rehab Eng[J],2003,11(2):25-28
[10] Badillo L,Leija L,Valentino A,et al.Sixteen Channels Holter to EEG Signal, Proceedings 19th International Conference, ChicagoUSA, IEEE/EMBS[J], 1997, 30(2):230-233
[11] Ali Bashashati,Borna Noureddin,et al.An Experimental Study to Investigate the Effects of a Motion Tracking Electromagnetic Sensor During EEG Data Acqusition,IEEE Transaction on Biomedical Engineering[J],2006 53(3):25-35
[12] Chan P K, Ng K A, Zhang X L. A cmos chopper-stabilized differential difference amplifier for biomedical intergrated circuits.The 47th IEEE international Midwest symposium on circuits and systems,2004,3:33-36
[13]姜宗义等.一种新型有源陷波器设计.中国生物医学工程学报[J],1997,16(4):323-326
[14] Ferdjallah M, Barr RE. A daptive digital notch filter design on the unit circle for the removal of powerline noise from biomedical signals.BME[J],1994,6:529-536
[15] Meeting AC,Vanrijin.The Isolation Mode Rejection Ratio in Bioelectioc Amplifiers.IEEE trans BME[J],1991,38(11):1154
[16] J.R.Wolpaw et al. Brain computer interface research at the Wadsworth Center,IEEE Trans.Rehab.Eng[J],2000,8(2):222-226
[17]童诗白.模拟电子技术基础[M],北京:高等教育出版社,1987:349-356
[18] Wolpaw J R et al.Brain computer interface technology:A review of the first international meeting.IEEE Trans Rehab Eng[J],2000,8(2):164
[19]汪国强等.SOPC技术与应用[M].北京:机械工业出版社,2006:200-240
[20]张志刚.FPGA与SOPC设计教程—DE2实践[M].西安:西安电子科技大学出版社,2007:324-360
[21] Rolf Enzler,Christian Plessl.Virtualizing Hardware with Multi-Context Reconfigurable Arrays Swiss Federal Institute of Technology[M],2005:30-34
[22] Yajuvendra Nagaonkar.FPGA-Based Experiment Platform for Hardware -Software Codesign and Hardware Emulation[M]. Brigham Young University,2006:234-239
[23] Aakko Kairus,et al.Bridging the Gap between Future Software and Hardware Engineers:A Case Study Using the Nios Soft-core Processor.33th ASEE/IEEE Frontiers in Education Conference,2003:120-127
[24] Jeff Garrison,IP Enabling SOPC-Technology Information,Electronic News[J], 2001,8(3):134-137
[25] Hall.T.S,Hanblem,J.O.System-on-a-programmable-chip development platforms in the classroom,Education,IEEE Transactions,2004,47(4):33-35
[26] H.Kalte,et.al. Dynamically Reconfigurable System-on-a-programmable-chip,10th Euromicro Workshop on Parallel.Distributed and Network-based Processing. January 9th-11th , Gra Canaria Island Spain,2002:339-345
[27]李兰英等.NiosⅡ嵌入式软核SOPC设计原理及应用[M],北京:北京航空航天大学出版社,2006:144-157
[28] ALTERA Inc,DE2 Development and Education Board User Manual,2006:167-169
[29] ALTERA Inc,SDRAM Controller with Avalon Interface,July 2003:200-230
[30]潘松,黄继业.SOPC技术实用教程[M].北京:清华大学出版社,2005:322-345
[31]曹伟军,聂洋.ADS8344和FPGA的高精度数据采集前端,新器件技术[J], 2007,(2):45-47
[32]夏宇闻.Verilog数字系统设计教程[M].北京:北京航空航天大学出版社,2003:78-89
[33]郭书军.嵌入式处理器原理及应用—NIOS系统设计和C语言编程[M].北京:清华大学出版社,2004:20-46,87-89
[34] ALTERA Inc.Nios II Software Developer’s Handbook,2005:36-44
[35] Palnikar S.Verilog HDL:A Guide to Digital Design and Synthesis[J].NewYork: Prentice Hall Ptr,2000:256-267
[36] ALTERA Inc,SOPC Builder datasheet,2003:145-148
[37]张晓燕,臧延新等. NiosⅡ嵌入式处理器设计大赛2005年优秀作品精选集[M].西安:西安电子科技大学出版社,2006:326-345
[38] (美)Uwe Meyer-Baese著,刘凌译.数字信号处理的FPGA实现[M].北京:清华大学出版社,2006:89-100
[39]王彬,戴厚德等.基于SOPC技术的多路并行ECG实时检测分析系统的设计[J].生物医学工程进展,2008,29(1):300-302
[40] ALTERA Inc,NiosⅡSoftware Developer’s Handbook, 2007:151-226
[2]官金安,林家瑞.脑-机接口技术进展与挑战.中国医疗器械杂志[J],2004,28(3):157-164
[3]孟飞,黄军友,高小榕.基于脑机接口技术的上肢康复训练系统.中国康复医学杂志[J],2004,19(5):327-329
[4] P. R. Kennedy et al. Direct control of a computer from the human central nervous system, IEEE Trans. Rehab. Eng[J]., 2000,1(8):198-202
[5]邓亲恺.现代医学仪器设计原理[M].北京:科学出版社,2004:126-346
[6] Ferree,T.C.,P.L. Luu,G.S. Russell and D.M.Tucker. Scalp-electrode impedance and EEG infection risk Submitted to electroencephalography and Clinical Neurophysiology[J], 2001 20(4):35-37
[7] Xinbo Qian, Youngling Xu, Xiaoping Li.A CMOS Continuous-Time Low-Pass Notch Filter for EEG Systems[J],Analog Integrated Circuits and Signal Processing, 2005, 44:231-238
[8] Calvagno G,Ermani M,Rinaldo R et a1.A multire solution approach to spike detection in EEG.IEEE international Conference on Acoustica Speechand Singnal Processing, Turkey, 2000,128-133
[9] Cincotti F,Mattia D,Babiloni C,et al. The use of EEG modifrcations due to motor imagery for brain computer interfaces.IEEE Trans Rehab Eng[J],2003,11(2):25-28
[10] Badillo L,Leija L,Valentino A,et al.Sixteen Channels Holter to EEG Signal, Proceedings 19th International Conference, ChicagoUSA, IEEE/EMBS[J], 1997, 30(2):230-233
[11] Ali Bashashati,Borna Noureddin,et al.An Experimental Study to Investigate the Effects of a Motion Tracking Electromagnetic Sensor During EEG Data Acqusition,IEEE Transaction on Biomedical Engineering[J],2006 53(3):25-35
[12] Chan P K, Ng K A, Zhang X L. A cmos chopper-stabilized differential difference amplifier for biomedical intergrated circuits.The 47th IEEE international Midwest symposium on circuits and systems,2004,3:33-36
[13]姜宗义等.一种新型有源陷波器设计.中国生物医学工程学报[J],1997,16(4):323-326
[14] Ferdjallah M, Barr RE. A daptive digital notch filter design on the unit circle for the removal of powerline noise from biomedical signals.BME[J],1994,6:529-536
[15] Meeting AC,Vanrijin.The Isolation Mode Rejection Ratio in Bioelectioc Amplifiers.IEEE trans BME[J],1991,38(11):1154
[16] J.R.Wolpaw et al. Brain computer interface research at the Wadsworth Center,IEEE Trans.Rehab.Eng[J],2000,8(2):222-226
[17]童诗白.模拟电子技术基础[M],北京:高等教育出版社,1987:349-356
[18] Wolpaw J R et al.Brain computer interface technology:A review of the first international meeting.IEEE Trans Rehab Eng[J],2000,8(2):164
[19]汪国强等.SOPC技术与应用[M].北京:机械工业出版社,2006:200-240
[20]张志刚.FPGA与SOPC设计教程—DE2实践[M].西安:西安电子科技大学出版社,2007:324-360
[21] Rolf Enzler,Christian Plessl.Virtualizing Hardware with Multi-Context Reconfigurable Arrays Swiss Federal Institute of Technology[M],2005:30-34
[22] Yajuvendra Nagaonkar.FPGA-Based Experiment Platform for Hardware -Software Codesign and Hardware Emulation[M]. Brigham Young University,2006:234-239
[23] Aakko Kairus,et al.Bridging the Gap between Future Software and Hardware Engineers:A Case Study Using the Nios Soft-core Processor.33th ASEE/IEEE Frontiers in Education Conference,2003:120-127
[24] Jeff Garrison,IP Enabling SOPC-Technology Information,Electronic News[J], 2001,8(3):134-137
[25] Hall.T.S,Hanblem,J.O.System-on-a-programmable-chip development platforms in the classroom,Education,IEEE Transactions,2004,47(4):33-35
[26] H.Kalte,et.al. Dynamically Reconfigurable System-on-a-programmable-chip,10th Euromicro Workshop on Parallel.Distributed and Network-based Processing. January 9th-11th , Gra Canaria Island Spain,2002:339-345
[27]李兰英等.NiosⅡ嵌入式软核SOPC设计原理及应用[M],北京:北京航空航天大学出版社,2006:144-157
[28] ALTERA Inc,DE2 Development and Education Board User Manual,2006:167-169
[29] ALTERA Inc,SDRAM Controller with Avalon Interface,July 2003:200-230
[30]潘松,黄继业.SOPC技术实用教程[M].北京:清华大学出版社,2005:322-345
[31]曹伟军,聂洋.ADS8344和FPGA的高精度数据采集前端,新器件技术[J], 2007,(2):45-47
[32]夏宇闻.Verilog数字系统设计教程[M].北京:北京航空航天大学出版社,2003:78-89
[33]郭书军.嵌入式处理器原理及应用—NIOS系统设计和C语言编程[M].北京:清华大学出版社,2004:20-46,87-89
[34] ALTERA Inc.Nios II Software Developer’s Handbook,2005:36-44
[35] Palnikar S.Verilog HDL:A Guide to Digital Design and Synthesis[J].NewYork: Prentice Hall Ptr,2000:256-267
[36] ALTERA Inc,SOPC Builder datasheet,2003:145-148
[37]张晓燕,臧延新等. NiosⅡ嵌入式处理器设计大赛2005年优秀作品精选集[M].西安:西安电子科技大学出版社,2006:326-345
[38] (美)Uwe Meyer-Baese著,刘凌译.数字信号处理的FPGA实现[M].北京:清华大学出版社,2006:89-100
[39]王彬,戴厚德等.基于SOPC技术的多路并行ECG实时检测分析系统的设计[J].生物医学工程进展,2008,29(1):300-302
[40] ALTERA Inc,NiosⅡSoftware Developer’s Handbook, 2007:151-226