无线通信中数字中频接收系统研究
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摘要
随着通信技术的飞速发展，无线通信正向着综合化、高速化和个人化的方向发展。但是，目前通信网中，存在多种通信标准，这就对通信设备的兼容性提出了越来越高的要求。而软件无线电(Software Radio，SR)的提出，为解决这一问题提供了新的思路，SR也因此成为研究的焦点，它使通信系统摆脱了面向应用的设计思想，被认为是无线通信从模拟到数字，从固定到移动之后的又一次突破。
软件无线电是一种无线通信新的体系结构，其中的中频部分有别于传统通信系统，完全实现了数字化，从而可以利用先进而成熟的数字信号处理(Digital Signal Processing，DSP)技术来实现系统，克服了传统模拟方法的缺点。数字信号处理的实现有多种方法，比如传统数字信号处理器(Digital Signal Processors，DSPs)，而运用FPGA／CPLD实现，由于可编程器件的可编程性，使得系统的实现更加灵活，可以从软件的高度来实现硬件。
本文的焦点正是如何高效的实现无线通信接收系统中的数字中频部分。主要研究的内容包括：
1．DSP中常用的算法，并结合FPGA的特点，重点仿真分析；
2．数字解调技术及其实现。比较了各种解调技术，分析了它们的优势和劣势，就中频系统提出了实现的方法，并进行仿真验证；
3．研究了多抽样率技术。重点研究了抽取技术，并将这种技术应用于数字中频系统，设计了CIC滤波器和半带滤波器；
4．运用先进的仿真工具matlab，maxplus Ⅱ等对数字中频系统的核心部分进行仿真；
5．重点研究了如何在FPGA中，以较小硬件规模，较快速度来实现系统。
本文取得的一些成果有：
1．在分析各种数字解调技术的基础上，应用CORDIC算法较好地实现了数字解调；
2．应用剪除理论实现多级CIC滤波器，进一步提高了硬件效率和运行速度；
3．在半波带滤波器和CIC滤波器的基础上设计了多级抽取系统。
With the rapid development of communication technology, wireless communication becomes more and more integrated and individualized. Its speed becomes higher and higher. Now there are several communication standards in current communication system. It is difficult to make these standards be compatible. As a good solution to this problem, Software Radio(SR) has became the focus of research. Software Radio makes the communication system break away from application-oriented design method. Therefore SR has been recognized as the next major leap forward in wireless communication.
Softwar Radio is a new architecture of wireless communication. The Intermediate Frequency (IF) part in SR is different from that in tranditional communication system. IF is digitized totally in SR. As a result, we can use advanced and mature Digital Signal Processing(DSP) technology to realize system. Furthermore digitalization can conquer some disadvantages in analog IF system. There are several methods to implement DSP, such as using traditional Digtial Signal Processors(DSPs). When it comes to FPGA/CPLD, due to its programmability, system implementation with it is flexible. Therefore engineers can design hardware system with software method.
The focus of this paper is how to implement the digital IF in wireless receiver efficiently.The main content includes:
1. Introduce general algorithms in DSP and simulate the key algorithms with FPGA.
2. Research the digital quadrature demodulation. Firstly analyze several demodulation methods and give out their advantages and disadvantages. Then bring up a effecient method to implement digital IF system and simulate it with EDA tools.
3. Research multi-rate theory. The emphasis of research is decimation technology. Design CIC filters and Halfband filters with this theroy.
4. Simulate the core parts of digital IF system with software Matlab and Maxplus.
5. Pay most attention to the implementation of digital IF system with smaller scale and higher speed in FPGA.
The original contributions in dissertation include:
1. After analyzing several methods of digital demodulation, implement the digital demodulation more efficiently.
2. Apply truncation theory and design multi-stage CIC filters with higher efficiency.
3. Design multi-stage decimation system on the basis of Halfband filters and CIC filters.
软件无线电是一种无线通信新的体系结构，其中的中频部分有别于传统通信系统，完全实现了数字化，从而可以利用先进而成熟的数字信号处理(Digital Signal Processing，DSP)技术来实现系统，克服了传统模拟方法的缺点。数字信号处理的实现有多种方法，比如传统数字信号处理器(Digital Signal Processors，DSPs)，而运用FPGA／CPLD实现，由于可编程器件的可编程性，使得系统的实现更加灵活，可以从软件的高度来实现硬件。
本文的焦点正是如何高效的实现无线通信接收系统中的数字中频部分。主要研究的内容包括：
1．DSP中常用的算法，并结合FPGA的特点，重点仿真分析；
2．数字解调技术及其实现。比较了各种解调技术，分析了它们的优势和劣势，就中频系统提出了实现的方法，并进行仿真验证；
3．研究了多抽样率技术。重点研究了抽取技术，并将这种技术应用于数字中频系统，设计了CIC滤波器和半带滤波器；
4．运用先进的仿真工具matlab，maxplus Ⅱ等对数字中频系统的核心部分进行仿真；
5．重点研究了如何在FPGA中，以较小硬件规模，较快速度来实现系统。
本文取得的一些成果有：
1．在分析各种数字解调技术的基础上，应用CORDIC算法较好地实现了数字解调；
2．应用剪除理论实现多级CIC滤波器，进一步提高了硬件效率和运行速度；
3．在半波带滤波器和CIC滤波器的基础上设计了多级抽取系统。
With the rapid development of communication technology, wireless communication becomes more and more integrated and individualized. Its speed becomes higher and higher. Now there are several communication standards in current communication system. It is difficult to make these standards be compatible. As a good solution to this problem, Software Radio(SR) has became the focus of research. Software Radio makes the communication system break away from application-oriented design method. Therefore SR has been recognized as the next major leap forward in wireless communication.
Softwar Radio is a new architecture of wireless communication. The Intermediate Frequency (IF) part in SR is different from that in tranditional communication system. IF is digitized totally in SR. As a result, we can use advanced and mature Digital Signal Processing(DSP) technology to realize system. Furthermore digitalization can conquer some disadvantages in analog IF system. There are several methods to implement DSP, such as using traditional Digtial Signal Processors(DSPs). When it comes to FPGA/CPLD, due to its programmability, system implementation with it is flexible. Therefore engineers can design hardware system with software method.
The focus of this paper is how to implement the digital IF in wireless receiver efficiently.The main content includes:
1. Introduce general algorithms in DSP and simulate the key algorithms with FPGA.
2. Research the digital quadrature demodulation. Firstly analyze several demodulation methods and give out their advantages and disadvantages. Then bring up a effecient method to implement digital IF system and simulate it with EDA tools.
3. Research multi-rate theory. The emphasis of research is decimation technology. Design CIC filters and Halfband filters with this theroy.
4. Simulate the core parts of digital IF system with software Matlab and Maxplus.
5. Pay most attention to the implementation of digital IF system with smaller scale and higher speed in FPGA.
The original contributions in dissertation include:
1. After analyzing several methods of digital demodulation, implement the digital demodulation more efficiently.
2. Apply truncation theory and design multi-stage CIC filters with higher efficiency.
3. Design multi-stage decimation system on the basis of Halfband filters and CIC filters.
引文
[1] O.Spaniol, Computer Arithmetic: Logic and Design (John Wiley & Sons, New York, 1981)
[2] I.Koren , Computer Arithmetic Algorithms (Prentice Hall, Englewood Cliffs, New Jersey, 1993)
[3] Earl E.Swartzlander, Computer Arithmetic (Dowden, Hutchinson and Ross, Inc., Stroudsburg, Pennysylvania, 1980)
[4] K.Hwang, Computer Arithmetic: Principles, Architecture and Design (John Wiley & Sons, New York, 1979)
[5] C.Rader, Discrete Convolutions via Mersenne Transforms, IEEE Transactions on Computers C-21, 1269-1273(1972)
[6] Leibowitz, A Simplified Binary Arithmetic for the Fermat Number Transform, IEEE Transactions on Acoustics, Speech and Signal Processing 24, 356-359(1976)
[7] M.Soderstrand , W.Jenkins , G.Jullien , F.Taylor Residue Number System Arithmetic: Modern Applications in Digital Signal Processing, IEEE Press Reprint Series (IEEE Press, New York, 1986)
[8] N.Szabo , R.Tanaka Residue Arithmetic and Its Applications to Computer Technolodgy(McGraw-Hill, New York, 1967)
[9] W.K.Jenkins, B.J.Leon, The Use of Residue Number Systems in the Design of Finite Impulse
Response Digital Filters, IEEE Trans. Circuit Syst., vol. CAS-24, pp.191-201, Apr. 1977
[10] B.D.Tseng, G.A.Jullien, W.C.Miller, Implementation of FFT Structures Using the Residue Number System, IEEE Trans. Computers, vol. C-28, pp.831-845, Nov. 1979
[11] F.J.Taylor, C.H.Huang, A Comparison of DFT Algorithms Using a Residue Architecture, Computer and Elect. Eng., Vol.8 ,No.3, pp.161-171, Sept. 1981
[12] M.A.Soderstrand, A High Speed Low-cost Reeursive Digital Filter Using Residue Number Arithmetic, Proc. IEEE, Vol.65, pp.1065-1067
[13] D.F.Fraser , N.J.Bryg , An Adapative Digital Processor Based on the Residue Number System, Proc AIAA2~(nt) Computers in Aerospace Conf., Los Angeles, CA, Oct. 1979
[14] M.A.Soderstrand, C.Vernia, Microprocessor Controlled Development System for Adaptive Filtering Using Parallel Processing and Residue Number Arithmetic, Intern. J.Mini and Micro Computers, Vol.3, No.3, pp. 39-43, Sept.1981
[15] G.A.Jullien, W.C.Miller, J.J.Soltis, A.Baraniecka, B.D.Tseng, Hardware Realization of Digital Signal Processing Elements Using the Residue Number System, in Proc. 1977 Int. Conf. Acoustic Speech and Signal Processing, Apr. 1972.
[16] M.A.Soderstrand, C.Vernia, A High-speed Low-cost Modulo P Multiplier with RNS Arithmetic Applications, Proc. IEEE, Vol.68, pp.524-532, Apr. 1980
[17] V.Hamann, M.Sprachrnann, Fast Residual Arithmetics with FPGAs, in Proceedings of the Workshop on Design Methodologies for Microelectronics Smolenice Castle, Slovakia(1995), pp.253-255
[18] G.Julien, Residue Number Scaling and Other Operations Using ROM Arrays , IEEE Transactions on Communications 27, 325-336(1978)
[19] A.Croisier, D.Esteban, M.Levilion, V.Rizo, Digital Filter for PCM Encoded Signals, US Patent No.3777130 (1973)
[20] A.Peled, B.Liu, A New Realization of Digital Filters, IEEE Transactions on Acoustics, Speech and Signal Processing 22(6), 456-462(1974)
[21] K.Yiu, Oil Sign-Bit. Assignment for a Vector Multiplier, Proceedings of the IEEE 64, 372-373(1976)
[22] K.Kammeyer, Quantization Error on the Distributed Arithmetic, IEEE Transactions on Circuits and Systems 24(12), 681-689(1981)
[23] F.Taylor, An Analysis of the Distributed-Arithmetic Digital Filter, IEEE Transactions on Acoustics, Speech and Signal Processings 35(5), 1165-1170(1986)
[24] F.Taylor, Digital Filter Design Handbook (Marcel Dekker, New Youk, 1983)
[25] H.Nussbaumer, Fast Fourier Transform and Convolution Algorithms (Springer, Heidelberg, 1990)
[26] H.Nyquist, Certain Topics in Telegraph Transmission Theory, AIEE Transactions, Vol.47, pp.617-644(1928)
[27] D.Gabor, Theory of Communication, Journal of the Institution of Electrical Engineers, 93:429-459(1946)
[2] I.Koren , Computer Arithmetic Algorithms (Prentice Hall, Englewood Cliffs, New Jersey, 1993)
[3] Earl E.Swartzlander, Computer Arithmetic (Dowden, Hutchinson and Ross, Inc., Stroudsburg, Pennysylvania, 1980)
[4] K.Hwang, Computer Arithmetic: Principles, Architecture and Design (John Wiley & Sons, New York, 1979)
[5] C.Rader, Discrete Convolutions via Mersenne Transforms, IEEE Transactions on Computers C-21, 1269-1273(1972)
[6] Leibowitz, A Simplified Binary Arithmetic for the Fermat Number Transform, IEEE Transactions on Acoustics, Speech and Signal Processing 24, 356-359(1976)
[7] M.Soderstrand , W.Jenkins , G.Jullien , F.Taylor Residue Number System Arithmetic: Modern Applications in Digital Signal Processing, IEEE Press Reprint Series (IEEE Press, New York, 1986)
[8] N.Szabo , R.Tanaka Residue Arithmetic and Its Applications to Computer Technolodgy(McGraw-Hill, New York, 1967)
[9] W.K.Jenkins, B.J.Leon, The Use of Residue Number Systems in the Design of Finite Impulse
Response Digital Filters, IEEE Trans. Circuit Syst., vol. CAS-24, pp.191-201, Apr. 1977
[10] B.D.Tseng, G.A.Jullien, W.C.Miller, Implementation of FFT Structures Using the Residue Number System, IEEE Trans. Computers, vol. C-28, pp.831-845, Nov. 1979
[11] F.J.Taylor, C.H.Huang, A Comparison of DFT Algorithms Using a Residue Architecture, Computer and Elect. Eng., Vol.8 ,No.3, pp.161-171, Sept. 1981
[12] M.A.Soderstrand, A High Speed Low-cost Reeursive Digital Filter Using Residue Number Arithmetic, Proc. IEEE, Vol.65, pp.1065-1067
[13] D.F.Fraser , N.J.Bryg , An Adapative Digital Processor Based on the Residue Number System, Proc AIAA2~(nt) Computers in Aerospace Conf., Los Angeles, CA, Oct. 1979
[14] M.A.Soderstrand, C.Vernia, Microprocessor Controlled Development System for Adaptive Filtering Using Parallel Processing and Residue Number Arithmetic, Intern. J.Mini and Micro Computers, Vol.3, No.3, pp. 39-43, Sept.1981
[15] G.A.Jullien, W.C.Miller, J.J.Soltis, A.Baraniecka, B.D.Tseng, Hardware Realization of Digital Signal Processing Elements Using the Residue Number System, in Proc. 1977 Int. Conf. Acoustic Speech and Signal Processing, Apr. 1972.
[16] M.A.Soderstrand, C.Vernia, A High-speed Low-cost Modulo P Multiplier with RNS Arithmetic Applications, Proc. IEEE, Vol.68, pp.524-532, Apr. 1980
[17] V.Hamann, M.Sprachrnann, Fast Residual Arithmetics with FPGAs, in Proceedings of the Workshop on Design Methodologies for Microelectronics Smolenice Castle, Slovakia(1995), pp.253-255
[18] G.Julien, Residue Number Scaling and Other Operations Using ROM Arrays , IEEE Transactions on Communications 27, 325-336(1978)
[19] A.Croisier, D.Esteban, M.Levilion, V.Rizo, Digital Filter for PCM Encoded Signals, US Patent No.3777130 (1973)
[20] A.Peled, B.Liu, A New Realization of Digital Filters, IEEE Transactions on Acoustics, Speech and Signal Processing 22(6), 456-462(1974)
[21] K.Yiu, Oil Sign-Bit. Assignment for a Vector Multiplier, Proceedings of the IEEE 64, 372-373(1976)
[22] K.Kammeyer, Quantization Error on the Distributed Arithmetic, IEEE Transactions on Circuits and Systems 24(12), 681-689(1981)
[23] F.Taylor, An Analysis of the Distributed-Arithmetic Digital Filter, IEEE Transactions on Acoustics, Speech and Signal Processings 35(5), 1165-1170(1986)
[24] F.Taylor, Digital Filter Design Handbook (Marcel Dekker, New Youk, 1983)
[25] H.Nussbaumer, Fast Fourier Transform and Convolution Algorithms (Springer, Heidelberg, 1990)
[26] H.Nyquist, Certain Topics in Telegraph Transmission Theory, AIEE Transactions, Vol.47, pp.617-644(1928)
[27] D.Gabor, Theory of Communication, Journal of the Institution of Electrical Engineers, 93:429-459(1946)