数字示波器中高速实时数据处理技术的研究
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摘要
数字示波器是集数据采集、A/D转换以及软件编程等一系列的技术而制造出来的高性能示波器。能为用户提供波形触发、存储、显示、测量、波形数据分析处理等功能。一台好的数字示波器,不仅要有较高的采样率,以便能很好地重建原信号,还需要有很强地波形分析的能力。要做到这些,都得靠数字信号处理技术在数字示波器的运用。而随着对数字示波器性能的要求逐渐提高,DSP处理器的运算速度渐渐不能满足要求。于是,基于硬件的高速数据处理成为了数字示波器一个新的研究方向。本文主要介绍了在FPGA中实现数字信号处理技术中的插值算法、FFT算法以及运用DSP技术来校正误差。
插值算法对于数字示波器来说,是必须采用的数字信号处理技术,在以往的研究中,都是用DSP处理器来实现的,速度渐渐不能满足要求。插值算法包括正弦插值,线性插值等。本文采用的是正弦插值,是基于低通滤波器来实现的,根据数字示波器的时基档来确定需要插值的倍数,从而根据正弦插值的公式计算出系数,利用FPGA中丰富的乘法器加法器资源来编程实现。
FFT算法在数字示波器中,主要用于计算波形的频谱,便于分析波形细节。本文设计了1024个精度为8位的采样点的FFT运算,在DSP处理器中运算,效率太低,所以移植到FPGA中来实现。本文设计FFT算法的流程为:首先利用对Xilinx公司软件ISE自带的FFT IP CORE进行端口设置,生成代码,再加入ISE工程,进行仿真,将仿真结果与Matlab中的仿真结果进行对比分析。
为了弥补国内数字示波器实时采样率的不足,采用时间交替并行采样技术,用多片相对低采样率的ADC并行采样拼合成高采样率。但由于工艺等原因,会造成通道失配误差,如偏置误差、增益误差和时延误差。本文提出一种综合校正方法,能同时校正三种误差,有效提高数字示波器的整机性能。
由于研究的深度和广度不足,所以研究成果离国际先进水平还有很大一段距离,文章最后对下一步的工作进行了展望。
Digital oscilloscope is a high-performance oscilloscope which is created by a series of technologies ,such as a set of data acquisition, A / D conversion, software programming and so on . It is able to provide users with waveform trigger, storage, display, measurement, waveform data analysis and processing functions. A good digital oscilloscope, not only have a high sampling rate, to be able to rebuild the original signal very well, but also need to have a strong ability to analyze the waveform. To achieve the above these,it is have to rely on digital signal processing technology‘s use in the digital oscilloscope. With the gradual increase in demand of digital oscilloscope performance, DSP processor’s computing speed gradually can not meet the requirements. Therefore, hardware-based high-speed data processing become a new research direction of digital oscilloscope .This paper describes using the FPGA to implement digital signal processing techniques ,such as the interpolation algorithm, FFT algorithm, as well as the use of DSP technology to correct errors.
For digital oscilloscopes, Interpolation algorithm is a digital signal processing technology which is must be used, in previous studies, Interpolation algorithm is achieved with the DSP processor, the speed gradually does not meet the requirements. Interpolation algorithm, including sinusoidal interpolation, linear interpolation and so on. In this paper, the sine interpolation is used to achieve,which is based on the low-pass filter, according to time-base files of the digital oscilloscope to determine the need for interpolation of multiple,then according to the formula of sine interpolation to calculate the coefficient,using the rich resources of FPGA ,such as multipliers and adder to programming.
In the digital oscilloscope, mainly use FFT algorithm to calculate the wave spectrum, to facilitate analysis of the details of the waveform. This paper is designed for 8-bit precision of 1024 sample points FFT operation in the FPGA to achieve,because the efficiency of DSP processor operation is too low. The process of FFT algorithm designed in this paper as follows: First, set the port of FFT IP CORE which is built-in Xilinx's ISE software,generate code, and then join the ISE project, simulation, compared this results with the simulation results in Matlab,then analyzed.
In order to meet the shortage of real-time sampling rate of domestic Digital oscilloscope, using a parallel time-interleaved sampling technique, using multi-chip relatively low sampling rate ADC parallel sampling together such a high sampling rate. However, because of technology and other factors, it will cause channel mismatch errors, such as offset error, gain error, time delay error. This paper presents a comprehensive correction method, three kinds of errors can be corrected at the same time, improve the overall performance of digital oscilloscope effectively .
Because the research is lack of depth and breadth , there is a great distance between research results of the article and the international advanced level, Finally, the next step was prospected.
插值算法对于数字示波器来说,是必须采用的数字信号处理技术,在以往的研究中,都是用DSP处理器来实现的,速度渐渐不能满足要求。插值算法包括正弦插值,线性插值等。本文采用的是正弦插值,是基于低通滤波器来实现的,根据数字示波器的时基档来确定需要插值的倍数,从而根据正弦插值的公式计算出系数,利用FPGA中丰富的乘法器加法器资源来编程实现。
FFT算法在数字示波器中,主要用于计算波形的频谱,便于分析波形细节。本文设计了1024个精度为8位的采样点的FFT运算,在DSP处理器中运算,效率太低,所以移植到FPGA中来实现。本文设计FFT算法的流程为:首先利用对Xilinx公司软件ISE自带的FFT IP CORE进行端口设置,生成代码,再加入ISE工程,进行仿真,将仿真结果与Matlab中的仿真结果进行对比分析。
为了弥补国内数字示波器实时采样率的不足,采用时间交替并行采样技术,用多片相对低采样率的ADC并行采样拼合成高采样率。但由于工艺等原因,会造成通道失配误差,如偏置误差、增益误差和时延误差。本文提出一种综合校正方法,能同时校正三种误差,有效提高数字示波器的整机性能。
由于研究的深度和广度不足,所以研究成果离国际先进水平还有很大一段距离,文章最后对下一步的工作进行了展望。
Digital oscilloscope is a high-performance oscilloscope which is created by a series of technologies ,such as a set of data acquisition, A / D conversion, software programming and so on . It is able to provide users with waveform trigger, storage, display, measurement, waveform data analysis and processing functions. A good digital oscilloscope, not only have a high sampling rate, to be able to rebuild the original signal very well, but also need to have a strong ability to analyze the waveform. To achieve the above these,it is have to rely on digital signal processing technology‘s use in the digital oscilloscope. With the gradual increase in demand of digital oscilloscope performance, DSP processor’s computing speed gradually can not meet the requirements. Therefore, hardware-based high-speed data processing become a new research direction of digital oscilloscope .This paper describes using the FPGA to implement digital signal processing techniques ,such as the interpolation algorithm, FFT algorithm, as well as the use of DSP technology to correct errors.
For digital oscilloscopes, Interpolation algorithm is a digital signal processing technology which is must be used, in previous studies, Interpolation algorithm is achieved with the DSP processor, the speed gradually does not meet the requirements. Interpolation algorithm, including sinusoidal interpolation, linear interpolation and so on. In this paper, the sine interpolation is used to achieve,which is based on the low-pass filter, according to time-base files of the digital oscilloscope to determine the need for interpolation of multiple,then according to the formula of sine interpolation to calculate the coefficient,using the rich resources of FPGA ,such as multipliers and adder to programming.
In the digital oscilloscope, mainly use FFT algorithm to calculate the wave spectrum, to facilitate analysis of the details of the waveform. This paper is designed for 8-bit precision of 1024 sample points FFT operation in the FPGA to achieve,because the efficiency of DSP processor operation is too low. The process of FFT algorithm designed in this paper as follows: First, set the port of FFT IP CORE which is built-in Xilinx's ISE software,generate code, and then join the ISE project, simulation, compared this results with the simulation results in Matlab,then analyzed.
In order to meet the shortage of real-time sampling rate of domestic Digital oscilloscope, using a parallel time-interleaved sampling technique, using multi-chip relatively low sampling rate ADC parallel sampling together such a high sampling rate. However, because of technology and other factors, it will cause channel mismatch errors, such as offset error, gain error, time delay error. This paper presents a comprehensive correction method, three kinds of errors can be corrected at the same time, improve the overall performance of digital oscilloscope effectively .
Because the research is lack of depth and breadth , there is a great distance between research results of the article and the international advanced level, Finally, the next step was prospected.
引文
[1] Bob Myers, A Practical Look at Calibrating High-Speed DSOs, Evaluation Engineering, 1997(5), pp:114~118
[2]向川云.一种并行架构的数字存储示波器研究与设计. [硕士学位论文].成都:电子科技大学自动化工程学院, 2009
[3]程佩青,数字信号处理教程[M].北京:清华大学出版社,2001
[4]胡广书.数字信号处理.北京:清华大学出版社,1997
[5]胡广书.数字信号处理—理论、算法与实现(第二版).北京:清华大学出版社,2003: 260~261
[6]盛森芝,强明数字信号处理技术发展概要.数据采集与处理, 1996, 11(2),PP:160~161
[7] Huiqing Pan, Shulin Tian. Time Delay Estimation for Parallel Sampling Systems. ICCCAS'08, 2008
[8]纪志成,高春能. FPGA数字信号处理设计教程—System Generator入门与提高.西安:西安电子科技大学出版社,2008.2
[9]美国泰克公司(Tektronix, Inc.)2001年版权所有,深入了解示波器, www.tektronix.com
[10]田耘,徐文波等. ISE Design Suite 10.x FPGA开发指南(逻辑设计篇) [M].人民邮电出版社, 2008:14~18
[11]王钿,卓兴旺.基于Verilog HDL的数字系统应用设计.国防工业出版社,2006
[12]张惠.数字存储示波器中的数字信号处理研究.[硕士学位论文].南京:东南大学信息与信号处理专业,2006.
[13] R.E.Goehiere and L.Rrabiner,Interpolation and ecimation of digital signal”S[J]A Tutorial Review,Proe,IEEE,69(3), Mareh. 1981
[14]杨小牛,楼才义,徐建良.软件无线电原理与应用.北京,电子工业出版社,2001
[15] S. He, M Torkelson. Design and implementation of a 1024-point Pipeline FFT CustomIntegrated Circuits Conference, pp. 131~134, Ssnta Clara, CA,May 1998
[16] JAE SUNG LEE, MYUNG H.SUNWOO. Design of new DSP Instructions and Their Hardware Architecture for High-Speed FFT, Journal of VLSI Signal Processing,2003, Vol.33,247~254
[17]张傲华.基于FPGA的高速实时信号处理技术研究. [硕士学位论文].成都:电子科技大学生物医学工程, 2005
[18]邓学禹.基于FPGA的1024点流水线工作方式的FFT实现.[硕士学位论文].成都:电子科技大学信号与信息处理, 2005
[19]韩颖,王旭,吴嗣亮. FPGA实现高速FFT处理器的设计.电讯技术,2003, No.2: 74~78
[20] Xilinx,Virtex-5 FPGA XtremeDSP设计注意事项用户指南. 2008.4
[21] Xilinx,Fast Fourier Transform v6.0 Product Specification,2008.9
[22] S K Mitra, A Petraglia. Analysis of mismatch effects among A/D converters in a time-interleaved waveform digitizer [J]. IEEE Transactions on Instrumentation and Measurement, vol. 40, no. 5, October 1991: 831-835
[23] Vogel, C., D. Draxelmayr, et al. Spectral shaping of timing mismatches in time-interleaved analog-to-digital converters [J]. Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
[24] J M Pereira, PMB Silva, A M C Serra.An FFT-based Method to Evaluate and Compensate Gain and Offset Errors of Interleaved ADC Systems[J].IEEE Transactions on Instrumentation and Measurement, vol.53 (2), 2004
[25] J Elbornsson,F Gustafsson,J-E Eklund.Blind adaptive equalization of mismatch errors in a time-interleaved A/D converter system[J].IEEE Transactions on Circuits and Systems I:Regular Papers-Jan.2004-51:151-158.
[26] Jin Huawen.E K F Lee.A digital-background calibration technique for minimizing timing-error efects in time-interleaved ADCs[J].IEEE Transactions on Circuits and SystemsⅡ:Analog and Digital Signal Processing,July 2000,47:603-613.
[27] S M Jama1.Fu Daihong.M P singh.et a1.Calibration of sample-time error in a two channel time interleaved analog to digital converter[J]. IEEE Transact-ions on Circuits and Systems I:Regular Papers,Jan.2004,51:130-139.
[2]向川云.一种并行架构的数字存储示波器研究与设计. [硕士学位论文].成都:电子科技大学自动化工程学院, 2009
[3]程佩青,数字信号处理教程[M].北京:清华大学出版社,2001
[4]胡广书.数字信号处理.北京:清华大学出版社,1997
[5]胡广书.数字信号处理—理论、算法与实现(第二版).北京:清华大学出版社,2003: 260~261
[6]盛森芝,强明数字信号处理技术发展概要.数据采集与处理, 1996, 11(2),PP:160~161
[7] Huiqing Pan, Shulin Tian. Time Delay Estimation for Parallel Sampling Systems. ICCCAS'08, 2008
[8]纪志成,高春能. FPGA数字信号处理设计教程—System Generator入门与提高.西安:西安电子科技大学出版社,2008.2
[9]美国泰克公司(Tektronix, Inc.)2001年版权所有,深入了解示波器, www.tektronix.com
[10]田耘,徐文波等. ISE Design Suite 10.x FPGA开发指南(逻辑设计篇) [M].人民邮电出版社, 2008:14~18
[11]王钿,卓兴旺.基于Verilog HDL的数字系统应用设计.国防工业出版社,2006
[12]张惠.数字存储示波器中的数字信号处理研究.[硕士学位论文].南京:东南大学信息与信号处理专业,2006.
[13] R.E.Goehiere and L.Rrabiner,Interpolation and ecimation of digital signal”S[J]A Tutorial Review,Proe,IEEE,69(3), Mareh. 1981
[14]杨小牛,楼才义,徐建良.软件无线电原理与应用.北京,电子工业出版社,2001
[15] S. He, M Torkelson. Design and implementation of a 1024-point Pipeline FFT CustomIntegrated Circuits Conference, pp. 131~134, Ssnta Clara, CA,May 1998
[16] JAE SUNG LEE, MYUNG H.SUNWOO. Design of new DSP Instructions and Their Hardware Architecture for High-Speed FFT, Journal of VLSI Signal Processing,2003, Vol.33,247~254
[17]张傲华.基于FPGA的高速实时信号处理技术研究. [硕士学位论文].成都:电子科技大学生物医学工程, 2005
[18]邓学禹.基于FPGA的1024点流水线工作方式的FFT实现.[硕士学位论文].成都:电子科技大学信号与信息处理, 2005
[19]韩颖,王旭,吴嗣亮. FPGA实现高速FFT处理器的设计.电讯技术,2003, No.2: 74~78
[20] Xilinx,Virtex-5 FPGA XtremeDSP设计注意事项用户指南. 2008.4
[21] Xilinx,Fast Fourier Transform v6.0 Product Specification,2008.9
[22] S K Mitra, A Petraglia. Analysis of mismatch effects among A/D converters in a time-interleaved waveform digitizer [J]. IEEE Transactions on Instrumentation and Measurement, vol. 40, no. 5, October 1991: 831-835
[23] Vogel, C., D. Draxelmayr, et al. Spectral shaping of timing mismatches in time-interleaved analog-to-digital converters [J]. Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
[24] J M Pereira, PMB Silva, A M C Serra.An FFT-based Method to Evaluate and Compensate Gain and Offset Errors of Interleaved ADC Systems[J].IEEE Transactions on Instrumentation and Measurement, vol.53 (2), 2004
[25] J Elbornsson,F Gustafsson,J-E Eklund.Blind adaptive equalization of mismatch errors in a time-interleaved A/D converter system[J].IEEE Transactions on Circuits and Systems I:Regular Papers-Jan.2004-51:151-158.
[26] Jin Huawen.E K F Lee.A digital-background calibration technique for minimizing timing-error efects in time-interleaved ADCs[J].IEEE Transactions on Circuits and SystemsⅡ:Analog and Digital Signal Processing,July 2000,47:603-613.
[27] S M Jama1.Fu Daihong.M P singh.et a1.Calibration of sample-time error in a two channel time interleaved analog to digital converter[J]. IEEE Transact-ions on Circuits and Systems I:Regular Papers,Jan.2004,51:130-139.