3GPP LTE下行接收系统的数字信号处理与VLSI实现研究
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摘要
随着个人移动通信日新月异的发展,人们已经不满足于简单的语音通信。越来越多的业务如移动互联网,可视通话,流媒体,移动电视等,逐渐成为了市场上新的热点。在这些应用的促使下,移动通信技术正在向更高数据率的方向发展。从目前的发展来看,第三代合作计划(3rd Generation Partnership Project,3GPP)推出的长期演进技术(Long Term Evolution, LTE)以其高数据率、高频谱利用率和灵活性、低延迟、应用设备广泛等的特性在下一代移动通信标准的竞争中脱颖而出,成为准4G技术的主流标准。
作者在对3GPP LTE系统的发展历史及现状进行分析和调研的基础上,发现在3GPP LTE的推广和普及中存在着以下的挑战：1)移动终端的功耗和成本的降低。与3G的移动终端相比,LTE的移动终端需要进行在更高的工作频率上(LTE标准支持的最大信号带宽为20 MHz)进行更多的数字信号处理(Digital Signal Processing, DSP)操作,如快速傅里叶变换(FFT)和多输入多输出(MIMO)信号检测等。这些操作会导致LTE移动终端在DSP部分消耗更多的能量。对于以手持式设备和消费电子产品为主要应用的技术而言,降低移动终端中DSP部分的功耗和运算复杂度具有重要意义。2)对多模多协议的支持。3 GPP LTE的应用必然面临着与3G协议如WCDMA和TD-SCDMA共存的局面；多模多协议的移动终端正在逐步成为主流。如何从芯片设计的角度对多模多协议进行支持是下一代移动终端设计的难点。其中,数字前端是目前各种多模架构中必不可少的一个部分,并且由于其工作频率高,运算量大,是多模多协议移动终端需要解决的首要问题之一。针对以上两个技术难点,本文研究了3GPP LTE下行接收系统中DSP技术及其VLSI实现的关键技术,设计了低复杂度高性能的关键信号处理模块,并从系统级对性能-运算复杂度可伸缩性的LTE下行接收系统进行了分析和建模。
数字前端是沟通射频模拟前端和基带处理器的桥梁,能够实现采样率转换(SRC),信道滤波,匹配滤波等功能,其运算量大,支持的模式多,是移动终端DSP部分的重要模块。本文研究了支持3GPP LTE/WCDMA/TD-SCDMA的多模多协议数字前端的低复杂度设计,主要工作包括高效的SRC和信道滤波的设计与实现以及3 GPP LTE主同步信号(PSS)的高效搜索。本文提出了以最低运算复杂度为目标的SRC因子分解算法,与现有算法相比,能节省约40%的运算。本文在数字前端中还研究了PSS信号(频域Zadoff-Chu序列)的冗余特性,并根据该特性设计了高效的PSS信号匹配滤波器。与传统的结构相比,该结构能够节省63.5%的复数乘法运算和46.5%的复数加法运算。
快速傅里叶变换(FFT)/反变换(IFFT)处理器是MIMO-OFDM系统中的进行OFDM调制解调的关键处理模块,对系统的性能和芯片的功耗和面积具有很大影响。本文设计了基于24和23混合基算法的4路并行延迟反馈型128～2048点流水线FFT/IFFT处理器,并改进了针对多路并行结构的无乘法旋转因子计算方法。借助于计算机辅助的最优搜索,改进后的方法能够以更少的常系数乘法器完成FFT/IFFT处理器中旋转因子的计算。采用了本文提出的无乘法旋转因子计算方法的128点4路并行FFT/IFFT处理器的功耗和面积都要优于已发表的结果。
MIMO技术是下一代移动通信中的关键技术。本文对MIMO信号检测的低功耗算法和芯片实现方法进行了研究,从算法和硬件架构的角度对MIMO信号检测器进行了分析,明确了制约吞吐率和能量效率的关键因素。本文改进了现有的度量值优先MIMO信号检测算法,为算法增加了预中止的特性,并提出了新型的格点枚举策略。在新型的枚举策略下,部分欧几里得距离的计算可以通过增量累加的方式实现。由于增量计算的复杂度显著低于直接计算,这使得本文提出的MIMO信号检测算法的运算量与传统算法相比节省20%以上。在VLSI设计中,本文设计了基于流水线区间堆的双向有序队列结构,并优化了MIMO检测器的时序控制,使得本文设计的MIMO信号检测器的性能明显优于已发表的结果。
最后,在3GPP LTE下行接收系统的关键DSP模块有了充分认识的基础上本文研究了具有性能-运算复杂度可伸缩性的LTE下行接收系统。本文从性能认知/运算控制/状态判断三个方面对3GPP LTE下行接收系统进行分析,提出了基于等效噪声贡献的伸缩算法,根据系统当前的性能动态调整数据通路(包括FFT/IFFT处理器、信道估计器和MIMO信号检测器)的运算复杂度。通过动态调整,信道估计和MIMO信号检测的运算量能够节省30%以上
With the advance of mobile communications, voice service is not the only applications. Driven by services such as mobile internet, vedio phone, streaming media, and mobile TV, mobile communication technology advances towards providing a higher and higher data rates. The Long Term Evolution (LTE) released by the 3rd Generation Partnership Project (3GPP) is one of the most potential mainstream standard for next generation mobile communictions. LTE outperforms its competitors beacause it is of high data-rate, more flexible spectrum utilization, low latency and rich applications.
There are some challenges that may slow future application of LTE. One is the power and cost constraints of mobile stations (MS). Compared to its 2G and 3G counterparts, LTE mobile stations are required to do more Digital Signal Processing (DSP) operations in a higher frequency (because the widest bandwidth defined in LTE standard is 20 MHz, and the corresponding sample rate of baseband processing is 30.72 MHz). The DSP operations include but are not restricted to Fast Fourier Transforms (FFT) and Multiple Input Multiple Output (MIMO) Detection. The existence of these DSP operations would consume much more power and require a larger battery. For handheld equipments and consumer electronics products, lowering the power consumption and computational complexity of DSP operations in mobile stations is of significant importance.
The other chanllenge lies in the support of multiple mode and multiple standards. The applications of LTE cannot prevent the existence of 3G standards such as WCDMA and TD-SCDMA. Thus, supports of both 3G and B3G standards would be requiremtns to next generation mobile stations, and how to enable multiple standards supports is one of the design chanllenges. Digital Front End (DFE) is an essential part in all current multiple standards mobile station architectures, and is one of the most open issues when design a multiple standard mobile station, because it works in the highest rate and comsumes lots of computation.
In order to solve the above problems, this dissertation studies on the DSP of LTE downlink receivers and investigates its VLSI implementation. This dissertation starts from finding the most computation-harvest bulding blocks in the system, optimizes them and proposes a system approach to enable the Quality-Computational Complexity Scalability to the system.
DFE is the bridge between RF/Analog Front End and Baseband Processor. It accomplishes the following functions, such as Sample Rate Conversion (SRC), channelization filtering, matched filtering and so on. It is important module in multiple standard mobile stations because of the intensive computation and diversity of operation. A low computational complexity, multiple modes DFE support 3GPP LTE, WCDMA, and TD-SCDMA is studied in this dissertation. The contributions include a computational complexity oriented SRC factorization methods and efficient matched filtering of LTE PSS. Via the improved SRC factorization, the SRC and channelization part saves 40% computations complexity compared with those using a conventional factorization. The abundancy property of PSS (Zadoff-Chu sequence in frequency domain) is proven, and efficient matched filters are proposed which can save more than 63% complex multiplications and 46% complex additions.
The FFT/IFFT processor is the key block in MIMO-Orthogonal Frequency Division Multiplex (OFDM) systems. It does the OFDM modulation and demodulation, and has effect on the power and cost of the chip. A R23 and R24 mixed radix 4-path parallel Delay Feedback pipline 128-2048-point FFT/IFFT processor is studied. The author also improves the multiplier-less Twiddle Factor multiplication method used in parallel FFT/IFFTs. Using computer aided optimization, the impoved mehod can use less constant mulpliers to complete the twiddle factor mulitplications, and FFT/IFFT processor adopting this method outperforms the published results.
MIMO is the key technology in next generation wireless communcations. The low power algorithms and chip implementation methods of MIMO detectors are studied. The restricting factors of throughputs and energy efficiency are found. The author improves the Metric-First MIMO detection algorithm by emable pre-termination and a novel enumeration method. Via the novel enumeration, Partial Euclid Distance (PED) is computed by accumulation of PED increments. Because computation of PED increments is much smaller than direction calculation, algorithm propsed by this dissertation save more tha 20% computational complexity than conventional ones. While VLSI implementing, the author designs priority dual queue based on pipeline interval heap and optimize timing of MIMO detection, and obtain a significant results compared with published works.
Quality-Compuational Complexity (Q-CC) Scalable signal processing is a recently developing technology, which enables system to. get a balance between energy and quality. In the last part of this dissertation, the author researches the Q-CC scalable DSP systems, and develops a Q-CC scalable LTE downlink receiver. This receiver adopts a control method based on evaluation of equivalent noise contribution. Simulation shows that channel estimation and MIMO detection in this receiver can save more than 30% computational complexity.
作者在对3GPP LTE系统的发展历史及现状进行分析和调研的基础上,发现在3GPP LTE的推广和普及中存在着以下的挑战：1)移动终端的功耗和成本的降低。与3G的移动终端相比,LTE的移动终端需要进行在更高的工作频率上(LTE标准支持的最大信号带宽为20 MHz)进行更多的数字信号处理(Digital Signal Processing, DSP)操作,如快速傅里叶变换(FFT)和多输入多输出(MIMO)信号检测等。这些操作会导致LTE移动终端在DSP部分消耗更多的能量。对于以手持式设备和消费电子产品为主要应用的技术而言,降低移动终端中DSP部分的功耗和运算复杂度具有重要意义。2)对多模多协议的支持。3 GPP LTE的应用必然面临着与3G协议如WCDMA和TD-SCDMA共存的局面；多模多协议的移动终端正在逐步成为主流。如何从芯片设计的角度对多模多协议进行支持是下一代移动终端设计的难点。其中,数字前端是目前各种多模架构中必不可少的一个部分,并且由于其工作频率高,运算量大,是多模多协议移动终端需要解决的首要问题之一。针对以上两个技术难点,本文研究了3GPP LTE下行接收系统中DSP技术及其VLSI实现的关键技术,设计了低复杂度高性能的关键信号处理模块,并从系统级对性能-运算复杂度可伸缩性的LTE下行接收系统进行了分析和建模。
数字前端是沟通射频模拟前端和基带处理器的桥梁,能够实现采样率转换(SRC),信道滤波,匹配滤波等功能,其运算量大,支持的模式多,是移动终端DSP部分的重要模块。本文研究了支持3GPP LTE/WCDMA/TD-SCDMA的多模多协议数字前端的低复杂度设计,主要工作包括高效的SRC和信道滤波的设计与实现以及3 GPP LTE主同步信号(PSS)的高效搜索。本文提出了以最低运算复杂度为目标的SRC因子分解算法,与现有算法相比,能节省约40%的运算。本文在数字前端中还研究了PSS信号(频域Zadoff-Chu序列)的冗余特性,并根据该特性设计了高效的PSS信号匹配滤波器。与传统的结构相比,该结构能够节省63.5%的复数乘法运算和46.5%的复数加法运算。
快速傅里叶变换(FFT)/反变换(IFFT)处理器是MIMO-OFDM系统中的进行OFDM调制解调的关键处理模块,对系统的性能和芯片的功耗和面积具有很大影响。本文设计了基于24和23混合基算法的4路并行延迟反馈型128～2048点流水线FFT/IFFT处理器,并改进了针对多路并行结构的无乘法旋转因子计算方法。借助于计算机辅助的最优搜索,改进后的方法能够以更少的常系数乘法器完成FFT/IFFT处理器中旋转因子的计算。采用了本文提出的无乘法旋转因子计算方法的128点4路并行FFT/IFFT处理器的功耗和面积都要优于已发表的结果。
MIMO技术是下一代移动通信中的关键技术。本文对MIMO信号检测的低功耗算法和芯片实现方法进行了研究,从算法和硬件架构的角度对MIMO信号检测器进行了分析,明确了制约吞吐率和能量效率的关键因素。本文改进了现有的度量值优先MIMO信号检测算法,为算法增加了预中止的特性,并提出了新型的格点枚举策略。在新型的枚举策略下,部分欧几里得距离的计算可以通过增量累加的方式实现。由于增量计算的复杂度显著低于直接计算,这使得本文提出的MIMO信号检测算法的运算量与传统算法相比节省20%以上。在VLSI设计中,本文设计了基于流水线区间堆的双向有序队列结构,并优化了MIMO检测器的时序控制,使得本文设计的MIMO信号检测器的性能明显优于已发表的结果。
最后,在3GPP LTE下行接收系统的关键DSP模块有了充分认识的基础上本文研究了具有性能-运算复杂度可伸缩性的LTE下行接收系统。本文从性能认知/运算控制/状态判断三个方面对3GPP LTE下行接收系统进行分析,提出了基于等效噪声贡献的伸缩算法,根据系统当前的性能动态调整数据通路(包括FFT/IFFT处理器、信道估计器和MIMO信号检测器)的运算复杂度。通过动态调整,信道估计和MIMO信号检测的运算量能够节省30%以上
With the advance of mobile communications, voice service is not the only applications. Driven by services such as mobile internet, vedio phone, streaming media, and mobile TV, mobile communication technology advances towards providing a higher and higher data rates. The Long Term Evolution (LTE) released by the 3rd Generation Partnership Project (3GPP) is one of the most potential mainstream standard for next generation mobile communictions. LTE outperforms its competitors beacause it is of high data-rate, more flexible spectrum utilization, low latency and rich applications.
There are some challenges that may slow future application of LTE. One is the power and cost constraints of mobile stations (MS). Compared to its 2G and 3G counterparts, LTE mobile stations are required to do more Digital Signal Processing (DSP) operations in a higher frequency (because the widest bandwidth defined in LTE standard is 20 MHz, and the corresponding sample rate of baseband processing is 30.72 MHz). The DSP operations include but are not restricted to Fast Fourier Transforms (FFT) and Multiple Input Multiple Output (MIMO) Detection. The existence of these DSP operations would consume much more power and require a larger battery. For handheld equipments and consumer electronics products, lowering the power consumption and computational complexity of DSP operations in mobile stations is of significant importance.
The other chanllenge lies in the support of multiple mode and multiple standards. The applications of LTE cannot prevent the existence of 3G standards such as WCDMA and TD-SCDMA. Thus, supports of both 3G and B3G standards would be requiremtns to next generation mobile stations, and how to enable multiple standards supports is one of the design chanllenges. Digital Front End (DFE) is an essential part in all current multiple standards mobile station architectures, and is one of the most open issues when design a multiple standard mobile station, because it works in the highest rate and comsumes lots of computation.
In order to solve the above problems, this dissertation studies on the DSP of LTE downlink receivers and investigates its VLSI implementation. This dissertation starts from finding the most computation-harvest bulding blocks in the system, optimizes them and proposes a system approach to enable the Quality-Computational Complexity Scalability to the system.
DFE is the bridge between RF/Analog Front End and Baseband Processor. It accomplishes the following functions, such as Sample Rate Conversion (SRC), channelization filtering, matched filtering and so on. It is important module in multiple standard mobile stations because of the intensive computation and diversity of operation. A low computational complexity, multiple modes DFE support 3GPP LTE, WCDMA, and TD-SCDMA is studied in this dissertation. The contributions include a computational complexity oriented SRC factorization methods and efficient matched filtering of LTE PSS. Via the improved SRC factorization, the SRC and channelization part saves 40% computations complexity compared with those using a conventional factorization. The abundancy property of PSS (Zadoff-Chu sequence in frequency domain) is proven, and efficient matched filters are proposed which can save more than 63% complex multiplications and 46% complex additions.
The FFT/IFFT processor is the key block in MIMO-Orthogonal Frequency Division Multiplex (OFDM) systems. It does the OFDM modulation and demodulation, and has effect on the power and cost of the chip. A R23 and R24 mixed radix 4-path parallel Delay Feedback pipline 128-2048-point FFT/IFFT processor is studied. The author also improves the multiplier-less Twiddle Factor multiplication method used in parallel FFT/IFFTs. Using computer aided optimization, the impoved mehod can use less constant mulpliers to complete the twiddle factor mulitplications, and FFT/IFFT processor adopting this method outperforms the published results.
MIMO is the key technology in next generation wireless communcations. The low power algorithms and chip implementation methods of MIMO detectors are studied. The restricting factors of throughputs and energy efficiency are found. The author improves the Metric-First MIMO detection algorithm by emable pre-termination and a novel enumeration method. Via the novel enumeration, Partial Euclid Distance (PED) is computed by accumulation of PED increments. Because computation of PED increments is much smaller than direction calculation, algorithm propsed by this dissertation save more tha 20% computational complexity than conventional ones. While VLSI implementing, the author designs priority dual queue based on pipeline interval heap and optimize timing of MIMO detection, and obtain a significant results compared with published works.
Quality-Compuational Complexity (Q-CC) Scalable signal processing is a recently developing technology, which enables system to. get a balance between energy and quality. In the last part of this dissertation, the author researches the Q-CC scalable DSP systems, and develops a Q-CC scalable LTE downlink receiver. This receiver adopts a control method based on evaluation of equivalent noise contribution. Simulation shows that channel estimation and MIMO detection in this receiver can save more than 30% computational complexity.
引文
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