数字集成电路多故障测试生成算法和可测性设计的研究
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摘要
微电子技术是当今发展最快的技术领域之一。随着集成电路设计及工艺技术的发展，电路的规模和复杂度日益增大，芯片故障的测试日趋困难，对电路的测试也提出了更高的要求，从而推动了测试生成算法的研究。传统的测试生成算法已不能满足要求，因此集成电路测试研究的重点主要集中于研究新的更加有效的测试生成算法和电路可测性设计技术。
本论文主要研究数字集成电路中组合电路的多故障测试生成算法和可测性设计技术，以提高算法的故障覆盖率、减少测试生成时间及减少测试矢量的产生和施加为研究目标，主要研究了以下内容：
在深入研究了二值神经网络模型基础上，建立了三值神经网络模型，并将三值神经网络成功应用于组合电路测试生成算法中。通过构建被测电路的约束网络，采用遗传算法并使用本文提出的适应度函数，求出约束网络对应能量函数的最小值点。通过编程仿真，在基准电路上得到故障的测试矢量。给出了三值模型与二值模型测试的比较结果。用三值神经网络表示数字电路，可以减小搜索空间，避免很多不必要的赋值，因此可以在保证具有较高故障覆盖率的情况下，减少测试生成时间，提高算法的测试生成效率。
研究了基于布尔差分的组合电路测试生成算法。针对布尔差分算法需要进行大量的异或运算，特别是求解多故障测试矢量时，求解高阶布尔差分更加繁琐的问题，提出了将组合电路多故障转换成单固定故障或双固定故障后，采用具有约束条件的一阶、二阶布尔差分简化法的方法，可不用异或运算，而是通过求解恒等式及约束条件来得到完全测试集，避免了大量的布尔差分运算。
在EST(equivalent state hashing)算法的基础上，利用E-前沿的控制关系，对基于搜索状态控制的组合电路测试生成算法进行了研究，通过实例证明了该算法可以更有效的减小搜索空间；通过仿真验证了所求测试矢量的正确性。
症候群测试不需要产生测试矢量，因此对电路的症候群测试进行了深入研究。针对传统的症候群可测性判定条件需要写出电路的逻辑表达式，对于大规模集成电路，按照传统的方式很难进行判断，本文推导出了一元症候群和二元症候群可测性判定条件的新形式，并由此推出了多元症候群的判定条件。利用该判定条件，既可直接进行多元症候群判定，不必写出电路的逻辑表达式，又可保证症候群可测。
研究了基于Reed-Muller模式的组合电路的可测性。针对组合电路产生测试矢量开销大的问题，对Reed-Muller模式的组合电路进行了研究。该方法采用通用型测试集测试的电路结构或模块进行电路设计。用此种方法不但可以方便的检测出电路的单固定型故障，而且可以确定单故障的具体位置，对于双故障以及多故障也可用此方法检测出来。
为了减少测试矢量，有必要对电路中的故障加以分析，寻找各类故障之间的关系，以求压缩测试矢量。本文提出了一种将并行故障仿真与布尔约简法相结合来确定测试矢量最小测试集的方法。该方法通过编制软件程序进行并行故障仿真，利用并行故障仿真结果确定出故障点和测试矢量的对应关系，然后即可根据布尔约简法求出测试矢量的最小测试集。
Microelectronic technique is one of the most rapidly developing techniquesin technological field at present. With the advancement of its design andproduction process, integrated circuits (ICs) are becoming more and morecomplex and larger and larger in scale, making the test for the chips increasinglydifficult. In the meantime, higher requirements for circuits test have been putforward, thus the research on test generation algorithms are drived forward. Asthe traditional test generation algorithms no longer meet the requirements, thekey points in ICs testing research mainly focus on new and more effective testgeneration algorithms and design for testability of Digital Integrated Circuits.
In this dissertation, the multi-fault test generation algorithms and design fortestability of combinational circuits have been studied for the purpose ofimproving faults coverage, reducing the test generation time, the generation andapplication of test patterns. The main contents of this thesis are as follows:
Based on the research on two-valued neural networks model, three-valuedneural networks model for combinational circuits has been established andapplied successfully to test generation algorithms for combinational circuits. Byconstructing the constraint networks of circuits to be tested, using geneticalgorithm and fitness function proposed in this paper, through programming, theminimum of the energy function to correspond with the constraint network can begotten. By means of simulation, the test patterns of faults can be obtained forbenchmark circuits. Further, the comparative results of three-valued and two-valuedmodels have been presented. If digital circuits are represented by three-valuedneural networks model, the search space can be reduced and many unnecessaryassignments can be avoided. Therefore, the method can reduce test time andimprove test efficiency.
The test generation algorithms based on Boolean difference forcombinational circuits has been studied. Considering that there are a lot ofexclusive OR operations in the Boolean difference, we proposed single fault ordouble faults test generation simplified method with constraint conditions. In thisway, multi-fault can be equated into single fault or double faults forcombinational circuits, test patterns can be obtained only by solving the identityand constraint conditions without exclusive OR operations.
In accordance with EST algorithm, a kind of test generation algorithm hasbeen studied based on search state dominance for combinational circuits. Takingthe advantage of the dominance relation of the E-frontier (evaluation frontier),we can prove through some examples that this algorithm can prune the searchspace more effectively than the EST algorithm. The calculated test patterns candetect the given faults with the help of the simulation.
Since generating test patterns are not needed in the course of Syndrometesting, Syndrome of circuits has been thoroughly studied. As the logicalexpression is needed to be given for the traditional Syndrome test, it is difficultto test for the VLSI. In this dissertation, first order and second order Syndrometestable new conditions have been derived, and the high-order test Syndrometestable condition can be obtained therefrom. By making use of it, we can fulfillthe judgment of high-order Syndrome directly with no need of giving the logicalexpression. In addition, it can be ensured that Syndrome of circuits would betestable.
Design for testability based on Reed-Muller pattern for combinational circuitshas been studied. In consideration of the problem that test patterns generation ofcombinational circuits needs much resource, we have made a research on thecombinational circuits based on Reed-Muller pattern. The circuit structure ormodule designed in this way may be tested by general test patterns set. It can notonly detect single-fault easily, but also define ihe fault location. Besides, thedouble-fault and multi-fault can also be detected by this method.
In order to decrease the test patterns, it is necessary to analyze the faults incircuits and find out the relationships among all kinds of faults. This paperpresents a kind of method that combines parallel faults simulation with Booleansimplified method for determining the minimum test patterns set. By using the results of parallel faults simulation, the corresponding relationship between faultpoints and test patterns can be determined, also, the minimum test patterns setcan be gotten based on Boolean simplified method.
本论文主要研究数字集成电路中组合电路的多故障测试生成算法和可测性设计技术，以提高算法的故障覆盖率、减少测试生成时间及减少测试矢量的产生和施加为研究目标，主要研究了以下内容：
在深入研究了二值神经网络模型基础上，建立了三值神经网络模型，并将三值神经网络成功应用于组合电路测试生成算法中。通过构建被测电路的约束网络，采用遗传算法并使用本文提出的适应度函数，求出约束网络对应能量函数的最小值点。通过编程仿真，在基准电路上得到故障的测试矢量。给出了三值模型与二值模型测试的比较结果。用三值神经网络表示数字电路，可以减小搜索空间，避免很多不必要的赋值，因此可以在保证具有较高故障覆盖率的情况下，减少测试生成时间，提高算法的测试生成效率。
研究了基于布尔差分的组合电路测试生成算法。针对布尔差分算法需要进行大量的异或运算，特别是求解多故障测试矢量时，求解高阶布尔差分更加繁琐的问题，提出了将组合电路多故障转换成单固定故障或双固定故障后，采用具有约束条件的一阶、二阶布尔差分简化法的方法，可不用异或运算，而是通过求解恒等式及约束条件来得到完全测试集，避免了大量的布尔差分运算。
在EST(equivalent state hashing)算法的基础上，利用E-前沿的控制关系，对基于搜索状态控制的组合电路测试生成算法进行了研究，通过实例证明了该算法可以更有效的减小搜索空间；通过仿真验证了所求测试矢量的正确性。
症候群测试不需要产生测试矢量，因此对电路的症候群测试进行了深入研究。针对传统的症候群可测性判定条件需要写出电路的逻辑表达式，对于大规模集成电路，按照传统的方式很难进行判断，本文推导出了一元症候群和二元症候群可测性判定条件的新形式，并由此推出了多元症候群的判定条件。利用该判定条件，既可直接进行多元症候群判定，不必写出电路的逻辑表达式，又可保证症候群可测。
研究了基于Reed-Muller模式的组合电路的可测性。针对组合电路产生测试矢量开销大的问题，对Reed-Muller模式的组合电路进行了研究。该方法采用通用型测试集测试的电路结构或模块进行电路设计。用此种方法不但可以方便的检测出电路的单固定型故障，而且可以确定单故障的具体位置，对于双故障以及多故障也可用此方法检测出来。
为了减少测试矢量，有必要对电路中的故障加以分析，寻找各类故障之间的关系，以求压缩测试矢量。本文提出了一种将并行故障仿真与布尔约简法相结合来确定测试矢量最小测试集的方法。该方法通过编制软件程序进行并行故障仿真，利用并行故障仿真结果确定出故障点和测试矢量的对应关系，然后即可根据布尔约简法求出测试矢量的最小测试集。
Microelectronic technique is one of the most rapidly developing techniquesin technological field at present. With the advancement of its design andproduction process, integrated circuits (ICs) are becoming more and morecomplex and larger and larger in scale, making the test for the chips increasinglydifficult. In the meantime, higher requirements for circuits test have been putforward, thus the research on test generation algorithms are drived forward. Asthe traditional test generation algorithms no longer meet the requirements, thekey points in ICs testing research mainly focus on new and more effective testgeneration algorithms and design for testability of Digital Integrated Circuits.
In this dissertation, the multi-fault test generation algorithms and design fortestability of combinational circuits have been studied for the purpose ofimproving faults coverage, reducing the test generation time, the generation andapplication of test patterns. The main contents of this thesis are as follows:
Based on the research on two-valued neural networks model, three-valuedneural networks model for combinational circuits has been established andapplied successfully to test generation algorithms for combinational circuits. Byconstructing the constraint networks of circuits to be tested, using geneticalgorithm and fitness function proposed in this paper, through programming, theminimum of the energy function to correspond with the constraint network can begotten. By means of simulation, the test patterns of faults can be obtained forbenchmark circuits. Further, the comparative results of three-valued and two-valuedmodels have been presented. If digital circuits are represented by three-valuedneural networks model, the search space can be reduced and many unnecessaryassignments can be avoided. Therefore, the method can reduce test time andimprove test efficiency.
The test generation algorithms based on Boolean difference forcombinational circuits has been studied. Considering that there are a lot ofexclusive OR operations in the Boolean difference, we proposed single fault ordouble faults test generation simplified method with constraint conditions. In thisway, multi-fault can be equated into single fault or double faults forcombinational circuits, test patterns can be obtained only by solving the identityand constraint conditions without exclusive OR operations.
In accordance with EST algorithm, a kind of test generation algorithm hasbeen studied based on search state dominance for combinational circuits. Takingthe advantage of the dominance relation of the E-frontier (evaluation frontier),we can prove through some examples that this algorithm can prune the searchspace more effectively than the EST algorithm. The calculated test patterns candetect the given faults with the help of the simulation.
Since generating test patterns are not needed in the course of Syndrometesting, Syndrome of circuits has been thoroughly studied. As the logicalexpression is needed to be given for the traditional Syndrome test, it is difficultto test for the VLSI. In this dissertation, first order and second order Syndrometestable new conditions have been derived, and the high-order test Syndrometestable condition can be obtained therefrom. By making use of it, we can fulfillthe judgment of high-order Syndrome directly with no need of giving the logicalexpression. In addition, it can be ensured that Syndrome of circuits would betestable.
Design for testability based on Reed-Muller pattern for combinational circuitshas been studied. In consideration of the problem that test patterns generation ofcombinational circuits needs much resource, we have made a research on thecombinational circuits based on Reed-Muller pattern. The circuit structure ormodule designed in this way may be tested by general test patterns set. It can notonly detect single-fault easily, but also define ihe fault location. Besides, thedouble-fault and multi-fault can also be detected by this method.
In order to decrease the test patterns, it is necessary to analyze the faults incircuits and find out the relationships among all kinds of faults. This paperpresents a kind of method that combines parallel faults simulation with Booleansimplified method for determining the minimum test patterns set. By using the results of parallel faults simulation, the corresponding relationship between faultpoints and test patterns can be determined, also, the minimum test patterns setcan be gotten based on Boolean simplified method.
引文
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61 T. Niermann, J. H. Patel. HITEC: A test ge.neration package for sequential circuit. Proc. Design automation Conf, 1991: 215～217
62 M. H. Schule, E. Auth. ESSENTIAL: An efficient self-learning test pattern generation algorithm for sequential circuit. IEEE Proc. International Test Conference, 1989: 27～36
63 T. P. Kelsey, K. K. Saluja, S. Y. Lee. An efficient algorithm for sequential test generation. IEEE Trans. On computer. 1993, 42(11): 1362～1370
64 V. D. Agrawal, K. T Cheng, P. Agrawal. CONTEST: A concurrent test generator for sequential circuit. IEEE Proc. 25th ACM Design automation Conf, 1988: 84～89
65 F. Corno, P. Prinetto, M. Rebaudengo, M. Sreorda. GATTO: A genetic algorithm for automatic test pattern generation for large synchronous sequential circuit. IEEE Transaction on Computer-Aided Design of Integrated Circuit and System, 1996, 15(8): 990～998
66 D. G. Saab, Y. G. Saab, J. A. Abraham. CRIS: A test cultivation program for sequential VLSI circuit. Proc. Int. Conf. Computer-Aided Design, 1992: 216～219
67 E. M. Rudnic, J. H. Patel, G. S. Greestein, T. M. Niermann. Sequential circuit test generation in a genetic algorithm framework. Proc. Design automation Conf, 1994: 698～704
68 H. K. T. Ma, S. Devadas, A. R. Newton, A. S. Vincentelli. Test generation for sequential circuit. IEEE Transaction on Computer-Aided Design. 2000, 7(10): 1081～1092
69 Ghosh, S. Devadas, A. R. Newton. Test generation and verification for highly sequential circuit. IEEE Transaction on Computer-Aided Design, 1991, 10(5): 655～666
70 Hideo Fujiwara. A Method of Generation for Path Faults in Banlanced Sequential Circuits. Proceeding of the 20th IEEE VLSI Test Symposium. 2002
71 Michiko Inoue. Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption. Journal of Electronic: Theory and Applications, 20021: 55～58
72 Tsuyoshi Iwagaki, Satoshi Ohtake Hideo Fujiwara. Acceleration of Transition Test Generation for Acyclic Sequentiai Circuits Utilizing Constrained Combinational Stuck-at Test Generation. Proceedings of 10th IEEE European Test Symposium, May 22-25 2005, Tallinn, Estonia: 48～53
73 阮根鸿．异步时序电路的测试生成算法—H算法．电子学报，1983，(1)：49～57
74 杨士元．数字系统的故障诊断与可靠性设计．第二版 清华大学出版社，2000
75 Jerry Gao, Ph. D. and Ming-Chih Shih. A component Testability Model for Verification and Measurement. Proceddings of the 29th Annual International Computer Software and Applications Conference. 2005, 1 (1): 211～218
76 D. xiaog and J. H. Patel. Agloobal Algotithm for the Partial Scan Design Problem Using Circuit State Information. Proc. IEEE int'l Test Conf., Oct. 1996: 548～557
77 Pomeranz, S. M. Reddy. Functional Test Generation for Full Scan Circuits. Proc. Design, Automation and Test in Europe, 2000: 396～401
78 Debesh K. Das, Bhargab B. Bhattacharya, Satoshi Ohtake and Hideo Fujiwara. Testable Design of Sequential Circuit with Improved Fault Efficiency. Fourteenth International Conference on VLSI Design, 2001: 128～133
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80 潘中良．数字电路可测性设计的一种故障定位方法．中国工程科学，2002，(1)：69～74
81 Dong Xiang, Yi Xu, Hideo Fujiwara. Non-Scan Design for Testability for Synchronous Sequential Circuits Based on Conflict Analysis. Information and Systems, v E86-D, n 11, November, 2003, 2407～2417
82 张立明．人工神经网络的模型及应用．复旦大学出版社，2000：45～48
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84 Hideo Fujiwara. Three-Valued Neural Networks for Test Generation. Proc. of 20th Fault-Tolerant Computing Symposium, 1990: 66～67.
85 潘中良，陈翎．基于神经网络的电路多故障测试及并行实现．仪器仪表学报，2002，(6)：680～681
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87 潘中良，陈光与．测试图形生成的遗传算法研究．电子科技大学学报，1997，26(5)：511～514
88 潘中良，张光昭．基于模拟与遗传进化的电路测试生成方法研究．仪器仪表学报，1999，20(5)：470～472
89 王小平．遗传算法理论与应用．西安交通大学出版社，2002：28～50
90 Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja. Multiple Faults: Modeling, Simulation and Test. Proceedings of the 15th International Conference on VLSI Design, 2002: 24～26
91 梁玉英，蔡金英等．组合逻辑多故障诊断．微电子学，2002，3(3)：185～187
92 J. Giraldi and M. L. Bushnell. EST: The new frontier in automatic test pattern generation. Proc. 27th ACMIIEEE Design Automation Conf. June 1990: 667～672
93 T. Fujino and H. Fujiwara, An efficient test generation algorithm based on search state dominance, in Proc. Intl. Symposium on Fault-Tolerant Comp. 2002: 246～253
94 刘晓东，张毅刚，孙圣和．具有最小搜索空间的优化测试生成算法．仪器仪表学报，2002，(6)：32～34
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96 金娜，姚秀华．数字集成电路的可测性设计及其应用，微处理机，1998，(5)：63～67
97 Yin-He Su, Ching-Hwa Cheng and Shih-Chieh Chang. Novel Techniques for Improving Testability Analysis, Fundamentals of Electronics, Communications and Computer Sciences, v E85-A, n 12, December, 2002: 2901～2912
98 Benoit Baudry, Yves Le Traon, Gerson Sunye and Jean-Marc Jezequel. Measuring and Improving Design Patterns Teseability. Proceddings of the Ninth International Software Metrics Symposium, 2003: 50～59
99 Savir J. Syndrme-testable Design Test of Combinational Circuirts. IEEE Trans, Comput. 1980, c-29(9): 16～19
100 Bhattachaya B B, B Gupta. Syndrme Testable Design Test of Combinational Network for Detecting Stuck-at and Bridging Faults. Pro.Int.Test Conf. 1983.
101 Barzilai Z, Savir J, Markowsky G, Smith M G. The Weighted Syndrme Sums Approach to VISL Testing. IEEE Trans, Comput: 1981, c-30(1-2): 23～26
102 Shiyi Xu. High-Order Syndrome Testing for VLSI Circuits. Proceedings 11th Pacific Rim International Symposium on Dependable Computing, Hunan, China, 12-14 Dec. 2005: 8～12
103 Abramovici, M. P. M. Menon and D. T. Mill. Critical Path Tracing: An Alternative to fault simulation. IEEE Design and Test of Computers, 1984: 83～93
104 W. Kuzmicz, W. Pleskacz, J. Raik and R. Ubar. Defect-Oriented Fault Simulation and Test Generation in Digital Circuits. Proceedings of the IEEE 2001. The 2nd International Symposium on Quality Electronic Design, 2001: 365～371
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58 P. Muth. A nine-valued cirduit model for test generation. IEEE Trans. On Computers, 1976, C-25(6): 630～636
59 W. T. Cheng. The BACK algorithm for sequential test generation. Proc. Int. Conf. on Computer Design, 1988: 66～69
60 R. Marlett. EBT: A Comprehensive Test Generation Technique for Highly Sequential Circuits. Proc. Design Automation Conference, 1978, 6: 332～339
61 T. Niermann, J. H. Patel. HITEC: A test ge.neration package for sequential circuit. Proc. Design automation Conf, 1991: 215～217
62 M. H. Schule, E. Auth. ESSENTIAL: An efficient self-learning test pattern generation algorithm for sequential circuit. IEEE Proc. International Test Conference, 1989: 27～36
63 T. P. Kelsey, K. K. Saluja, S. Y. Lee. An efficient algorithm for sequential test generation. IEEE Trans. On computer. 1993, 42(11): 1362～1370
64 V. D. Agrawal, K. T Cheng, P. Agrawal. CONTEST: A concurrent test generator for sequential circuit. IEEE Proc. 25th ACM Design automation Conf, 1988: 84～89
65 F. Corno, P. Prinetto, M. Rebaudengo, M. Sreorda. GATTO: A genetic algorithm for automatic test pattern generation for large synchronous sequential circuit. IEEE Transaction on Computer-Aided Design of Integrated Circuit and System, 1996, 15(8): 990～998
66 D. G. Saab, Y. G. Saab, J. A. Abraham. CRIS: A test cultivation program for sequential VLSI circuit. Proc. Int. Conf. Computer-Aided Design, 1992: 216～219
67 E. M. Rudnic, J. H. Patel, G. S. Greestein, T. M. Niermann. Sequential circuit test generation in a genetic algorithm framework. Proc. Design automation Conf, 1994: 698～704
68 H. K. T. Ma, S. Devadas, A. R. Newton, A. S. Vincentelli. Test generation for sequential circuit. IEEE Transaction on Computer-Aided Design. 2000, 7(10): 1081～1092
69 Ghosh, S. Devadas, A. R. Newton. Test generation and verification for highly sequential circuit. IEEE Transaction on Computer-Aided Design, 1991, 10(5): 655～666
70 Hideo Fujiwara. A Method of Generation for Path Faults in Banlanced Sequential Circuits. Proceeding of the 20th IEEE VLSI Test Symposium. 2002
71 Michiko Inoue. Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption. Journal of Electronic: Theory and Applications, 20021: 55～58
72 Tsuyoshi Iwagaki, Satoshi Ohtake Hideo Fujiwara. Acceleration of Transition Test Generation for Acyclic Sequentiai Circuits Utilizing Constrained Combinational Stuck-at Test Generation. Proceedings of 10th IEEE European Test Symposium, May 22-25 2005, Tallinn, Estonia: 48～53
73 阮根鸿．异步时序电路的测试生成算法—H算法．电子学报，1983，(1)：49～57
74 杨士元．数字系统的故障诊断与可靠性设计．第二版 清华大学出版社，2000
75 Jerry Gao, Ph. D. and Ming-Chih Shih. A component Testability Model for Verification and Measurement. Proceddings of the 29th Annual International Computer Software and Applications Conference. 2005, 1 (1): 211～218
76 D. xiaog and J. H. Patel. Agloobal Algotithm for the Partial Scan Design Problem Using Circuit State Information. Proc. IEEE int'l Test Conf., Oct. 1996: 548～557
77 Pomeranz, S. M. Reddy. Functional Test Generation for Full Scan Circuits. Proc. Design, Automation and Test in Europe, 2000: 396～401
78 Debesh K. Das, Bhargab B. Bhattacharya, Satoshi Ohtake and Hideo Fujiwara. Testable Design of Sequential Circuit with Improved Fault Efficiency. Fourteenth International Conference on VLSI Design, 2001: 128～133
79 潘中良．基于逻辑函数的电路可测性设计及多故障测试．应用科学学报，2002，(6)：111～115
80 潘中良．数字电路可测性设计的一种故障定位方法．中国工程科学，2002，(1)：69～74
81 Dong Xiang, Yi Xu, Hideo Fujiwara. Non-Scan Design for Testability for Synchronous Sequential Circuits Based on Conflict Analysis. Information and Systems, v E86-D, n 11, November, 2003, 2407～2417
82 张立明．人工神经网络的模型及应用．复旦大学出版社，2000：45～48
83 杨行峻，郑君里．人工神经网络与盲信号处理．清华大学出版社，2003：32～36
84 Hideo Fujiwara. Three-Valued Neural Networks for Test Generation. Proc. of 20th Fault-Tolerant Computing Symposium, 1990: 66～67.
85 潘中良，陈翎．基于神经网络的电路多故障测试及并行实现．仪器仪表学报，2002，(6)：680～681
86 潘中良．数字电路多故障测试生成方法的研究与实现．电子科技大学博士论文，1997：10～24
87 潘中良，陈光与．测试图形生成的遗传算法研究．电子科技大学学报，1997，26(5)：511～514
88 潘中良，张光昭．基于模拟与遗传进化的电路测试生成方法研究．仪器仪表学报，1999，20(5)：470～472
89 王小平．遗传算法理论与应用．西安交通大学出版社，2002：28～50
90 Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja. Multiple Faults: Modeling, Simulation and Test. Proceedings of the 15th International Conference on VLSI Design, 2002: 24～26
91 梁玉英，蔡金英等．组合逻辑多故障诊断．微电子学，2002，3(3)：185～187
92 J. Giraldi and M. L. Bushnell. EST: The new frontier in automatic test pattern generation. Proc. 27th ACMIIEEE Design Automation Conf. June 1990: 667～672
93 T. Fujino and H. Fujiwara, An efficient test generation algorithm based on search state dominance, in Proc. Intl. Symposium on Fault-Tolerant Comp. 2002: 246～253
94 刘晓东，张毅刚，孙圣和．具有最小搜索空间的优化测试生成算法．仪器仪表学报，2002，(6)：32～34
95 牛为华，孟建良，张素文．成对测试中的测试生成策略研究．计算机仿 真，2003，(7)：111～115
96 金娜，姚秀华．数字集成电路的可测性设计及其应用，微处理机，1998，(5)：63～67
97 Yin-He Su, Ching-Hwa Cheng and Shih-Chieh Chang. Novel Techniques for Improving Testability Analysis, Fundamentals of Electronics, Communications and Computer Sciences, v E85-A, n 12, December, 2002: 2901～2912
98 Benoit Baudry, Yves Le Traon, Gerson Sunye and Jean-Marc Jezequel. Measuring and Improving Design Patterns Teseability. Proceddings of the Ninth International Software Metrics Symposium, 2003: 50～59
99 Savir J. Syndrme-testable Design Test of Combinational Circuirts. IEEE Trans, Comput. 1980, c-29(9): 16～19
100 Bhattachaya B B, B Gupta. Syndrme Testable Design Test of Combinational Network for Detecting Stuck-at and Bridging Faults. Pro.Int.Test Conf. 1983.
101 Barzilai Z, Savir J, Markowsky G, Smith M G. The Weighted Syndrme Sums Approach to VISL Testing. IEEE Trans, Comput: 1981, c-30(1-2): 23～26
102 Shiyi Xu. High-Order Syndrome Testing for VLSI Circuits. Proceedings 11th Pacific Rim International Symposium on Dependable Computing, Hunan, China, 12-14 Dec. 2005: 8～12
103 Abramovici, M. P. M. Menon and D. T. Mill. Critical Path Tracing: An Alternative to fault simulation. IEEE Design and Test of Computers, 1984: 83～93
104 W. Kuzmicz, W. Pleskacz, J. Raik and R. Ubar. Defect-Oriented Fault Simulation and Test Generation in Digital Circuits. Proceedings of the IEEE 2001. The 2nd International Symposium on Quality Electronic Design, 2001: 365～371