VLSI低功耗高层综合设计技术研究
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摘要
随着电路规模的不断扩大,集成度的不断提高,高速率高性能的系统芯片的功耗成为日渐突出的问题。如何设计出低功耗的VLSI,成为当务之急。高层次综合技术是数字系统设计的关键技术,它拥有与许多其他层次相异的特点,因此我们选择了高层次综合技术进行低功耗设计。本文的工作针对高层设计中与功耗相关的电压、频率、互连及拓扑结构等方面展开,研究并解决了其中几项关键问题。
基于多电压下的物理布局问题,可将一块芯片划分成若干个电压区域,在不同电压操作下信号传送于各区域间。本文提出了一种高层综合方法—Tabu搜索法,目的是在多电压的时间和资源限制下实现集成电路功耗最小化。与仅考虑调度的传统方法不同,本文中的Tabu法同时考虑调度和分区,减小了各功能单元及单元间连线的功耗,并能有效地解决在多电压设计中存在的布局问题。利用Tabu搜索法所得的解决方法以三元矢量的形式从调度和分区两个方面说明,应用Tabu表可以避免解决问题方法的多次反复,Tabu表还配有一个校正作用的期望函数,因此该搜索算法具有快速收敛性,能够在更大范围的解的空间找出最优解。实验表明该算法使得电路的平均功耗下降49.6%左右。另外针对多电压下的布局问题还提出模拟退火(Simulated Annealing)法,在时间和资源限制下实现多电压的集成电路功耗最小化,通过对温度的控制对问题求解进行多次迭代。其优点在于能有效地避免了局部搜索算法陷入局部最优的弊端而收敛于全局最优解。实验证明该算法能有效降低电路功耗。
降低频率可以降低功耗,但是单纯地降低频率并不能节省能量。只有在降低频率的同时降低电压,才能真正地降低能量的消耗。多电压下基于动态时钟频率的调度也开始被研究,通过改变电压和时钟频率,能够使系统的功耗降低,从而能够获得高的性能。本文采用多电压和动态频率机制,提出了基于时间约束和资源约束的Gain调度算法及分配方法,它包括两个模块: Allocate_F与Allocate_V。算法的输入是没有调度的数据流图及约束条件,包括资源约束,时间约束条件和工作电压,输出为总能耗及执行时间。实验表明该方案能有效地降低功耗,并且提高系统性能。
此外,基于多电压综合从调度互连两个角度达到低功耗的目的,本文还提出了VLSI高层综合设计方案。该方案基于Gain大小搜索调度,将功耗增益、灵活度和行为执行密度因素作为优先函数,全面地考虑操作的属性。在互连中同时考虑单根总线上的翻转和邻线的耦合。该方案在CDFG工具包中实现并证明了它的有效性,并给出了相应的实验数据。
多核体系是系统向更大规模发展的趋势。从SoC发展到NoC,其主要过程就是它采用网络的通信方式代替传统总线通信方式。对于片上网络来讲,可从物理设计、软件方法以及网络拓扑三个方面来研究减少功耗的方法,各个组件连接形成的网络性能与网络拓朴结构有很密切关系。本文提出一种NoC拓扑结构—Spidernet,其具有平均最短路径小、可平面化的优点、还具有很好的扩展性,并以网络的主要属性:节点度、网络直径、连通度、平均最短路径和平均最短布线几个方面将其与其他拓朴结构进行比较。实验中采用模拟退火的布局映射算法在不同的拓扑结构上运行基准程序,结果表明提出的网络拓扑结构更适合于将来的SoC的片上网络构造。
为了实现并证明所提出的低功耗的算法和方法,本文介绍了高层综合设计中的有效工具--CDFG工具包,文中各章节的实验均在CDFG工具包下进行的。它包括CDFG生成器、CDFG到C(VHDL)的转换器、CDFG剖析器、CDFG阅读器。CDFG工具包为高层次综合设计提供了一套方便实用的工具。通过对CDFG工具包的分析,并将其应用于高层次综合设计,验证了工具包高效方便的辅助设计作用。
With today's increasingly large and complex digital integrated circuit (IC) and system-on-chip designs, power dissipation has emerged as a primary design consideration. Reduction of power consumption in VLSI designs can be achieved at various levels of the design hierarchy, ranging from processing technology, circuit, logic, architectural and algorithmic (behavioral) levels, up to system level. It has also been long recognized that the most dramatic power saving is achievable at the algorithm and architecture levels, where computations are normally described using data/control flow graphs. Thus, in this thesis, a multiple supply voltage IC is synthesized at the high level.
In this thesis, a tabu-search-based behavior level synthesis scheme is proposed to minimize power consumption with resources operating at multiple voltages under the timing and the resource constraints. Unlike the conventional methods where only scheduling is considered, our synthesis scheme considers both scheduling and partitioning simultaneously to reduce power consumption due to the functional units as well as the interconnects among them. In particular, we have configured our solutions as a three-tuple vector to account for both the schedule and the partition. Cycling of the same solutions is prevented by applying a tabu list with an update mechanism enhanced with an aspiration function. In this way, the algorithm can search a large solution space with fast convergence rate. Experiments with a number of DSP benchmarks show that the proposed algorithms achieve an average power reduction by 49.6%.
In this thesis, a Simulated-Annealing-based behavior level synthesis scheme is proposed to minimize power consumption with resources operating at multiple voltages under the timing and the resource constraints. Our synthesis scheme considers both scheduling and partitioning simultaneously to reduce power consumption due to the functional units as well as the interconnects among them. In particular, we have configured our solutions as a three-tuple vector and have got it by many iterations under the controlled temperature. The advantage of this algorithm is that it can avoid local optimization and converge whole optimization. Experiments with a number of DSP benchmarks show that the proposed algorithm is effective for low power design.
In this thesis, a scheduling scheme based on dynamic frequency clocking and multiple voltages is proposed for low power designs under the timing and the resource constraints. Unlike the conventional methods at high level synthesis where only voltages of nodes were considered, the scheme based on a gain function considers both voltage and frequency simultaneously to reduce energy consumption. Experiments with a number of DSP benchmarks show that the proposed scheme achieves an effective energy reduction.
A high level synthesis scheme based on multiple voltages is proposed for low power design in VLSI. This scheme considers both scheduling and interconnection to reduce power. In GAIN scheduling, the priority function includes the power gain, the mobility, and the computation density of an operation. The transition activities on the signal lines and the coupling capacitances of the lines are considered simultaneously in interconnection. This scheme is realized in CDFG Toolkits and its efficiency is proved.
From System-on-chip to Network-on-chip, the main dissimilarity is replacing the bus with the network. How connect, how formative network function is related to topology structure. In this paper we propose a topology structure for NoC, and compare it with other topology networks by five kinds of mainly properties : node degree, network diameter, connectivity, the average most short-circuit path and the average shortest wire length. Experiment results show that this topology has better performance on cost/performance layout.
CDFG Toolkits provide a set of software tools convenient and practical for high level synthesis. The CDFG toolkit includes CDFG generator, CDFG to C (VHDL) converter, CDFG parser, and CDFG viewer. The CDFG Toolkits have been proved by our research work.
基于多电压下的物理布局问题,可将一块芯片划分成若干个电压区域,在不同电压操作下信号传送于各区域间。本文提出了一种高层综合方法—Tabu搜索法,目的是在多电压的时间和资源限制下实现集成电路功耗最小化。与仅考虑调度的传统方法不同,本文中的Tabu法同时考虑调度和分区,减小了各功能单元及单元间连线的功耗,并能有效地解决在多电压设计中存在的布局问题。利用Tabu搜索法所得的解决方法以三元矢量的形式从调度和分区两个方面说明,应用Tabu表可以避免解决问题方法的多次反复,Tabu表还配有一个校正作用的期望函数,因此该搜索算法具有快速收敛性,能够在更大范围的解的空间找出最优解。实验表明该算法使得电路的平均功耗下降49.6%左右。另外针对多电压下的布局问题还提出模拟退火(Simulated Annealing)法,在时间和资源限制下实现多电压的集成电路功耗最小化,通过对温度的控制对问题求解进行多次迭代。其优点在于能有效地避免了局部搜索算法陷入局部最优的弊端而收敛于全局最优解。实验证明该算法能有效降低电路功耗。
降低频率可以降低功耗,但是单纯地降低频率并不能节省能量。只有在降低频率的同时降低电压,才能真正地降低能量的消耗。多电压下基于动态时钟频率的调度也开始被研究,通过改变电压和时钟频率,能够使系统的功耗降低,从而能够获得高的性能。本文采用多电压和动态频率机制,提出了基于时间约束和资源约束的Gain调度算法及分配方法,它包括两个模块: Allocate_F与Allocate_V。算法的输入是没有调度的数据流图及约束条件,包括资源约束,时间约束条件和工作电压,输出为总能耗及执行时间。实验表明该方案能有效地降低功耗,并且提高系统性能。
此外,基于多电压综合从调度互连两个角度达到低功耗的目的,本文还提出了VLSI高层综合设计方案。该方案基于Gain大小搜索调度,将功耗增益、灵活度和行为执行密度因素作为优先函数,全面地考虑操作的属性。在互连中同时考虑单根总线上的翻转和邻线的耦合。该方案在CDFG工具包中实现并证明了它的有效性,并给出了相应的实验数据。
多核体系是系统向更大规模发展的趋势。从SoC发展到NoC,其主要过程就是它采用网络的通信方式代替传统总线通信方式。对于片上网络来讲,可从物理设计、软件方法以及网络拓扑三个方面来研究减少功耗的方法,各个组件连接形成的网络性能与网络拓朴结构有很密切关系。本文提出一种NoC拓扑结构—Spidernet,其具有平均最短路径小、可平面化的优点、还具有很好的扩展性,并以网络的主要属性:节点度、网络直径、连通度、平均最短路径和平均最短布线几个方面将其与其他拓朴结构进行比较。实验中采用模拟退火的布局映射算法在不同的拓扑结构上运行基准程序,结果表明提出的网络拓扑结构更适合于将来的SoC的片上网络构造。
为了实现并证明所提出的低功耗的算法和方法,本文介绍了高层综合设计中的有效工具--CDFG工具包,文中各章节的实验均在CDFG工具包下进行的。它包括CDFG生成器、CDFG到C(VHDL)的转换器、CDFG剖析器、CDFG阅读器。CDFG工具包为高层次综合设计提供了一套方便实用的工具。通过对CDFG工具包的分析,并将其应用于高层次综合设计,验证了工具包高效方便的辅助设计作用。
With today's increasingly large and complex digital integrated circuit (IC) and system-on-chip designs, power dissipation has emerged as a primary design consideration. Reduction of power consumption in VLSI designs can be achieved at various levels of the design hierarchy, ranging from processing technology, circuit, logic, architectural and algorithmic (behavioral) levels, up to system level. It has also been long recognized that the most dramatic power saving is achievable at the algorithm and architecture levels, where computations are normally described using data/control flow graphs. Thus, in this thesis, a multiple supply voltage IC is synthesized at the high level.
In this thesis, a tabu-search-based behavior level synthesis scheme is proposed to minimize power consumption with resources operating at multiple voltages under the timing and the resource constraints. Unlike the conventional methods where only scheduling is considered, our synthesis scheme considers both scheduling and partitioning simultaneously to reduce power consumption due to the functional units as well as the interconnects among them. In particular, we have configured our solutions as a three-tuple vector to account for both the schedule and the partition. Cycling of the same solutions is prevented by applying a tabu list with an update mechanism enhanced with an aspiration function. In this way, the algorithm can search a large solution space with fast convergence rate. Experiments with a number of DSP benchmarks show that the proposed algorithms achieve an average power reduction by 49.6%.
In this thesis, a Simulated-Annealing-based behavior level synthesis scheme is proposed to minimize power consumption with resources operating at multiple voltages under the timing and the resource constraints. Our synthesis scheme considers both scheduling and partitioning simultaneously to reduce power consumption due to the functional units as well as the interconnects among them. In particular, we have configured our solutions as a three-tuple vector and have got it by many iterations under the controlled temperature. The advantage of this algorithm is that it can avoid local optimization and converge whole optimization. Experiments with a number of DSP benchmarks show that the proposed algorithm is effective for low power design.
In this thesis, a scheduling scheme based on dynamic frequency clocking and multiple voltages is proposed for low power designs under the timing and the resource constraints. Unlike the conventional methods at high level synthesis where only voltages of nodes were considered, the scheme based on a gain function considers both voltage and frequency simultaneously to reduce energy consumption. Experiments with a number of DSP benchmarks show that the proposed scheme achieves an effective energy reduction.
A high level synthesis scheme based on multiple voltages is proposed for low power design in VLSI. This scheme considers both scheduling and interconnection to reduce power. In GAIN scheduling, the priority function includes the power gain, the mobility, and the computation density of an operation. The transition activities on the signal lines and the coupling capacitances of the lines are considered simultaneously in interconnection. This scheme is realized in CDFG Toolkits and its efficiency is proved.
From System-on-chip to Network-on-chip, the main dissimilarity is replacing the bus with the network. How connect, how formative network function is related to topology structure. In this paper we propose a topology structure for NoC, and compare it with other topology networks by five kinds of mainly properties : node degree, network diameter, connectivity, the average most short-circuit path and the average shortest wire length. Experiment results show that this topology has better performance on cost/performance layout.
CDFG Toolkits provide a set of software tools convenient and practical for high level synthesis. The CDFG toolkit includes CDFG generator, CDFG to C (VHDL) converter, CDFG parser, and CDFG viewer. The CDFG Toolkits have been proved by our research work.
引文
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62. Joong-Seok Moon. Low-Power Circuit Techniques for Battery-Powered DSP Applications博士论文, 2003
63. Woonseok Kim. Performance Comparison of Dynamic Voltage Scaling Algorithms for Hard Real-Time Systems. 2002:67-73
64. Dongkun Shin , Jihong Kim. Look-ahead Intra-Task Voltage Scheduling Using Data Flow Information. 2001:87-92
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70. Jinhwan Jeon, Daehong Kim, Dongwan Shin. High-Level Synthesis Under Multi-Cycle Interconnect Delay Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific. 30 Jan.-2 Feb. 2001: 662– 667
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72. N.Magen, A.Kolodny. Interconnect-Power Dissipation in a Microprocessor ,SLIP’04, February 14-15, 2004, Paris, France.
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76. D.Sylvester, C.Hu. Analytical Modeling and Characterization of Deep-submicro Meter Interconnect. Proc. of theIEEE, May 2001,89(5):634–664
77. Wooseung Yang, Chong-MinKyung. Low-Power High-Level Synthesis Using Latche, Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific:462-465
78. Lin Zhong, Jiong Luo. Register Binding Based Power Management for High-level Synthesis of Control-Flow Intensive Behavior. Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD’02)
79. Lin Zhong, Niraj K. Jha. Interconnect-aware High-level Synthesis for LowPower. Electrical Engineering. 2000:110-111
80. Zhenyu (Peter) Gu, Jia Wang, Incremental Exploration of the Combined Physical and Behavioral Design Space ,DAC 2005 June 13–17, 2005, Anaheim, California, USA:208-213
81. Ranga Vemuri, Srinivas Katkoori. An Efficient Register Optimization Algorithm for High-Level Synthesis from Hierarchical Behavioral Specifications . ACM Transactions on Design Automation of Electronic Systems, January 2002,7(1) : 189–216.
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86. J.-M. Chang and M.Pedram, Register Allocation and Binding for Low Power, Proc. of DAC,1996:50-55
87. S. Hong , T. Kim, Bus Optimization for Low Power Dta Path Synthesis Based on Network Flow Method, Proc. of ICCAD,2001;134-138
88. Chun-Gi Lyub, Coupling-Aware High-level Interconnect Synthesis for Low Power, International Conference on Computer-Aided Design, 2002: 609-613
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91.王宏伟,陆俊林,佟冬,程旭.层次化的片上网络,北京大学学报,2007年1期45-49
92. Luca Benini ,Giovanni De Micheli, Networks on Chips: A New SoC Paradigm., DATE, Design, Automation and Test in Europe, Paris, March 3 - 7, 2002
93. Ahmed.Jerraya,HannuTenhunen,Wayne Wolf, Multiprocessor System-on-chips,IEEE Computer magazine, July 2005 , 38(7)
94. J. Dielissen, A. R_adulescu, K. Goossens, and E. Rijpkema, Concepts and implementation of the Philips network-on-chip, IP-Based SoC Design,Nov. 2003:230-235
95. M. Millberg, E. Nilsson, R. Thid, S. Kumar,and A. Jantsch, The Nostrum Backbone– A Communication Protocol Stack for Networks on Chip, Proc. Intl. Conf. VLSI design, 2004
96. S. Lee, S. Song, K. Lee, J. Woo, S. Kim, B.Nam, and H. Yoo, An 800MHz Star-connected on-chip Network for Application to Systems on a Chip, Proc. Intl Solid-State Circuits Conf., Feb. 2003:98-104
97. S. Hong, T. Kim. Bus Optimization for Low Power Data Path Synthesis Based on Network Flow Method. Proc. of ICCAD. 2001:89-94
98. S. Kirkpatrick, C. D. Gelatt, Jr., M. P. Vecchi. Optimization by Simulated Annealing, 13 May 1983, 220( 4598)
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100. F. G.Moraes, N.Calazans, A.Mello, L.M?ller and L.Ost, HERMES: an Infrastructure for Low Area Overhead Packet-switching Networks on Chip, Integration VLSI Journal, 2003: 78-83
101. Daniel Wiklund, Dake Liu, Switched Interconnect for System-on-a-chip Designs, Proc. IP2000 Europe conference, 2000.120-125
102. WilliamJ. Dally , Brian Towles, Route Packets, Not Wires: On-chip Interconnection Networks, in Proceedings of the Design Automation Conference(DAC), Las Vegas, NV, June 2001: 684-689
103. Shashi Kumar, Axel Jantsch, Juha-Pekka Soininen,Martti Forsell, Mikael Millberg Johny Oberg, KariTiensyrja and Ahmed Himani, A Network on Chip Architecture and Design Methodology, Procesidngsof the IEEE computer society annual symposium on VLSI 2002:79-83
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