IC验证方法学研究及AVS视频解码芯片的验证实现
摘要
随着集成电路设计规模和复杂度的不断增大,验证工作越来越重要,往往占到整个开发周期的70%,验证也越来越困难,成了现代数字开发周期的瓶颈。如何快速地搭建一个强大、高效的验证平台是工程师们关注的重点。本文对IC验证方法学进行了研究,并对AVS视频解码芯片进行了高效的验证。
本论文研究了业内常用的高级验证方法学RVM(Reference Verification Methodology)、VMM (Verification Methodology Manual)、AVM (Advanced Verification Methodology)和OVM (Open Verification Methodology),并介绍了常用的验证语言。之后,基于RVM验证方法学,本文利用Vera验证语言搭建了一个层次化验证平台,对AVS视频编解码芯片进行验证。Vera验证完成后,采用Xilinx公司的Virtex-5系列的FPGA芯片xc5vlx220作为目标芯片,对AVS解码器进行FPGA验证。本设计中,AVS视频解码芯片的Vera验证一共开发测试用例2400多条,覆盖率也已达到项目要求,其中行覆盖率为99.2%,条件覆盖率为95%,状态机覆盖率是98.1%,跳转覆盖达95.2%,且平台可重用性较好。
验证结果表明,经FPGA验证处理后的图像数据用matlab'恢复出正确解码图像,且PSNR为27.2dB,图像质量较高,说明本解码芯片解码效果较好。同时测试结果也证明,采用Vera与FPGA可以准确高效地对芯片进行验证。
Verification for digital design is more and more important as the increasing of design scale and complexity of integrated circuit, even reaches 70% of the development cycle. It is also more and more difficult and becoming the bottleneck of the digital development. The engineers are focusing on how to build a powerful and efficient verification platform. With this reason, the IC verification methodologies are studied and the AVS video decoder is verified in this paper.
The common senior verification methodologies are studied in this paper, including RVM (Reference Verification Methodology), VMM (Verification Methodology Manual), AVM (Advanced Verification Methodology) and OVM (Open Verification Methodology). The common verification languages are also introduced. Then, based on RVM, a hierarchical verification platform is built with Vera to verify the AVS video decoder. When it is finished, the FPGA (field-programmable gate array) verification for AVS video decoder is accomplished on the FPGA chip xc5vlx220 of Xilinx Company. In this paper,2400 test cases are developed for AVS video decoder, the code coverage fulfills the requirements of project, the line coverage is 99.2%, the condition coverage is 95%, the fsm coverage is 98.1% and the toggle coverage is 95.2%. The reusability of the platform is fine.
The image data that is processed by FPGA can be converted into significative images. A high PSNR of this 720*576 image with the block size 8×8 is obtained, which is 27.2dB and illustrates the decoded image has high quality. It indicates that the decoder has a good performance. The results show that using Vera and FPGA can verify the ASIC (Application Specific Integrated Circuit) efficiently and accurately.
本论文研究了业内常用的高级验证方法学RVM(Reference Verification Methodology)、VMM (Verification Methodology Manual)、AVM (Advanced Verification Methodology)和OVM (Open Verification Methodology),并介绍了常用的验证语言。之后,基于RVM验证方法学,本文利用Vera验证语言搭建了一个层次化验证平台,对AVS视频编解码芯片进行验证。Vera验证完成后,采用Xilinx公司的Virtex-5系列的FPGA芯片xc5vlx220作为目标芯片,对AVS解码器进行FPGA验证。本设计中,AVS视频解码芯片的Vera验证一共开发测试用例2400多条,覆盖率也已达到项目要求,其中行覆盖率为99.2%,条件覆盖率为95%,状态机覆盖率是98.1%,跳转覆盖达95.2%,且平台可重用性较好。
验证结果表明,经FPGA验证处理后的图像数据用matlab'恢复出正确解码图像,且PSNR为27.2dB,图像质量较高,说明本解码芯片解码效果较好。同时测试结果也证明,采用Vera与FPGA可以准确高效地对芯片进行验证。
Verification for digital design is more and more important as the increasing of design scale and complexity of integrated circuit, even reaches 70% of the development cycle. It is also more and more difficult and becoming the bottleneck of the digital development. The engineers are focusing on how to build a powerful and efficient verification platform. With this reason, the IC verification methodologies are studied and the AVS video decoder is verified in this paper.
The common senior verification methodologies are studied in this paper, including RVM (Reference Verification Methodology), VMM (Verification Methodology Manual), AVM (Advanced Verification Methodology) and OVM (Open Verification Methodology). The common verification languages are also introduced. Then, based on RVM, a hierarchical verification platform is built with Vera to verify the AVS video decoder. When it is finished, the FPGA (field-programmable gate array) verification for AVS video decoder is accomplished on the FPGA chip xc5vlx220 of Xilinx Company. In this paper,2400 test cases are developed for AVS video decoder, the code coverage fulfills the requirements of project, the line coverage is 99.2%, the condition coverage is 95%, the fsm coverage is 98.1% and the toggle coverage is 95.2%. The reusability of the platform is fine.
The image data that is processed by FPGA can be converted into significative images. A high PSNR of this 720*576 image with the block size 8×8 is obtained, which is 27.2dB and illustrates the decoded image has high quality. It indicates that the decoder has a good performance. The results show that using Vera and FPGA can verify the ASIC (Application Specific Integrated Circuit) efficiently and accurately.
引文
[1]杨宗凯,黄建,杜旭,数字专用集成电路的设计与验证[M],电子工业出版社,2004.139～155
[2]Janick Bergeron. Writing Testbenches:Functional Verification of HDL Models.
[3]高文,黄铁军,信源编码标准AVS及其在数字电视中的应用[J],电视技术,2003年第11期,p23-26
[4]黄铁军,AVS知识产权策略与状况知识产权策略与状况,信息技术与标准化,2003年第七期,p3-7
[5]黄丽,百万门级专用集成电路的FPGA验证[D],西安电子科技大学硕士论文学位,2007
[6]陈迅,X微处理器功能验证方法研究[D],国防科学技术大学硕士论文学位,2005.1,p1-3
[7]叶茂,基于VMM的验证平台的研究与实现,华中科技大学硕士学位论文,2008
[8]张亚楠,申敏,游敏惠,基于RVM的可重用测试方法及应用[J],重庆邮电学院学报(自然科学版),2006
[9]丁婷婷,申敏,左春生,RVM的分层式验证平台及覆盖率驱动技术[J],微计算机信息,2008
[10]Mark Glasser, Adam Rose, Tom Fitzpatrick, Dave Rich, Harry Foster, Advanced Verification Methodology Cookbook[M],2006.12
[11]Mentor, AVM Users Guide for Dummies,2006
[12]Mentor, Open Verification Methodology Datasheet,2007
[13]王青,李强,利用OVM实现基于Class的高效仿真验证环境[J],2009.1
[14]夏宇闻,Verilog数字系统设计教程[M],北京航空航天大学出版社,2005.
[15]Open Verification Library Reference Manual, Accellera, California,2003
[16]夏宇闻,SystemVerilog简介[J],夏宇闻,中国集成电路,2006
[17]李伟丹,基于FPGA的AVS帧内解码关键技术的实现[D],暨南大学硕士论文学位,2008
[18]贾惠柱,解晓东,高文,基于软硬件分区的AVS高清视频解码器结构[J]计算机研究与发展2008年第3期,p510-518
[19]GB／T200090.2-2006,信息技术-先进音视频编码-第2部分：视频[S]
[20]藤勇.中国网通：AVS IPTV产业化的实践与创新[J].中国数字电视,2007,11(39)：68-69
[21]毕厚杰,新一代视频压缩编码标准-H.264/AVC[M].北京：人民邮电出版社,2005：53-65
[22]Xilinx,Virtex-5 Family Advanced Packaging.2006.5
[23]FU Fangfang, YI Qingming, SHI Min, Functional Verification based on FPGA for AVS Video Decoder[J], Semiconductor Photonics And Technology,2009
[24]沈理,SOC/ASIC设计、验证和测试方法学[M]中山大学出版社2006.3
[25]徐英伟,刘佳.SoC功能验证的特点和方法.微处理器.2006
[26]张新伟,基于RVM的I2C总线控制器的验证[J],科苑杂谈,2007
[27]Janick Bergeron, Eduard Cerny, Alan Hunter, Andrew Nightingale, SystemVerilog验证方法学[M],北京航空航天大学出版社,2007
[28]吕欣欣,刘淑芬,基于Synopsys VMM方法的FPGA验证技术[J],计算机应用,2009.9
[29]罗登富,赵建明,基于VMM的ASIC建模验证[J],科技经济市场技术平台,2008
[30]Stephen Bailey, Comparison of VHDL,Verilog and SystemVerilog[R], Digital Simulatiom White Paper
[31]Synopsys, OpenVera Language Reference Manual[R],2005
[32]Synopsys, Reference Verification Methodology User Guide[R],2005
[33]Vera User Guide-X2005.06-SP1.Synopsys.September 2005 [R],2005
[34]Victor Besyakov, David Shleifman. Constrained Random Test Environmentfor Soc Verification Using Vera.SNUG Israel
[35]Kevin Thompson,Ladd Williamson.Block-Based ASIC Verification UsingVera.SNUG San.Jose,2003
[36]张利峰,基于Vera语言的MAC验证环境实现[D],西安电子科技大学硕士论文学位,2007
[37]Charles Li,Ashesh Doshi.Five Vital Steps to a Robust Testbench with Design Ware Verification IP and RVM.2005.8.Synopsys.Inc
[38]孙航,Xilinx可编程逻辑器件的高级应用与设计技巧[M],电子工业出版社,2004
[39]薛小刚,葛毅敏,Xilinx ISE 9.x FPGA/CPLD设计指南[M],人民邮电出版社,2007
[40]飞思科技产品研发中心,MATLAB6.5辅助图像处理[M],电子工业出版社,2003.1
[41]清源计算机工作室,MATLAB6.0基础及应用[M],机械工业出版社2001.5
[2]Janick Bergeron. Writing Testbenches:Functional Verification of HDL Models.
[3]高文,黄铁军,信源编码标准AVS及其在数字电视中的应用[J],电视技术,2003年第11期,p23-26
[4]黄铁军,AVS知识产权策略与状况知识产权策略与状况,信息技术与标准化,2003年第七期,p3-7
[5]黄丽,百万门级专用集成电路的FPGA验证[D],西安电子科技大学硕士论文学位,2007
[6]陈迅,X微处理器功能验证方法研究[D],国防科学技术大学硕士论文学位,2005.1,p1-3
[7]叶茂,基于VMM的验证平台的研究与实现,华中科技大学硕士学位论文,2008
[8]张亚楠,申敏,游敏惠,基于RVM的可重用测试方法及应用[J],重庆邮电学院学报(自然科学版),2006
[9]丁婷婷,申敏,左春生,RVM的分层式验证平台及覆盖率驱动技术[J],微计算机信息,2008
[10]Mark Glasser, Adam Rose, Tom Fitzpatrick, Dave Rich, Harry Foster, Advanced Verification Methodology Cookbook[M],2006.12
[11]Mentor, AVM Users Guide for Dummies,2006
[12]Mentor, Open Verification Methodology Datasheet,2007
[13]王青,李强,利用OVM实现基于Class的高效仿真验证环境[J],2009.1
[14]夏宇闻,Verilog数字系统设计教程[M],北京航空航天大学出版社,2005.
[15]Open Verification Library Reference Manual, Accellera, California,2003
[16]夏宇闻,SystemVerilog简介[J],夏宇闻,中国集成电路,2006
[17]李伟丹,基于FPGA的AVS帧内解码关键技术的实现[D],暨南大学硕士论文学位,2008
[18]贾惠柱,解晓东,高文,基于软硬件分区的AVS高清视频解码器结构[J]计算机研究与发展2008年第3期,p510-518
[19]GB／T200090.2-2006,信息技术-先进音视频编码-第2部分：视频[S]
[20]藤勇.中国网通：AVS IPTV产业化的实践与创新[J].中国数字电视,2007,11(39)：68-69
[21]毕厚杰,新一代视频压缩编码标准-H.264/AVC[M].北京：人民邮电出版社,2005：53-65
[22]Xilinx,Virtex-5 Family Advanced Packaging.2006.5
[23]FU Fangfang, YI Qingming, SHI Min, Functional Verification based on FPGA for AVS Video Decoder[J], Semiconductor Photonics And Technology,2009
[24]沈理,SOC/ASIC设计、验证和测试方法学[M]中山大学出版社2006.3
[25]徐英伟,刘佳.SoC功能验证的特点和方法.微处理器.2006
[26]张新伟,基于RVM的I2C总线控制器的验证[J],科苑杂谈,2007
[27]Janick Bergeron, Eduard Cerny, Alan Hunter, Andrew Nightingale, SystemVerilog验证方法学[M],北京航空航天大学出版社,2007
[28]吕欣欣,刘淑芬,基于Synopsys VMM方法的FPGA验证技术[J],计算机应用,2009.9
[29]罗登富,赵建明,基于VMM的ASIC建模验证[J],科技经济市场技术平台,2008
[30]Stephen Bailey, Comparison of VHDL,Verilog and SystemVerilog[R], Digital Simulatiom White Paper
[31]Synopsys, OpenVera Language Reference Manual[R],2005
[32]Synopsys, Reference Verification Methodology User Guide[R],2005
[33]Vera User Guide-X2005.06-SP1.Synopsys.September 2005 [R],2005
[34]Victor Besyakov, David Shleifman. Constrained Random Test Environmentfor Soc Verification Using Vera.SNUG Israel
[35]Kevin Thompson,Ladd Williamson.Block-Based ASIC Verification UsingVera.SNUG San.Jose,2003
[36]张利峰,基于Vera语言的MAC验证环境实现[D],西安电子科技大学硕士论文学位,2007
[37]Charles Li,Ashesh Doshi.Five Vital Steps to a Robust Testbench with Design Ware Verification IP and RVM.2005.8.Synopsys.Inc
[38]孙航,Xilinx可编程逻辑器件的高级应用与设计技巧[M],电子工业出版社,2004
[39]薛小刚,葛毅敏,Xilinx ISE 9.x FPGA/CPLD设计指南[M],人民邮电出版社,2007
[40]飞思科技产品研发中心,MATLAB6.5辅助图像处理[M],电子工业出版社,2003.1
[41]清源计算机工作室,MATLAB6.0基础及应用[M],机械工业出版社2001.5