基于空间特性优化的映射布局算法研究
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摘要
随着半导体工艺技术的发展,集成电路设计者能够将越来越复杂的电路功能集成到单硅片上,并最终在20世纪90年代中期开发出SoC(System on Chip,系统芯片)。SoC代表着集成电路向集成系统转变的大方向。但是,随着SoC中所包含的IP核数目增至成千上万的时候,现有的以总线结构为通信基础的SoC技术面临着在性能、功耗、延时和可靠性等方面的巨大挑战。为了解决复杂SoC所面临的问题,在2001年左右,一些研究机构借鉴和吸收通信网络中的一些思想,提出了以通信为核心的复杂SoC的IP核的集成方法,即片上网络(Network on Chip,NoC).
本文的研究工作主要集中在一下几个方面,首先对目前片上网络设计中的路由算法,交换技术,帧传输技术,网络拓扑,映射布局等方面做了详细的介绍。其次,本文提出一种基于贪心思想的映射布局算法,本文集中讨论了几种常用的数据结构方式：0-tree, B*tree,队列结构,Map结构。随着应用负载的形式与种类的不断地增多,0-tree以及B*tree结构无法满足不规则应用负载以及非联通负载的要求。本文算法采用更加灵活的队列结构对映射布局进行建模,使用队列结构移动模块的时间复杂度仅为0(1),旋转模块的时间复杂度为0(n),计算解的质量的时间复杂度为0(a3)。通过Map结构的辅助,计算解的质量的时间复杂度降低为0(a2)。
在本文中使用了一些新的技术,如：标志位标示法,动态窗口策略,初始布局优化方法,移动估值矩阵等。标志位标示法解决了Map结构中重叠模块无法分离的问题。动态窗口策略解决了使贪心算法获得全局搜索能力,避免了映射布局算法中陷入局部最优解的问题。初始布局优化以及移动估值矩阵方法为布局算法中的优化技术,通过这些优化技术使算法的收敛速度加快。通过实验看出,改进后的贪心布局算法比较目前较为常见的模拟退火算法,运行时间降低了70%左右,解的质量提升7%左右。并且根据对迭代数据的追踪发现,改进后的贪心布局算法更为高效,稳定。
As development of semiconductor process technology, IC designers can integrate more and more complex circuit functions into a single silicon wafer, and ultimately the SoC (System on Chip) was developed in the 20th century. SoC represents the development of integrated circuits. However, as the number of IP core of SoC increased to more than thousands, bus-based SoC communication technology faces enormous challenges in performance, power consumption, delay, and reliability. In order to solve problems complex SoC faced, in 2001, some research institutions refer to the traditional network and propose a integrated method of complex SoC that focus on communication. It is NoC (Network on Chip).
My research focuses on following aspects, first of all some technology was presented,such as the current routing algorithm, switching technology, the frame transmission technology, network topology, mapping and layout. Secondly, a mapping algorithms based on greedy was proposed in the paper. Several common data structures were compared in the paper.such as O-tree, B* tree, queue structure, Map structure. With the type of application module constantly increasing, O-tree and B* tree structure can't express the irregular application module and non-unicom application module. So the algorithm uses a more flexible queue structure to express application module. when the queue structure was used, the time complexity of moving the module is O (1) in the algorithm, rotating the module is O (n), Calculating the quality of the layout is O (a3). If the Map structure were used for assisting my algorithm, the time complexity of Calculating the quality of the layout reduces to O (a2).
In addition, some new techniques were introduced to improve efficiency of this algorithm, such as:Marker bit method, dynamical selection and weight matrix, Initialize the layout. In order to solving overlapping and connection problems,Marker bit method is proposed in this paper to merge and separate different modules. Through the dynamical selection, Greedy has an ability of global selection which avoid to get local solution. Initial layout optimization and weight matrix make Greedy more efficient. From the experiments and comparison with Simulated Annealing algorithm, the running time reduce about 70%,the quality of solution increases about 7%.on the other hand, through tracking those algorithm,improved Greedy algorithm shows better stability and accuracy.
本文的研究工作主要集中在一下几个方面,首先对目前片上网络设计中的路由算法,交换技术,帧传输技术,网络拓扑,映射布局等方面做了详细的介绍。其次,本文提出一种基于贪心思想的映射布局算法,本文集中讨论了几种常用的数据结构方式：0-tree, B*tree,队列结构,Map结构。随着应用负载的形式与种类的不断地增多,0-tree以及B*tree结构无法满足不规则应用负载以及非联通负载的要求。本文算法采用更加灵活的队列结构对映射布局进行建模,使用队列结构移动模块的时间复杂度仅为0(1),旋转模块的时间复杂度为0(n),计算解的质量的时间复杂度为0(a3)。通过Map结构的辅助,计算解的质量的时间复杂度降低为0(a2)。
在本文中使用了一些新的技术,如：标志位标示法,动态窗口策略,初始布局优化方法,移动估值矩阵等。标志位标示法解决了Map结构中重叠模块无法分离的问题。动态窗口策略解决了使贪心算法获得全局搜索能力,避免了映射布局算法中陷入局部最优解的问题。初始布局优化以及移动估值矩阵方法为布局算法中的优化技术,通过这些优化技术使算法的收敛速度加快。通过实验看出,改进后的贪心布局算法比较目前较为常见的模拟退火算法,运行时间降低了70%左右,解的质量提升7%左右。并且根据对迭代数据的追踪发现,改进后的贪心布局算法更为高效,稳定。
As development of semiconductor process technology, IC designers can integrate more and more complex circuit functions into a single silicon wafer, and ultimately the SoC (System on Chip) was developed in the 20th century. SoC represents the development of integrated circuits. However, as the number of IP core of SoC increased to more than thousands, bus-based SoC communication technology faces enormous challenges in performance, power consumption, delay, and reliability. In order to solve problems complex SoC faced, in 2001, some research institutions refer to the traditional network and propose a integrated method of complex SoC that focus on communication. It is NoC (Network on Chip).
My research focuses on following aspects, first of all some technology was presented,such as the current routing algorithm, switching technology, the frame transmission technology, network topology, mapping and layout. Secondly, a mapping algorithms based on greedy was proposed in the paper. Several common data structures were compared in the paper.such as O-tree, B* tree, queue structure, Map structure. With the type of application module constantly increasing, O-tree and B* tree structure can't express the irregular application module and non-unicom application module. So the algorithm uses a more flexible queue structure to express application module. when the queue structure was used, the time complexity of moving the module is O (1) in the algorithm, rotating the module is O (n), Calculating the quality of the layout is O (a3). If the Map structure were used for assisting my algorithm, the time complexity of Calculating the quality of the layout reduces to O (a2).
In addition, some new techniques were introduced to improve efficiency of this algorithm, such as:Marker bit method, dynamical selection and weight matrix, Initialize the layout. In order to solving overlapping and connection problems,Marker bit method is proposed in this paper to merge and separate different modules. Through the dynamical selection, Greedy has an ability of global selection which avoid to get local solution. Initial layout optimization and weight matrix make Greedy more efficient. From the experiments and comparison with Simulated Annealing algorithm, the running time reduce about 70%,the quality of solution increases about 7%.on the other hand, through tracking those algorithm,improved Greedy algorithm shows better stability and accuracy.
引文
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[35].R. Ho, K. Mai, M. Horowitz, The Future of Wires[C], Proc. IEEE, Apr.2001, pp.490-504.
[36].S.Kumar,A.Jantsch,J.Soininen,et al A networks on chip architecture and design methodology [J],Proceedings of IEEE Computer SocietyAnnual Symposium on VLSI,2002:105-112.
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[38].Leiserson, Fat-trees:Universal Networks for Hardware-Efficient Supercomputing [J], IEEE Transaction on Computers,34(10),1985:892-901.
[39].Marcello Coppola,Riccardo Locatelli,Giuseppe Maruccia,et al, Spidergon:a novel on-chip communication network[C],System-on-Chip,2004. Proceedings.2004 International Symposiumon,2004:15-18.
[40].F.Karim et al. An Interconnect Architecture for Networking Systems on Chips[J], IEEE Micro,22(5),2002:36-45.
[41].岳培培,刘建Sheraz Anjum,等基于遗传算法的NoC路径分配算法[J]微电子学与计算机2008 25(4)：48-71
[42].刘有耀,杜慧敏,韩俊刚.NoC关键问题[J],计算机科学200835(2)：13-15
[43]. Bolotin E, Cidon I, Ginosar R, et al. QNoC:QoS architecture and design process for network on chip[J]. Journal of Systems Architecture, special issue on Network on Chip, February 2004,50:105-128
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[2]. GUERRIER P, GREINER A. A generic architecture for on-chip packet switched interconnections [C] Proc of Design Automation and Test in Europe Conf and Exhibition. Paris,France,2000.
[3]. HEMANI A, JANTSCH A, KUMAR S, et al. Network on chip:an architecture for billion transistor era [C] Proc of the IEEE NoC Conf. Turku, Finland,2000
[4]. Bertozzi D,Benini L. Xpipes, A Network-on-Chip Architecture for Gigascale Systems-on-Chip[C] IECircuit s and Systems Magazine,2004 (4):18-31
[5]. S. Kumar, A. Jantsch, J.-P. Soininen, et. al, A network on chip architecture and design methodology[C] USA, Proc. of IEEE Computer SoCiety Annual Symposium on VLSI, April 2002.pp.117-124,
[6].罗浩SoC系统概述[J]湖北水利水电职业技术学院学报2006(1)35-39
[7]. C. Kim, D. Burger, et. al, An Adaptive, Non-Uniform Cache Structure for Wire-Delay Dominated On-Chip Caches[C], ASPLOS 2002.
[8].高明伦杜高明NoC：下一代集成电路主流设计技术[J]微电子学2006(04)：44-48
[9]. Hemani A, Jantsch A,Kumar S,et al. Network on a chip:an architecture for billion transistor era.[C] In:Proc. IEEE NoC Conference,2000.166-173
[10]. Ye T. On-chip multiprocessor communication network design and analysi [C]. USA. Stanford University,2003
[11].周干民.NoC基础研究[D].合肥：合肥工业大学,2005
[12].高明伦,杜高明.NoC：下一代集成电路主流设计技术[J].微电子学,2006,36(4)：461-466.
[13]. A. Agrawal, Raw Computation[J] Scientific Am.Aug.1999, pp.60-63.
[14]. Jun Wang, Ge Zhang, Weiwu Hu. An Efficient Error Control Scheme for Chip-to-Chip Optical Interconnects. [C] Proceedings of IEEE International Symposium on Circuits and Systems,May 27-30,2007.
[15]张旭NoC通信节点设计技术研究[D]西安西安电子科技大学2009
[16]. Wendell Odom, Cisco网络设备互连[M]李祥瑞(译)人民邮电出版社2006
[17]. L. Benini, D. Micheli, System-Level Power Optimization:Techniques and Tools[C] ACM Trans.Design Automation of Electronic Systems, Apr.2000,pp.115-192.
[18]. R. Hegde, N. Shanbhag, Toward Achieving Energy Efficiency in Presence of Deep Submicron Noise[C], IEEE Trans. VLSI Systems, Aug.2000, pp.379-391.
[19]. W. Dally, J. Poulton, Digital Systems Engineering[D], New York,Cambridge Univ. Press, 1998.
[20]. J. Duato, S. Yalamanchili, and L. Ni, Interconnection Networks:An Engineering Approach[C], Calif., IEEE CS Press, Los Alamitos,1997.
[21]. Adriahantenaina A, Charlery H, Greiner A, et al. SPIN:A Scalable, Packet Switched, On-Chip Micro-Network[C]. Proceedings of the Conference on Design, Automation and Test in Europe:Designers'Forum, March 03207,2003.20070-20073
[22]. Hemayet Hossain, Mostak Ahmed and Abdullah Al-Nayeem GpNoCSim-A general purpose simulator for network-on-chip[C],[S.1] ICICT2007
[23]. Jiang Xu, Wayne Wolf, Wei Zhang, Double-Data-Rate, Wave-Pipelined Interconnect for Asynchronous NoCs[C], IEEE Micro, June 2009.
[24]. Jiang Xu, Wayne Wolf, Joerg Henkel,et al, A Design Methodology for Application-Specific Networks-on-Chip[C], ACM Transactions on Embedded Computing Systems, July 2006.
[25]. Tiehan Lv, Jiang Xu, I. Burak Ozer,et al, A Methodology for Architectural Design of Multimedia Multiprocessor Systems-on-Chips[C], IEEE Design and Test of Computers, December 2004.
[26]李磊片上网络NoC的通信研究[D]浙江浙江大学博士论文2007
[27]. Xiaotao Chang, Mingming Zhang, Ge Zhang,et al. Adaptive Clock Gating Technique for Low Power IP Core Design in SoC [C]. Proceedings of IEEE International Symposium on Circuits and Systems,2007.
[28]. Ge Zhang, Yongjun Xu, Jiye Zhao. A Novel Heuristic Approach for Bounding Maximum and Minimum Leakage Power[C]. Proceedings of the 6th International Conference on ASIC, October 24-27,2005, pp.1027-1030.
[29]. Kun Huang, Jun Wang, Ge Zhang. An Innovative Power-Efficient Architecture for Input Buffer of Network on Chip[C]. Proceedings of IEEE International Conference on Integration Technology,2007.
[30]. Ge Zhang, Kun Huang, Haihua Shen, Feng Zhang. Low Power Techniques on a High Speed Floating-point Adder Design[C]. Proceedings of IEEE International Conference on Integration Technology,2007.
[31]. Hu weiwu, Zhang fuxin, Li zusong, Microarchitecture of the Godson-Processor[J], Computer Science and Technology,2005,20(2):243-249.
[32].Wang ling,Piao Shouye,Jiang Yingtao.On A Web-Graph-Based Micronetwork Architecture for SoCs[C].IEEE,mwscas/newcas,2007.
[33]. J. Walrand, P. Varaiya, High-Performance Communication Networks[C], Morgan Kaufmann, San Francisco,2000.
[34]. P. Guerrier, A. Grenier, A Generic Architecture for On-Chip Packet-Switched Interconnections[C], Proc. IEEE Design Automation and Test in Europe (DATE 2000), IEEE Press, Piscataway, N.J.,2000, pp.250-256.
[35].R. Ho, K. Mai, M. Horowitz, The Future of Wires[C], Proc. IEEE, Apr.2001, pp.490-504.
[36].S.Kumar,A.Jantsch,J.Soininen,et al A networks on chip architecture and design methodology [J],Proceedings of IEEE Computer SocietyAnnual Symposium on VLSI,2002:105-112.
[37].W.Dally,B.Towles,Route Packets, NotWires:On-Chip Interconnection Networks[C], Proceedings. The 38th Design Automation Conference,2001(6):684-689
[38].Leiserson, Fat-trees:Universal Networks for Hardware-Efficient Supercomputing [J], IEEE Transaction on Computers,34(10),1985:892-901.
[39].Marcello Coppola,Riccardo Locatelli,Giuseppe Maruccia,et al, Spidergon:a novel on-chip communication network[C],System-on-Chip,2004. Proceedings.2004 International Symposiumon,2004:15-18.
[40].F.Karim et al. An Interconnect Architecture for Networking Systems on Chips[J], IEEE Micro,22(5),2002:36-45.
[41].岳培培,刘建Sheraz Anjum,等基于遗传算法的NoC路径分配算法[J]微电子学与计算机2008 25(4)：48-71
[42].刘有耀,杜慧敏,韩俊刚.NoC关键问题[J],计算机科学200835(2)：13-15
[43]. Bolotin E, Cidon I, Ginosar R, et al. QNoC:QoS architecture and design process for network on chip[J]. Journal of Systems Architecture, special issue on Network on Chip, February 2004,50:105-128
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