纳米工艺集成电路可寻址测试芯片设计方法研究
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摘要
测试芯片作为集成电路制造工艺提取工艺器件参数,评估工艺设备性能,制定版图设计规则,检测工艺缺陷以及评估产品可靠性的重要手段,对缩短工艺开发周期、提升成品率起着重要的作用。随着集成电路进入纳米工艺时代,复杂的制造工艺对测试芯片的测试需求不断增加。测试芯片可寻址的设计方法由于能在有限的晶圆面积上对大量的测试结构进行测量,而成为当前制造工艺领域的一大研究热点。本文围绕高测量精度、更高面积利用率的可寻址测试芯片的设计方法展开了以下方面的研究：
1)针对工艺开发初始阶段工艺缺陷检测的需要,提出了一种大型可寻址测试芯片的电路设计方法。每个测试结构采用四端法连接以及使用单一的IO NMOS晶体管作为开关电路的做法,既提高了测试结构的阻值/漏电测量精度,又使得测试结构阵列规模可以很大,提高了面积利用率。该方法通用性强、工艺可移植性好,已在65nmCMOS制造工艺得到验证。
2)针对缺陷失效分析对缺陷精细定位的需求,对1)进行扩展。物理定位设备上能够提供的探针数量很少(<10),不足以让大型寻址电路正常工作以维持测试结构到PAD的通路。对此,利用原有电路仅增加少量探针引脚让所有的测试结构共用,并将维持测试结构到探针引脚的通路需要的探针数量减少到3个。该方法在110nmCMOS工艺的应用实例中得到证明,并成功定位到对该工艺的金属断路缺陷,并得到有效的失效分析。
3)将1)的设计方法应用到工艺量产阶段工艺缺陷检测,并针对划片槽狭长的特点,提出了适合的版图设计方法。将整个版图分成多个独立的模块,每个模块单独设计,而且模块的设计被定制为几种固定的类型。该方法简化了版图设计工作,而且使得设计的版图自动化程度高、扩展性强、工艺可移植性好。该方法在45nm CMOS制造工艺得到验证。
4)针对工艺波动引起的MOS器件性能变异检测、诊断、建模的需要,提出一种划片槽MOS器件可寻址的设计方法。该方法可以同时摆放240个MOS器件,并能准确测量每个MOS管的饱和电流、亚阈值漏电、栅极漏电以及阈值电压VT。而且芯片生产至金属层2时即可展开测试,缩短了测试周期。该方法在28nm CMOS制造工艺得到验证。
As the main approach to extract parameters, assess processing tool performance, formulating layout design rules, detect or quantify random and systematic defects, establish product reliability, test chips play an important role in reducing process development cycle and improving manufacturing yield. However, the increasingly complicated processes of nano-era require a lot more test structures than the amount that traditional test chips can accommodate. Under such a circumstance, addressable test chips emerge as the solution and become a hot research area. We have focused on this area and the main content of the thesis is the design methodology of high-density and high-accuracy addressable test chips. Next is a summary of our research contents and innovations:
Proposed an large-scale addressable test chip design scheme for process defects detection during the development of a new technology node. In our design, we make all the test structures four-terminal connected and implement the switch by thick-oxide NMOS transistor, thus improve the design of addressable test chip on measurement accuracy, array size as well as area efficiency. This design scheme has been verified by a64X64large-scale test chip in a65nm CMOS technology node. And also it has strong universality and can be well transferred to another technology node.
Expanded the application of the above design scheme to the fault location of failure analysis. Manual probing system fails to provide enough probes to perform fault location techniques. Another group of PADs are added, and all the test structures can share these PADs. Only three PADs are needed for each fault location, which make the fault location techniques feasible by using manual probing system. This specialized design scheme has been verified in a110nm CMOS technology node.
Applied the first mentioned design scheme for process defects detection during the process stage of mass production. A suitable layout design method is proposed to implement the design scheme in the limited space of scribe line. The whole layout is divided into several modules with separate design, and the design of the module is customized to some types. Such layout design method simplifies the work of the design, and makes it possible that the layout is highly automation, well extensibility and also easy to be transferred to another technology node. This layout design method has been verified in a45nm CMOS technology node.
Proposed a MOS transistor array design scheme for characterization and modeling of statistical variations in MOSFET characteristics. The proposed array achieves both compact layout area with240devices placed in scribe line and accurate measurement of saturation region current, sub-threshold current, sub-threshold voltage and gate leakage. Also to reduce the testing cycle, the array has been implemented with two levels of metal. This design scheme has been verified in a28nm CMOS technology node.
1)针对工艺开发初始阶段工艺缺陷检测的需要,提出了一种大型可寻址测试芯片的电路设计方法。每个测试结构采用四端法连接以及使用单一的IO NMOS晶体管作为开关电路的做法,既提高了测试结构的阻值/漏电测量精度,又使得测试结构阵列规模可以很大,提高了面积利用率。该方法通用性强、工艺可移植性好,已在65nmCMOS制造工艺得到验证。
2)针对缺陷失效分析对缺陷精细定位的需求,对1)进行扩展。物理定位设备上能够提供的探针数量很少(<10),不足以让大型寻址电路正常工作以维持测试结构到PAD的通路。对此,利用原有电路仅增加少量探针引脚让所有的测试结构共用,并将维持测试结构到探针引脚的通路需要的探针数量减少到3个。该方法在110nmCMOS工艺的应用实例中得到证明,并成功定位到对该工艺的金属断路缺陷,并得到有效的失效分析。
3)将1)的设计方法应用到工艺量产阶段工艺缺陷检测,并针对划片槽狭长的特点,提出了适合的版图设计方法。将整个版图分成多个独立的模块,每个模块单独设计,而且模块的设计被定制为几种固定的类型。该方法简化了版图设计工作,而且使得设计的版图自动化程度高、扩展性强、工艺可移植性好。该方法在45nm CMOS制造工艺得到验证。
4)针对工艺波动引起的MOS器件性能变异检测、诊断、建模的需要,提出一种划片槽MOS器件可寻址的设计方法。该方法可以同时摆放240个MOS器件,并能准确测量每个MOS管的饱和电流、亚阈值漏电、栅极漏电以及阈值电压VT。而且芯片生产至金属层2时即可展开测试,缩短了测试周期。该方法在28nm CMOS制造工艺得到验证。
As the main approach to extract parameters, assess processing tool performance, formulating layout design rules, detect or quantify random and systematic defects, establish product reliability, test chips play an important role in reducing process development cycle and improving manufacturing yield. However, the increasingly complicated processes of nano-era require a lot more test structures than the amount that traditional test chips can accommodate. Under such a circumstance, addressable test chips emerge as the solution and become a hot research area. We have focused on this area and the main content of the thesis is the design methodology of high-density and high-accuracy addressable test chips. Next is a summary of our research contents and innovations:
Proposed an large-scale addressable test chip design scheme for process defects detection during the development of a new technology node. In our design, we make all the test structures four-terminal connected and implement the switch by thick-oxide NMOS transistor, thus improve the design of addressable test chip on measurement accuracy, array size as well as area efficiency. This design scheme has been verified by a64X64large-scale test chip in a65nm CMOS technology node. And also it has strong universality and can be well transferred to another technology node.
Expanded the application of the above design scheme to the fault location of failure analysis. Manual probing system fails to provide enough probes to perform fault location techniques. Another group of PADs are added, and all the test structures can share these PADs. Only three PADs are needed for each fault location, which make the fault location techniques feasible by using manual probing system. This specialized design scheme has been verified in a110nm CMOS technology node.
Applied the first mentioned design scheme for process defects detection during the process stage of mass production. A suitable layout design method is proposed to implement the design scheme in the limited space of scribe line. The whole layout is divided into several modules with separate design, and the design of the module is customized to some types. Such layout design method simplifies the work of the design, and makes it possible that the layout is highly automation, well extensibility and also easy to be transferred to another technology node. This layout design method has been verified in a45nm CMOS technology node.
Proposed a MOS transistor array design scheme for characterization and modeling of statistical variations in MOSFET characteristics. The proposed array achieves both compact layout area with240devices placed in scribe line and accurate measurement of saturation region current, sub-threshold current, sub-threshold voltage and gate leakage. Also to reduce the testing cycle, the array has been implemented with two levels of metal. This design scheme has been verified in a28nm CMOS technology node.
引文
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