应用于SoC的频率综合器的ASIC设计
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摘要
本文根据阅读器芯片的总体要求,基于SMIC 0.18μm CMOS工艺库,完成了两种数字频率合成器的ASIC设计。其中一种是基于ROM结构的直接数字频率合成器(Direct Digital Synthesizer,DDS);另一种是全数字锁相环(All-Digital PLL,ADPLL)。
在DDS芯片设计中,分析了DDS具体应用要求,确定了DDS的系统结构和性能参数,完成了具体子模块的电路设计。其中累加器采用进位链和流水线相结合的方式,提高了工作频率的同时降低了资源占用率;ROM模块应用以正弦函数1/4波形对称性为基础,并结合Hutchison相交分离法的改进压缩算法,压缩率达到49倍,降低了芯片的功耗和面积。基于SMIC 0. 18μm CMOS工艺库完成了DDS芯片的后端物理设计和后仿真。最终,所设计的DDS由Astro生成的版图面积为260×260μm~2,等效两输入门数为1021,平均总功耗为7.79mw,频率分辨率为0.058Hz,输出频率为14.65MHz时,杂散大于70dB,最高输出频率达到100MHz。
在ADPLL芯片设计中,电路采用了带有使能控制的环形数控振荡器结构。环形结构分为粗调和精调两部分,具有锁定范围宽、锁定精度高、功耗低的特点,且捕获范围可以根据需要进一步拓宽。与传统锁相环设计不同,本设计基于CMOS标准单元,所有子模块均采用可综合的Verilog HDL代码描述,利于不同工艺间的移植,设计周期和复杂度大大降低。最终,所设计的ADPLL带宽可达72.95MHz-353.66MHz,频率增益为2.47ps,锁定时间小于35个参考时钟周期。输出300MHz时钟时,峰峰值抖动168ps,RMS抖动38.42ps。1.8V电源电压下,DCO功耗范围为0.7mw-1.52mw。最终完成的全数字锁相环版图面积为274μm×274μm,等效门两输入与非门数为4006。
Based on the general requirements of the readers , two ASIC designs of frequency synthesizer were implemented with SMIC 0.18μm CMOS technology library in this paper. One is a direct digital synthesizer based on ROM structure ; the other is an all-digital phase-locked loop.
In the DDS chip designing ,based on the analysis of specific application requirements of DDS, the paper defined the main performance parameters and system structure, and designed the sub-module circuits . The accumulator module combined the carry line and pipelined architecture together to improve the frequency and reduce the resource utilization; the compression algorithm in ROM module is based on the 1/4 symmetry of sine function and Hutchison algorithm, which made the compression ratio as high as 49 times . What’s more , the power consumption and die area had been greatly reduced . The back-end physical design and simulation had been finished in SMIC’s 0.18μm CMOS process. The finished area of the DDS layout is 260×260μm~2, and the equivalent gate count is 1021. The average power consumption is 7.79mw. The frequency resolution is 0.058Hz ; when the output frequency is 14.65MHz, the stray is more than 70dB. The highest operation frequency of DDS is up to 100MHz .
In the ADPLL chip designing, the ADPLL had a ring digital-controlled oscillator composed by enabled units, with the ring structure divided into two parts in terms of the coarse tuning part and the fine tuning part. It included the characteristic of wide locking range, high locking resolution, and low power consumption. What’s more, the locking range can be further expended according to the demand. Different from the traditional design, this design was based on CMOS standard cells and used synthesizable Verilog HDL for sub-modules description, so it could be easily implanted to different processes, and both the design time and complexity could be reduced. This ADPLL can operate from 72.95MHz to 353.66 MHz, the resolution is 2.47 ps , the locking time is smaller than 35 cycles. When the output frequency is 300MHz ,the peak-to-peak jitter is 168ps and RMS jitter is 38.42ps. With a 1.8V power supply, the proposed DCO has a power consumption range from 0.7mw to 1.52mw. The finished area of the ADPLL layout is 274μm×274μm, and the equivalent gate count is 4006.
在DDS芯片设计中,分析了DDS具体应用要求,确定了DDS的系统结构和性能参数,完成了具体子模块的电路设计。其中累加器采用进位链和流水线相结合的方式,提高了工作频率的同时降低了资源占用率;ROM模块应用以正弦函数1/4波形对称性为基础,并结合Hutchison相交分离法的改进压缩算法,压缩率达到49倍,降低了芯片的功耗和面积。基于SMIC 0. 18μm CMOS工艺库完成了DDS芯片的后端物理设计和后仿真。最终,所设计的DDS由Astro生成的版图面积为260×260μm~2,等效两输入门数为1021,平均总功耗为7.79mw,频率分辨率为0.058Hz,输出频率为14.65MHz时,杂散大于70dB,最高输出频率达到100MHz。
在ADPLL芯片设计中,电路采用了带有使能控制的环形数控振荡器结构。环形结构分为粗调和精调两部分,具有锁定范围宽、锁定精度高、功耗低的特点,且捕获范围可以根据需要进一步拓宽。与传统锁相环设计不同,本设计基于CMOS标准单元,所有子模块均采用可综合的Verilog HDL代码描述,利于不同工艺间的移植,设计周期和复杂度大大降低。最终,所设计的ADPLL带宽可达72.95MHz-353.66MHz,频率增益为2.47ps,锁定时间小于35个参考时钟周期。输出300MHz时钟时,峰峰值抖动168ps,RMS抖动38.42ps。1.8V电源电压下,DCO功耗范围为0.7mw-1.52mw。最终完成的全数字锁相环版图面积为274μm×274μm,等效门两输入与非门数为4006。
Based on the general requirements of the readers , two ASIC designs of frequency synthesizer were implemented with SMIC 0.18μm CMOS technology library in this paper. One is a direct digital synthesizer based on ROM structure ; the other is an all-digital phase-locked loop.
In the DDS chip designing ,based on the analysis of specific application requirements of DDS, the paper defined the main performance parameters and system structure, and designed the sub-module circuits . The accumulator module combined the carry line and pipelined architecture together to improve the frequency and reduce the resource utilization; the compression algorithm in ROM module is based on the 1/4 symmetry of sine function and Hutchison algorithm, which made the compression ratio as high as 49 times . What’s more , the power consumption and die area had been greatly reduced . The back-end physical design and simulation had been finished in SMIC’s 0.18μm CMOS process. The finished area of the DDS layout is 260×260μm~2, and the equivalent gate count is 1021. The average power consumption is 7.79mw. The frequency resolution is 0.058Hz ; when the output frequency is 14.65MHz, the stray is more than 70dB. The highest operation frequency of DDS is up to 100MHz .
In the ADPLL chip designing, the ADPLL had a ring digital-controlled oscillator composed by enabled units, with the ring structure divided into two parts in terms of the coarse tuning part and the fine tuning part. It included the characteristic of wide locking range, high locking resolution, and low power consumption. What’s more, the locking range can be further expended according to the demand. Different from the traditional design, this design was based on CMOS standard cells and used synthesizable Verilog HDL for sub-modules description, so it could be easily implanted to different processes, and both the design time and complexity could be reduced. This ADPLL can operate from 72.95MHz to 353.66 MHz, the resolution is 2.47 ps , the locking time is smaller than 35 cycles. When the output frequency is 300MHz ,the peak-to-peak jitter is 168ps and RMS jitter is 38.42ps. With a 1.8V power supply, the proposed DCO has a power consumption range from 0.7mw to 1.52mw. The finished area of the ADPLL layout is 274μm×274μm, and the equivalent gate count is 4006.
引文
[1]张明友,数字阵列雷达和软件化雷达[M] .北京:电子工业出版社,2008 . 149-201
[2]李宁,300MHz高性能DDS数字逻辑的ASIC设计:[硕士学位论文],长沙;国防科学技术大学,2007
[3] J.Tierney,C.Rader,B.Gold. A Digital Frequency Synthesizer.IEEE .Transactions on Audio and Electroacoustics, 1971.3 AU-19(1): 48-57
[4]段传华,王建和,杜进军.直接数字式频率合成器的原理及应用[J].电讯学术,1995.10:1-4.
[5]郭金淮,汤汉屏.DDS技术浅析[J].数据通信,2002(3):50~52
[6]邓胜吉,T-DAB发射机设计:[硕士学位论文],成都:电子科技大学,2010
[7] Saban R, Efendovich A. A full-digital 2-MB/s CMOS data separator [A]. IEEE Int Symp Circ and Syst [C]. 1994. 53-56.
[8]谈熙,杨莲兴.全数字锁相环系统的分析及优化[J] .复旦大学学报, 2006, 45 ( 4) : 443- 447.
[9] R B Staszewski, D Leipold, K Muhammad, and P T Balsara, Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS process, IEEE Trans. Circuits Syst. II, Analog Digit Signal Process, 2003 (50): 815–828.
[10] J Dunning, G. Garcia, J. Lundberg, and E. Nuckolls, An all-digital phase-locked loop with 50-cycle lock time suitable for high-performance microprocessors, IEEE J. Solid-State Circuits, 1995(30): 412–422.
[11] M. Maymandi-Nejad and M. Sachdev, "A Monotonic Digitally Controlled Delay Element," IEEE J. Solid-State Circuits, vol. 40, no.I 1, pp. 2212-2219, Nov. 2005.
[12]赵树杰,雷达信号处理技术[M] .北京:清华大学出版社,2010 . 119-122
[13]侯涛,基于多芯片组件(MCM)技术的雷达前端研究,[硕士学位论文],西安:西安电子科技大学,2009
[14]戈稳,雷达接收机技术[M] .北京:电子工业出版社,2006 . 161-187
[15]金荣洪,耿军平,范瑜,无线通信中的智能天线[M] .北京:北京邮电大学出版社,
[16] M. Chia, P. Chee, W. Loke, et al,“Electronic beam-steering IC for multimode and multiband RFID,”IEEE Trans. Microw. Theory and Tech., vol. 57, no. 5, pp. 1310-1319, May 2009.
[17]何庆强,测控通信系统中的天线新技术[J],微波学报,2010(05):87~91
[18]王子青,应用于SoC的全数字锁相环设计:[硕士学位论文],天津;天津大学,2010
[19]杨丰林,UHF RFID中Delta-Sigma Fractional-N频率综合器的研究:[硕士学位论文],上海:复旦大学
[20]张萍,基于Verilog语言的DDS设计与仿真:[硕士学位论文],西安;西安电子科技大学,2007
[21]刘静,一种低复杂度DDFS的设计与ASIC实现,微电子学学报,2009,39(5):619~622
[22]陈亮,基于ASIC的直接数字频率合成器前端设计与实现:[硕士学位论文],武汉:武汉科技大学,2008
[23]雷能芳.DDS的Veilog设计及QuartursII与Matlab联合仿真[J ] .现代电子技术,2009(12),163~168
[24] Wan Shuqin; Huang Yiding ; Zang Kaihong ;Yu Zongguang ; A 200MHz low-power direct digital frequency synthesizer based on mixed structure of angle rotation, ASICON '09. IEEE 8th International Conference onASIC, 2009. p. 1177
[25] T. Finateu, I. Miro-Panades, F. Boissieres, J.B. Begueret, Y. Deval,D. Belot, F. Badets,“A 500-MHzΣΔPhase-Interpolation Direct Digital Synthesizer”, IEEE ASSCC '07, November 2007,pp. 452-455
[26] Owen Casha ,Ivan Grech , Franck Badets , CMOS Phase-Interpolation DDS for an UWB MB-OFDM Alliance Application. Research in Microelectronics and Electronics, 2009. 12-17 July 2009, p200
[27]刘晨,王森章.直接数字频率合成器的设计及FPGA实现[J ].微电子学与计算机,2004,21(5),63~65
[28] J,Tierney,C.M.Raderand B.Gold,“A digital frequency synthesizer,’’IEEE Transactions on Audio and Electroacoustics,vol.AU-19,197l,PP.121.149.
[29] HUTCHISON B H . Frequency synthesis and applications [M ] . New York : IEEE Press , 1975.
[30] T. Olsson and P. Nilsson,“Portable digital clock generator for digital signal processing applications,”Electron. Lett., vol. 39, pp. 1372–1374, Sep. 2003.
[31] T. Olsson and P. Nilsson,“A digitally controlled PLL for SoC applications,”IEEE J. Solid-State Circuits, vol. 39, no. 5, pp. 751–760, May 2004.
[32] E. Roth, M. Thalmann, N. Felber, and W. Fichtner,“A delay-line based DCO for multimedia applications using digital standard cells only,”in Dig. Tech. Papers ISSCC’03, Feb. 2003, pp. 432–433.
[33] T.-Y. Hsu, C.-C.Wang, and C.-Y. Lee,“Design and analysis of a portable high-speed clock generator,”IEEE Trans. Circuits Syst. II, vol. 48, pp. 367–375, Apr. 2001.
[34]林旭,余锋.一种用于高速同步数据采集设备的数字锁相环[J].微电子学,2003(8) V0l.33.No 4:348-351. Lin Xu, Yu Feng. An All-Digital Phase Locked Loop for High-Speed Synchronous Data Acquisition[ J] . Microelectronics, 2003 V0l.33 No 4 348-351. ( in Chinese)
[35]陈春章,艾霞,王国维,数字集成电路物理设计,北京:科学出版社,2008.
[36] Synopsys Astro 1 Workshop Student Guide[20-I-022-SSG-007] Version 2003.09.
[2]李宁,300MHz高性能DDS数字逻辑的ASIC设计:[硕士学位论文],长沙;国防科学技术大学,2007
[3] J.Tierney,C.Rader,B.Gold. A Digital Frequency Synthesizer.IEEE .Transactions on Audio and Electroacoustics, 1971.3 AU-19(1): 48-57
[4]段传华,王建和,杜进军.直接数字式频率合成器的原理及应用[J].电讯学术,1995.10:1-4.
[5]郭金淮,汤汉屏.DDS技术浅析[J].数据通信,2002(3):50~52
[6]邓胜吉,T-DAB发射机设计:[硕士学位论文],成都:电子科技大学,2010
[7] Saban R, Efendovich A. A full-digital 2-MB/s CMOS data separator [A]. IEEE Int Symp Circ and Syst [C]. 1994. 53-56.
[8]谈熙,杨莲兴.全数字锁相环系统的分析及优化[J] .复旦大学学报, 2006, 45 ( 4) : 443- 447.
[9] R B Staszewski, D Leipold, K Muhammad, and P T Balsara, Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS process, IEEE Trans. Circuits Syst. II, Analog Digit Signal Process, 2003 (50): 815–828.
[10] J Dunning, G. Garcia, J. Lundberg, and E. Nuckolls, An all-digital phase-locked loop with 50-cycle lock time suitable for high-performance microprocessors, IEEE J. Solid-State Circuits, 1995(30): 412–422.
[11] M. Maymandi-Nejad and M. Sachdev, "A Monotonic Digitally Controlled Delay Element," IEEE J. Solid-State Circuits, vol. 40, no.I 1, pp. 2212-2219, Nov. 2005.
[12]赵树杰,雷达信号处理技术[M] .北京:清华大学出版社,2010 . 119-122
[13]侯涛,基于多芯片组件(MCM)技术的雷达前端研究,[硕士学位论文],西安:西安电子科技大学,2009
[14]戈稳,雷达接收机技术[M] .北京:电子工业出版社,2006 . 161-187
[15]金荣洪,耿军平,范瑜,无线通信中的智能天线[M] .北京:北京邮电大学出版社,
[16] M. Chia, P. Chee, W. Loke, et al,“Electronic beam-steering IC for multimode and multiband RFID,”IEEE Trans. Microw. Theory and Tech., vol. 57, no. 5, pp. 1310-1319, May 2009.
[17]何庆强,测控通信系统中的天线新技术[J],微波学报,2010(05):87~91
[18]王子青,应用于SoC的全数字锁相环设计:[硕士学位论文],天津;天津大学,2010
[19]杨丰林,UHF RFID中Delta-Sigma Fractional-N频率综合器的研究:[硕士学位论文],上海:复旦大学
[20]张萍,基于Verilog语言的DDS设计与仿真:[硕士学位论文],西安;西安电子科技大学,2007
[21]刘静,一种低复杂度DDFS的设计与ASIC实现,微电子学学报,2009,39(5):619~622
[22]陈亮,基于ASIC的直接数字频率合成器前端设计与实现:[硕士学位论文],武汉:武汉科技大学,2008
[23]雷能芳.DDS的Veilog设计及QuartursII与Matlab联合仿真[J ] .现代电子技术,2009(12),163~168
[24] Wan Shuqin; Huang Yiding ; Zang Kaihong ;Yu Zongguang ; A 200MHz low-power direct digital frequency synthesizer based on mixed structure of angle rotation, ASICON '09. IEEE 8th International Conference onASIC, 2009. p. 1177
[25] T. Finateu, I. Miro-Panades, F. Boissieres, J.B. Begueret, Y. Deval,D. Belot, F. Badets,“A 500-MHzΣΔPhase-Interpolation Direct Digital Synthesizer”, IEEE ASSCC '07, November 2007,pp. 452-455
[26] Owen Casha ,Ivan Grech , Franck Badets , CMOS Phase-Interpolation DDS for an UWB MB-OFDM Alliance Application. Research in Microelectronics and Electronics, 2009. 12-17 July 2009, p200
[27]刘晨,王森章.直接数字频率合成器的设计及FPGA实现[J ].微电子学与计算机,2004,21(5),63~65
[28] J,Tierney,C.M.Raderand B.Gold,“A digital frequency synthesizer,’’IEEE Transactions on Audio and Electroacoustics,vol.AU-19,197l,PP.121.149.
[29] HUTCHISON B H . Frequency synthesis and applications [M ] . New York : IEEE Press , 1975.
[30] T. Olsson and P. Nilsson,“Portable digital clock generator for digital signal processing applications,”Electron. Lett., vol. 39, pp. 1372–1374, Sep. 2003.
[31] T. Olsson and P. Nilsson,“A digitally controlled PLL for SoC applications,”IEEE J. Solid-State Circuits, vol. 39, no. 5, pp. 751–760, May 2004.
[32] E. Roth, M. Thalmann, N. Felber, and W. Fichtner,“A delay-line based DCO for multimedia applications using digital standard cells only,”in Dig. Tech. Papers ISSCC’03, Feb. 2003, pp. 432–433.
[33] T.-Y. Hsu, C.-C.Wang, and C.-Y. Lee,“Design and analysis of a portable high-speed clock generator,”IEEE Trans. Circuits Syst. II, vol. 48, pp. 367–375, Apr. 2001.
[34]林旭,余锋.一种用于高速同步数据采集设备的数字锁相环[J].微电子学,2003(8) V0l.33.No 4:348-351. Lin Xu, Yu Feng. An All-Digital Phase Locked Loop for High-Speed Synchronous Data Acquisition[ J] . Microelectronics, 2003 V0l.33 No 4 348-351. ( in Chinese)
[35]陈春章,艾霞,王国维,数字集成电路物理设计,北京:科学出版社,2008.
[36] Synopsys Astro 1 Workshop Student Guide[20-I-022-SSG-007] Version 2003.09.