板级光互连协议研究与FPGA实现
摘要
随着集成电路频率的提高和多核时代的到来,传统的高速电互连技术面临着越来越严重的瓶颈问题,而高速下的光互连具有电互连无法比拟的优势,成为未来电互连的理想替代者,也成为科学研究的热点问题。目前,由OIF(Optical Internetworking Forum,光网络论坛)论坛提出的甚短距离光互连协议,主要面向主干网,其延迟、功耗、兼容性等都不能满足板间、芯片间光互连的需要,因此,研究定制一种适用于板级、芯片级的光互连协议具有非常重要的研究意义。
本论文将协议功能分为数据链路层和物理层来设计,链路层功能包括了协议原语设计,数据帧格式和数据传输流程设计,流量控制机制设计,协议通道初始化设计,错误检测机制设计和空闲字符产生、时钟补偿方式设计;物理层功能包含了数据的串化和解串功能,多通道情况下的绑定功能,数据编解码功能等。
然后,文章采用FPGA(Field Programmable Gate Array,现场可编程门阵列)技术实现了定制协议的单通道模式。重点是数据链路层的实现,物理层采用定制具备其功能的IP(Intellectual Property,知识产权)——RocketIO来实现。实现的过程中,采用了Xilinx公司的ISE(Integrated System Environment,集成开发环境)开发流程,使用的设计工具包括:ISE,ModelSim,Synplify Pro,ChipScope等。
最后,本文对实现的协议进行了软件仿真和上板测试,访真和测试结果表明,实现的单通道模式,支持的最高串行频率达到3.5GHz,完全满足了光互连验证系统初期的要求,同时由RocketIO的高速串行差分口得到的眼图质量良好,表明对物理层IP的定制是成功的。
With the frequency of integrated circuits improving and multi-core’s coming,the bottleneck of the traditional high speed electronic interconnect technology is more and more serious.Comparing it,optical interconnector have more merits in high speed area,it is an ideal replacer for electronic interconnector in future.also,it is a hot area in scientific reseach.At present,the Very Short Reach(VSR) protocol suggested by OIF,mainly faced to backbone,its delay,power,compatibility etc.is not suitable for board-to-board,chip-to-chip optical interconnector.So reseaching a appropriate protocol for this is significance.
In this paper,the function of the protocol was divided into data link layer and physical layer,the former layer contains protocol primitive sets design,the format of data frame design and data transmit flow design,flow control design,the initial mechanism for the protocol channel design,error detect design,idle character generation design and the manner of clock compensation design;the latter include data serialize and deserializ function,lanes bind function,data coding and decoding etc.
Then, FPGA (Field Programmable Gate Array) technology was used to implemented the single channel of the protocol,this paper focus on data link layer,and the physical layer introduces an custom-built IP——RocketIO to replace.when implemented,the Xilinx corporation’s ISE development flow was adopted,the design tools included ISE, ModelSim,Synplify Pro,ChipScope etc.
At last,through software simulation and on board testing,the results indicate that the max serial frequency reached 3.5GHz when the protocol in single channel,it satisfies the optical interconnected validate system.at the same time,the eye diagram,obtained from the RocketIO’s high speed serial difference ports,is righ,this indicate that the customization of physical IP was success.
本论文将协议功能分为数据链路层和物理层来设计,链路层功能包括了协议原语设计,数据帧格式和数据传输流程设计,流量控制机制设计,协议通道初始化设计,错误检测机制设计和空闲字符产生、时钟补偿方式设计;物理层功能包含了数据的串化和解串功能,多通道情况下的绑定功能,数据编解码功能等。
然后,文章采用FPGA(Field Programmable Gate Array,现场可编程门阵列)技术实现了定制协议的单通道模式。重点是数据链路层的实现,物理层采用定制具备其功能的IP(Intellectual Property,知识产权)——RocketIO来实现。实现的过程中,采用了Xilinx公司的ISE(Integrated System Environment,集成开发环境)开发流程,使用的设计工具包括:ISE,ModelSim,Synplify Pro,ChipScope等。
最后,本文对实现的协议进行了软件仿真和上板测试,访真和测试结果表明,实现的单通道模式,支持的最高串行频率达到3.5GHz,完全满足了光互连验证系统初期的要求,同时由RocketIO的高速串行差分口得到的眼图质量良好,表明对物理层IP的定制是成功的。
With the frequency of integrated circuits improving and multi-core’s coming,the bottleneck of the traditional high speed electronic interconnect technology is more and more serious.Comparing it,optical interconnector have more merits in high speed area,it is an ideal replacer for electronic interconnector in future.also,it is a hot area in scientific reseach.At present,the Very Short Reach(VSR) protocol suggested by OIF,mainly faced to backbone,its delay,power,compatibility etc.is not suitable for board-to-board,chip-to-chip optical interconnector.So reseaching a appropriate protocol for this is significance.
In this paper,the function of the protocol was divided into data link layer and physical layer,the former layer contains protocol primitive sets design,the format of data frame design and data transmit flow design,flow control design,the initial mechanism for the protocol channel design,error detect design,idle character generation design and the manner of clock compensation design;the latter include data serialize and deserializ function,lanes bind function,data coding and decoding etc.
Then, FPGA (Field Programmable Gate Array) technology was used to implemented the single channel of the protocol,this paper focus on data link layer,and the physical layer introduces an custom-built IP——RocketIO to replace.when implemented,the Xilinx corporation’s ISE development flow was adopted,the design tools included ISE, ModelSim,Synplify Pro,ChipScope etc.
At last,through software simulation and on board testing,the results indicate that the max serial frequency reached 3.5GHz when the protocol in single channel,it satisfies the optical interconnected validate system.at the same time,the eye diagram,obtained from the RocketIO’s high speed serial difference ports,is righ,this indicate that the customization of physical IP was success.
引文
[1] PCI Local Bus Specification Revision 2.2, PCI Specification Interesting Group,http://www.pcisig.com/specifications/conventional/conventional_pci,1994
[2] PCI-Express Base Specification 1.0a, PCI Specification Interesting Group, http://www.pcisig.com/specifications/pciexpress/components letters, 2003
[3] Nga.NguyenThiHang,Lee.MinHyuk,Lee.Tae-Woo,Park.Hyo-Hoon.10Gb/s SerDes for Bidirectional Chip-to-Memory Optical Interconnection.Lasers and Electro-Optics-Pacific Rim,2007.CLEO/Pacific Rim 2007.Conference on.26-31Aug. 2007 Page(s):1-2
[4] 刘喜斌,罗文华.电流趋肤效应的研究.岳阳师范学院学报(自然科学版),2003,15(1):31-33
[5] Schneider M.V. Dielectric loss in hybrid integrated.circuits.Proceedings of the IEEE,Volume 57, Issue 6, June 1969 Page(s):1206 -1207.
[6] Pawan Kapur, Krishna C Saraswat, Comparisons between electrical and opticalinterconnects for on-chip signaling, Proceedings of the IEEE 2002 International Interconnect Technology Conference, 2002,Page(s): 89-91
[7] Mauro J.Kobrinsky,Bruce A.Block,Jun-Fei Zheng,Brandon C.Barantt,Scott List, etc. On-Chip Optical Interconnects.Intel International Journal, May. 2004,8(2), Page(s):129-141
[8] Neil Savage.Linking with light.Spectrum IEEE,2002,39(8):32-36
[9] A.F.J.Levi,Optical Interconnects in Systems,Proceedings,IEEE 88,2002,No.6, Page(s):750-757
[10] R.A.Nordim,A.F.J.Levi,R.N.Nottenburg,J.O’Gorman,T.Tanbun-Ek and R.A. Logan,A System Perspective on Digital Interconnection Technology, Lightwave Technology,1992,10(6),Page(s):811-827
[11] OIF Physical and Link Layer Working Group,Very Short Reach(VSR) OC-192/STM-64 Interface Based on Parallel Optics,Implementation Agreement: OIF-VSR4-01.0, http://www.oiforum.com/ public/impagreement- sum.html, 2000
[12] OIF Physical and Link Layer Working Group,Serial OC-192 1310nm Very Short Reach(VSR) Interfaces:Implementation Agreement OIF-VSR4-02.0, http://www.oiforum.com/ public/impagreementsum.html,2000
[13] OIF Physical and Link Layer Working Group,Very Short Reach(VSR)OC-192 Four Fiber Interface Based on Parallel Optics,Implementation Agreement: OIF-VSR4-03.0, http://www.oiforum.com/public/impagreementsum.html,2000
[14] OIF Physical and Link Layer Working Group, Serial Shortwave Very Short Reach (VSR) OC-192 Interface for Multimode Fiber,Implementation Agreement: OIF-VSR4-04.0, http://www.oiforum.com/ public/impagree- mentsum.html,2001
[15] OIF Physical and Link Layer Working Group, Very Short Reach(VSR) OC-192 Using 1310nm Wavelength and 4dB and 11dB Link Budgets, Implementation Agreement:OIF-VSR4-05.0, http://www.oiforum.com/ public /impagreementsum.html,2002
[16] OIF Physical and Link Layer Working Group, Very Short Reach Interface Level 5 (VSR-5): SONET/SDH OC-768 interface for Very Short Reach (VSR) applications, Implementation Agreement:OIF-VSR5-01.0, http://www.oiforu- m.com/public/impagreementsum.html,2002
[17] 邓晖,陈弘达,梁琨,杜云,唐君等.InGaAsv/GaAs 多量子阱 SEED 设计和特性研究,光电子.激光,2001,12(3):222-224
[18] Koyama.Fumio, Miyamoto.Tomoyuki,Recent Advances of VCSEL Technology,Indium Phosphide & Related Materials, 2007. IPRM '07. IEEE 19th International Conference on 14-18 May 2007 Page(s):420-425
[19] Srdan Glisic and Wolfgang Winkler. A Broadband Low Spur Fully Integrated BiCMOS PLL for 60GHz Wireless Applications.IEEE International Solid -state Circuits Conference, 2006, 39(9): 451-454
[20] 张劲松,曹明翠,陈涛,谭伟.VCSEL 技术与并行光互联.光通信研究,2002,第 6 期:54-58
[21] Cauvet.P,Bernard.S,Renovell.M,System-in-Package,a Combination of Challenges and Solutions European Test Symposium, 2007. ETS '07. 12th IEEE 20-24 May 2007 Page(s):193-199
[22] Abhijit Athavale,Carl Christensen.High-Speed Serial I/O Made Simple. Xilinx, 2005,57-65
[23] 邹道生,李铭.锁相环在频率合成技术中的应用研究.赣南师范学院学报,2002.11,(6):39-40
[24] K.Vichienchom,M.Clements and W.Liu, A Multi-gigabit CMOS Data Recovery Circuit using an Analog Parallel Sampling Technique, Proc. ISCAS 2001, June 2001
[25] WIDMER A X,FMMMEK P A.A DC-balance,partitionedblock,8B/10B tranmfission code.IBM Journal of research and development, 1983,23(5):441
[26] 张健,吴晓冰.LVDS技术原理和设计简介.电子技术应用.2000,(5):69-70
[27] Xilinx,Aurora Protocol Specification SP002(V1.2). http://www.xilinx.com/, 2003-04.
[28] 任晓东,郑侃.CPLD/FPGA高级应用开发指南.北京:人民邮电出版社,2003.11
[29] 夏宇闻,Verilog数字系统设计教程.第1版,北京:北京航空航天大学出版社,2003,4-8
[30] Xilinx.Virtex-II ProTM Platform FPGA User Guid. http://www.xilinx.com/, 2003-06
[31] Xilinx.RocketIOTM Transceiver User Guide.v2.1. http://www.xilinx.com/, 2003-06
[32] Xilinx.Single-Port Block Memory v6.1.http://www.xilinx.com/,2004-05
[33] Xilinx.Using Digital Clock Managers(DCMs).XAPP462. http://www.xilinx. com/, 2006-05
[34] 徐峰,冯正勇.基于RocketIO的SAR雷达系统高速串行传输的实现.遥感技术与应用,2006,21(2):125-129
[35] Xilinx .Chipscope pro software and cores user guide UG029(V7.1),2005,02
[36] Albertengo,G,Sisto, R.Parallel CRC Generation.IEEE Micro,Volume 10,Issue 5, Oct.1990 Page(s):63-71
[37] 赵文虎,王志功,费瑞霞等.基于逻辑设计的光纤通信8B/10B编解码方法研究.电路与系统,2003,8(2):48-53
[38] Xilinx.Efficient Shift Registers,LFSR Counters,and Long Pseudo-Random Sequence Generators v1.1,1996.July
[39] Lionel Bening and Harry Foster.Principles of Verifiable RTL Design.Second Edition.NewYork:Kluwer Academic Publishers,2001,9-21
[40] Marshall.J, A PC-Based JTAG Test Environment,Electro International, 1991,April 16-18, 1991 Page(s):540-545
[41] 吴继华,王诚.Altera FPGA/CPLD设计(高级篇).北京:人民邮电出版社, 2005, 315-318
[42] 樊昌信,张甫翊,徐炳祥等.通信原理.第5版,北京:国防工业出版社,2001.5,9-11
[2] PCI-Express Base Specification 1.0a, PCI Specification Interesting Group, http://www.pcisig.com/specifications/pciexpress/components letters, 2003
[3] Nga.NguyenThiHang,Lee.MinHyuk,Lee.Tae-Woo,Park.Hyo-Hoon.10Gb/s SerDes for Bidirectional Chip-to-Memory Optical Interconnection.Lasers and Electro-Optics-Pacific Rim,2007.CLEO/Pacific Rim 2007.Conference on.26-31Aug. 2007 Page(s):1-2
[4] 刘喜斌,罗文华.电流趋肤效应的研究.岳阳师范学院学报(自然科学版),2003,15(1):31-33
[5] Schneider M.V. Dielectric loss in hybrid integrated.circuits.Proceedings of the IEEE,Volume 57, Issue 6, June 1969 Page(s):1206 -1207.
[6] Pawan Kapur, Krishna C Saraswat, Comparisons between electrical and opticalinterconnects for on-chip signaling, Proceedings of the IEEE 2002 International Interconnect Technology Conference, 2002,Page(s): 89-91
[7] Mauro J.Kobrinsky,Bruce A.Block,Jun-Fei Zheng,Brandon C.Barantt,Scott List, etc. On-Chip Optical Interconnects.Intel International Journal, May. 2004,8(2), Page(s):129-141
[8] Neil Savage.Linking with light.Spectrum IEEE,2002,39(8):32-36
[9] A.F.J.Levi,Optical Interconnects in Systems,Proceedings,IEEE 88,2002,No.6, Page(s):750-757
[10] R.A.Nordim,A.F.J.Levi,R.N.Nottenburg,J.O’Gorman,T.Tanbun-Ek and R.A. Logan,A System Perspective on Digital Interconnection Technology, Lightwave Technology,1992,10(6),Page(s):811-827
[11] OIF Physical and Link Layer Working Group,Very Short Reach(VSR) OC-192/STM-64 Interface Based on Parallel Optics,Implementation Agreement: OIF-VSR4-01.0, http://www.oiforum.com/ public/impagreement- sum.html, 2000
[12] OIF Physical and Link Layer Working Group,Serial OC-192 1310nm Very Short Reach(VSR) Interfaces:Implementation Agreement OIF-VSR4-02.0, http://www.oiforum.com/ public/impagreementsum.html,2000
[13] OIF Physical and Link Layer Working Group,Very Short Reach(VSR)OC-192 Four Fiber Interface Based on Parallel Optics,Implementation Agreement: OIF-VSR4-03.0, http://www.oiforum.com/public/impagreementsum.html,2000
[14] OIF Physical and Link Layer Working Group, Serial Shortwave Very Short Reach (VSR) OC-192 Interface for Multimode Fiber,Implementation Agreement: OIF-VSR4-04.0, http://www.oiforum.com/ public/impagree- mentsum.html,2001
[15] OIF Physical and Link Layer Working Group, Very Short Reach(VSR) OC-192 Using 1310nm Wavelength and 4dB and 11dB Link Budgets, Implementation Agreement:OIF-VSR4-05.0, http://www.oiforum.com/ public /impagreementsum.html,2002
[16] OIF Physical and Link Layer Working Group, Very Short Reach Interface Level 5 (VSR-5): SONET/SDH OC-768 interface for Very Short Reach (VSR) applications, Implementation Agreement:OIF-VSR5-01.0, http://www.oiforu- m.com/public/impagreementsum.html,2002
[17] 邓晖,陈弘达,梁琨,杜云,唐君等.InGaAsv/GaAs 多量子阱 SEED 设计和特性研究,光电子.激光,2001,12(3):222-224
[18] Koyama.Fumio, Miyamoto.Tomoyuki,Recent Advances of VCSEL Technology,Indium Phosphide & Related Materials, 2007. IPRM '07. IEEE 19th International Conference on 14-18 May 2007 Page(s):420-425
[19] Srdan Glisic and Wolfgang Winkler. A Broadband Low Spur Fully Integrated BiCMOS PLL for 60GHz Wireless Applications.IEEE International Solid -state Circuits Conference, 2006, 39(9): 451-454
[20] 张劲松,曹明翠,陈涛,谭伟.VCSEL 技术与并行光互联.光通信研究,2002,第 6 期:54-58
[21] Cauvet.P,Bernard.S,Renovell.M,System-in-Package,a Combination of Challenges and Solutions European Test Symposium, 2007. ETS '07. 12th IEEE 20-24 May 2007 Page(s):193-199
[22] Abhijit Athavale,Carl Christensen.High-Speed Serial I/O Made Simple. Xilinx, 2005,57-65
[23] 邹道生,李铭.锁相环在频率合成技术中的应用研究.赣南师范学院学报,2002.11,(6):39-40
[24] K.Vichienchom,M.Clements and W.Liu, A Multi-gigabit CMOS Data Recovery Circuit using an Analog Parallel Sampling Technique, Proc. ISCAS 2001, June 2001
[25] WIDMER A X,FMMMEK P A.A DC-balance,partitionedblock,8B/10B tranmfission code.IBM Journal of research and development, 1983,23(5):441
[26] 张健,吴晓冰.LVDS技术原理和设计简介.电子技术应用.2000,(5):69-70
[27] Xilinx,Aurora Protocol Specification SP002(V1.2). http://www.xilinx.com/, 2003-04.
[28] 任晓东,郑侃.CPLD/FPGA高级应用开发指南.北京:人民邮电出版社,2003.11
[29] 夏宇闻,Verilog数字系统设计教程.第1版,北京:北京航空航天大学出版社,2003,4-8
[30] Xilinx.Virtex-II ProTM Platform FPGA User Guid. http://www.xilinx.com/, 2003-06
[31] Xilinx.RocketIOTM Transceiver User Guide.v2.1. http://www.xilinx.com/, 2003-06
[32] Xilinx.Single-Port Block Memory v6.1.http://www.xilinx.com/,2004-05
[33] Xilinx.Using Digital Clock Managers(DCMs).XAPP462. http://www.xilinx. com/, 2006-05
[34] 徐峰,冯正勇.基于RocketIO的SAR雷达系统高速串行传输的实现.遥感技术与应用,2006,21(2):125-129
[35] Xilinx .Chipscope pro software and cores user guide UG029(V7.1),2005,02
[36] Albertengo,G,Sisto, R.Parallel CRC Generation.IEEE Micro,Volume 10,Issue 5, Oct.1990 Page(s):63-71
[37] 赵文虎,王志功,费瑞霞等.基于逻辑设计的光纤通信8B/10B编解码方法研究.电路与系统,2003,8(2):48-53
[38] Xilinx.Efficient Shift Registers,LFSR Counters,and Long Pseudo-Random Sequence Generators v1.1,1996.July
[39] Lionel Bening and Harry Foster.Principles of Verifiable RTL Design.Second Edition.NewYork:Kluwer Academic Publishers,2001,9-21
[40] Marshall.J, A PC-Based JTAG Test Environment,Electro International, 1991,April 16-18, 1991 Page(s):540-545
[41] 吴继华,王诚.Altera FPGA/CPLD设计(高级篇).北京:人民邮电出版社, 2005, 315-318
[42] 樊昌信,张甫翊,徐炳祥等.通信原理.第5版,北京:国防工业出版社,2001.5,9-11