基于FPGA的片上多处理器建模方法
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摘要
片上多处理器的发展给计算机系统结构研究带来新的发展空间和挑战。一方面片上多处理器的发展使微处理器性能的提升由挖掘指令级并行性转变为开发线程级和数据级并行性。为了开发片上多处理器的这种并行性,我们必须抛弃传统单核处理器系统的架构,重新设计处理器系统的软硬件结构,包括硬件微结构、编程模型、编译器、运行时系统等等。而另一方面,传统上用于单核处理器结构研究的软件模拟器已经明显不能满足片上多处理器系统下这种软硬件研究的需要。处理器核数的膨胀使软件模拟器的性能成比例降低,无法进行周期精确的硬件结构模拟,更无法进行全系统模拟和系统软件的研究。由于以上原因,多核处理器体系结构的研究缺乏大量的实验评测和全面、有效的指导,而软件模拟器成为了多核时代处理器体系结构研究的瓶颈。因此,新的处理器模拟工具是有效开展片上多处理器结构研究的关键。FPGA天生的并行性使它在模拟片上多处理器时具有较高的模拟性能和高度的可扩放性,成为研究多核处理器体系结构理想的模拟平台。
本文研究了基于FPGA的片上多处理器建模方法。主要研究内容和成果包括：(1)研究了处理器的功能模型、性能模型以及原型,提出了一种功能与时序分离的处理器性能模型架构。其中功能部分只完成处理器的动作,不考虑硬件结构和动作的时序。时序部分则模拟处理器微结构,控制处理器动作发生的时序,并驱动功能部分模拟处理器的动作。由于功能部分与处理器的微结构无关,所以相同的功能部分可以重用于各种时序部分,并且可以兼容各种模拟方式,包括使用软件的模拟或者跨平台的模拟。这种架构使已有工作有效的被重用,减少了建模工作量。(2)研究了模拟器模块间的同步方式,针对FPGA模拟的特点提出基于管道的性能模拟技术。这种技术允许不同的处理器模块在同一时刻模拟不同的目标时钟周期,使运行速度较快的模块不必等待运行速度较慢的模块,显著提升了系统的模拟性能。模拟器各个模块之间的性能差距越大,管道模拟能发挥的作用也越大。(3)提出了使用软硬件协同模拟调节FPGA资源使用量和简化建模的方法。片上多处理器的模拟需要大量的FPGA资源,我们使用软件实现的存储缓存机制可以将数据缓存到宿主机器上,有效调节FPGA资源。基于FPGA的模拟不适合实现某些复杂的结构,可以使用软件实现这些结构的功能,简化FPGA建模过程。同时,FPGA模拟调试复杂且编译时间过长,我们通过使用软件实现模块并进行调试,有效减小建模难度,缩短编译时间。(4)研究了多核模拟的分时复用方法,提出了细粒度的分时复用技术。该技术将每个模块分为逻辑与状态两部分,将状态根据模拟核数复制多份,并将逻辑部分重用。细粒度的分时复用技术以模拟器各个模块内的规则为复用单位,使在任意时刻一个模块内可以同时进行多个处理器核的模拟,提高了系统资源的利用率。(5)分析了基于FPGA的模拟器性能瓶颈,提出了若干模拟性能的优化技术。包括在功能部分与时序部分之间统计功能部分延迟的机制,以及在时序部分各模块之间统计延迟的机制。(6)基于以上研究工作实现了RAMP-Pink模拟平台。RAMP-Pink平台是对事务存储和推测多线程提供统一支持的多核处理器模拟平台,采用了Alpha指令集；实现了RAMP-Pink平台上创建多线程的机制,取代PThreads库,该机制也可用于其他无操作系统支持的多核模拟平台；设计并实现了一个基于目录的MESI Cache一致性协议。
在研究基于FPGA的处理器建模和设计实现RAMP-Pink系统的过程中我们得到一些如何进行多核处理器硬件建模的认识。首先,软件模拟片上多处理器的关键问题是软件的串行性无法适应不断膨胀的处理器核数,为此采用具有高度可扩放性的FPGA模拟平台可以应对核数膨胀问题并带来硬件级别的模拟性能。其次,FPGA建模的复杂度和建模周期都远远超过软件建模,采用功能与时序分离的模拟架构和软硬件协同的模拟技术可以有效减少建模工作量,缩短建模周期。最后,实现多核模拟需要较多的FPGA资源,通过细粒度的分时复用以及软硬件协同模拟技术可以调节FPGA资源的使用量。
本文的研究工作和结果可用于指导基于FPGA的多核处理器建模和进一步的优化。
With the development of chip multiprocessor, the research of computer architecture now faces new opportunities and challenges. On one hand, the performance gain of multiprocessor has changed from instruction-level parallelism to thread-level and data-level parallelism. In order to find the parallelism, we must break the frameworks of traditional software and hardware, and redesign them, including microarchitecture, programming model, compiler, runtime system and so on. On the other hand, software simulator, traditional used in single-core processor architecture research, can not meet the research demand of multi-core processor. Software simulator performance reduce proportionally to processor cores, thus can not support cycle accurate simulation, full system simulation and the research of system software. For the reasons given above, research in multi-core processor architecture lack abundant experimental evaluations and comprehensive guides. And software simulator becomes the bottleneck of multi-core architecture research. Thus, the key of doing research in multi-core processor architecture effectively is adopting a new simulator. The inherently parallelism of FPGA gives it better simulation performance and scalability in hardware level, and becomes an ideal simulation platform
This dissertation focuses on the ways of modeling chip multi-processor. The major research contributions include:(1) Based on the study of functional emulator, performance model and prototype, we propose a novel performance model framework where functions and timing are departed. Specifically, the functional partition is just responsible for correct simulation of the processor actions, without considering the microarchitecture and timing sequence. The timing partition models the microarchitecture of the processor, determines the time of processor actions, and drives the functional partition to simulate the corresponding microarchitecture. Due to the microarchitecture independent, one functional partition can be reused to multiple timing partitions, and it is compatible with other simulation patterns, including software simulations and cross platform simulations. This framework reuses off the shelf modules and saves previous modeling work effectively.(2) By studying the synchronization method of modules in simulator, a synchronization technique based on port is proposed. Port synchronization technique enables multiple modules in a model simulate different model cycles at the same time. In this way, modules with high speed do not need to wait for the ones with low speed, and thus promotes the system performance. The larger speed difference between the modules, the better port performances can be observed.(3) With the technique of software-hardware co-modeling, we propose the methods of adjusting FPGA resource occupation and simplifying modeling process. Since simulating chip multi-processor needs vast FPGA resource, we use software memory buffer technique to store data in the host computer, reduce the occupation of FPGA resource. It is very difficult to simulate complex structure in FPGA, so we use software-hardware co-modeling technique to ease this process. RTL code is complex in debugging and time-consuming in compilation, software simulation can be used to reduce the modeling complexity and the compiling time.(4) Time-division multiplexing technique is investigated and a fine grained time-multiplexing technique is proposed. We divide a module into two parts:state and logic, where we duplicate state for multi-core and reuse the logic part. Fine granularity time-multiplexing takes rule as the reuse unit and makes multiple cores simulate in one module at the same time. It also increase FPGA resource utilization rate.(5) The performance bottleneck is analyzed and several optimize techniques are proposed. These techniques include the delay statistic between functional and timing partition, and the delay statistic between modules in timing partition.(6) Based on all the above research, we implement a RAMP-Pink simulation platform. RAMP-Pink supports both transactional memory and thread level speculation. We adopted the alpha ISA, and provide a multi-thread creation mechanism to replace PThreads library. This mechanism can also be used on other multi-core simulation platforms without OS support. During deployment, a MESI Cache coherence protocol is designed and implemented.
Through the research of processor modeling based on FPGA and RAMP-Pink system implementation, we have got some important conclusions about hardware modeling. Firstly, the key problem of software simulator for multi-core processor is that it does not scale well while the number of cores increasing. Thus, FPGA platform with highly scalability could solve the problem of core increasing and gets hardware-level performance. Secondly, FPGA modeling is more complex and the time-consuming is much higher than software modeling. With function-timing partition modeling framework and hardware-software co-modeling technique we can effectively reduce modeling work and modeling period. Thirdly, modeling multi-core processor needs abundant FPGA resources. Fine-grained time-multiplexing and software-hardware co-modeling technique can leverage the occupation of FPGA resources.
The research and experimental results in this dissertation can be provided to guide the simulation of multi-core processor based on FPGA and take further optimization.
本文研究了基于FPGA的片上多处理器建模方法。主要研究内容和成果包括：(1)研究了处理器的功能模型、性能模型以及原型,提出了一种功能与时序分离的处理器性能模型架构。其中功能部分只完成处理器的动作,不考虑硬件结构和动作的时序。时序部分则模拟处理器微结构,控制处理器动作发生的时序,并驱动功能部分模拟处理器的动作。由于功能部分与处理器的微结构无关,所以相同的功能部分可以重用于各种时序部分,并且可以兼容各种模拟方式,包括使用软件的模拟或者跨平台的模拟。这种架构使已有工作有效的被重用,减少了建模工作量。(2)研究了模拟器模块间的同步方式,针对FPGA模拟的特点提出基于管道的性能模拟技术。这种技术允许不同的处理器模块在同一时刻模拟不同的目标时钟周期,使运行速度较快的模块不必等待运行速度较慢的模块,显著提升了系统的模拟性能。模拟器各个模块之间的性能差距越大,管道模拟能发挥的作用也越大。(3)提出了使用软硬件协同模拟调节FPGA资源使用量和简化建模的方法。片上多处理器的模拟需要大量的FPGA资源,我们使用软件实现的存储缓存机制可以将数据缓存到宿主机器上,有效调节FPGA资源。基于FPGA的模拟不适合实现某些复杂的结构,可以使用软件实现这些结构的功能,简化FPGA建模过程。同时,FPGA模拟调试复杂且编译时间过长,我们通过使用软件实现模块并进行调试,有效减小建模难度,缩短编译时间。(4)研究了多核模拟的分时复用方法,提出了细粒度的分时复用技术。该技术将每个模块分为逻辑与状态两部分,将状态根据模拟核数复制多份,并将逻辑部分重用。细粒度的分时复用技术以模拟器各个模块内的规则为复用单位,使在任意时刻一个模块内可以同时进行多个处理器核的模拟,提高了系统资源的利用率。(5)分析了基于FPGA的模拟器性能瓶颈,提出了若干模拟性能的优化技术。包括在功能部分与时序部分之间统计功能部分延迟的机制,以及在时序部分各模块之间统计延迟的机制。(6)基于以上研究工作实现了RAMP-Pink模拟平台。RAMP-Pink平台是对事务存储和推测多线程提供统一支持的多核处理器模拟平台,采用了Alpha指令集；实现了RAMP-Pink平台上创建多线程的机制,取代PThreads库,该机制也可用于其他无操作系统支持的多核模拟平台；设计并实现了一个基于目录的MESI Cache一致性协议。
在研究基于FPGA的处理器建模和设计实现RAMP-Pink系统的过程中我们得到一些如何进行多核处理器硬件建模的认识。首先,软件模拟片上多处理器的关键问题是软件的串行性无法适应不断膨胀的处理器核数,为此采用具有高度可扩放性的FPGA模拟平台可以应对核数膨胀问题并带来硬件级别的模拟性能。其次,FPGA建模的复杂度和建模周期都远远超过软件建模,采用功能与时序分离的模拟架构和软硬件协同的模拟技术可以有效减少建模工作量,缩短建模周期。最后,实现多核模拟需要较多的FPGA资源,通过细粒度的分时复用以及软硬件协同模拟技术可以调节FPGA资源的使用量。
本文的研究工作和结果可用于指导基于FPGA的多核处理器建模和进一步的优化。
With the development of chip multiprocessor, the research of computer architecture now faces new opportunities and challenges. On one hand, the performance gain of multiprocessor has changed from instruction-level parallelism to thread-level and data-level parallelism. In order to find the parallelism, we must break the frameworks of traditional software and hardware, and redesign them, including microarchitecture, programming model, compiler, runtime system and so on. On the other hand, software simulator, traditional used in single-core processor architecture research, can not meet the research demand of multi-core processor. Software simulator performance reduce proportionally to processor cores, thus can not support cycle accurate simulation, full system simulation and the research of system software. For the reasons given above, research in multi-core processor architecture lack abundant experimental evaluations and comprehensive guides. And software simulator becomes the bottleneck of multi-core architecture research. Thus, the key of doing research in multi-core processor architecture effectively is adopting a new simulator. The inherently parallelism of FPGA gives it better simulation performance and scalability in hardware level, and becomes an ideal simulation platform
This dissertation focuses on the ways of modeling chip multi-processor. The major research contributions include:(1) Based on the study of functional emulator, performance model and prototype, we propose a novel performance model framework where functions and timing are departed. Specifically, the functional partition is just responsible for correct simulation of the processor actions, without considering the microarchitecture and timing sequence. The timing partition models the microarchitecture of the processor, determines the time of processor actions, and drives the functional partition to simulate the corresponding microarchitecture. Due to the microarchitecture independent, one functional partition can be reused to multiple timing partitions, and it is compatible with other simulation patterns, including software simulations and cross platform simulations. This framework reuses off the shelf modules and saves previous modeling work effectively.(2) By studying the synchronization method of modules in simulator, a synchronization technique based on port is proposed. Port synchronization technique enables multiple modules in a model simulate different model cycles at the same time. In this way, modules with high speed do not need to wait for the ones with low speed, and thus promotes the system performance. The larger speed difference between the modules, the better port performances can be observed.(3) With the technique of software-hardware co-modeling, we propose the methods of adjusting FPGA resource occupation and simplifying modeling process. Since simulating chip multi-processor needs vast FPGA resource, we use software memory buffer technique to store data in the host computer, reduce the occupation of FPGA resource. It is very difficult to simulate complex structure in FPGA, so we use software-hardware co-modeling technique to ease this process. RTL code is complex in debugging and time-consuming in compilation, software simulation can be used to reduce the modeling complexity and the compiling time.(4) Time-division multiplexing technique is investigated and a fine grained time-multiplexing technique is proposed. We divide a module into two parts:state and logic, where we duplicate state for multi-core and reuse the logic part. Fine granularity time-multiplexing takes rule as the reuse unit and makes multiple cores simulate in one module at the same time. It also increase FPGA resource utilization rate.(5) The performance bottleneck is analyzed and several optimize techniques are proposed. These techniques include the delay statistic between functional and timing partition, and the delay statistic between modules in timing partition.(6) Based on all the above research, we implement a RAMP-Pink simulation platform. RAMP-Pink supports both transactional memory and thread level speculation. We adopted the alpha ISA, and provide a multi-thread creation mechanism to replace PThreads library. This mechanism can also be used on other multi-core simulation platforms without OS support. During deployment, a MESI Cache coherence protocol is designed and implemented.
Through the research of processor modeling based on FPGA and RAMP-Pink system implementation, we have got some important conclusions about hardware modeling. Firstly, the key problem of software simulator for multi-core processor is that it does not scale well while the number of cores increasing. Thus, FPGA platform with highly scalability could solve the problem of core increasing and gets hardware-level performance. Secondly, FPGA modeling is more complex and the time-consuming is much higher than software modeling. With function-timing partition modeling framework and hardware-software co-modeling technique we can effectively reduce modeling work and modeling period. Thirdly, modeling multi-core processor needs abundant FPGA resources. Fine-grained time-multiplexing and software-hardware co-modeling technique can leverage the occupation of FPGA resources.
The research and experimental results in this dissertation can be provided to guide the simulation of multi-core processor based on FPGA and take further optimization.
引文
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