LVDS高速I/0接口芯片FTLVDS的设计与实现
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摘要
随着体系结构技术和半导体工艺的发展，集成电路芯片上的时钟频率提高很快，芯片内外的数据传输速率差异已经成为影响系统性能的一个瓶颈。
低电压差分信号LVDS是一个用于高速信号传输的国际通用接口标准，同时具有高速度、低噪声、低功耗和低成本的突出优点。LVDS高速I／O接口单元是高性能计算机和通讯电子设备中重要的构件，能够在广泛的应用领域里解决高速数据传输的瓶颈问题。本课题所设计的LVDS高速I／O接口芯片FTLVDS，正是对解决这一瓶颈的有益尝试。
FTLVDS芯片采用了“自顶向下”和“由底向上”相结合的正向设计方法。该芯片的功能包括LVDS信号的收发以及CMOS数据的串并转换。芯片可划分为LVDS驱动器、LVDS接收器、串行化器和解串行器四个模块。根据这些模块的功能及特点，分别采用了不同的设计方法来实现。
收发模块LVDS驱动器和接收器是LVDS高速I／O接口芯片的关键电路，采用全定制的方法设计，也是本课题的重点。课题着重对这两个模块的电路结构以及版图结构进行了深入的研究和分析，并采用SPICE工具进行了模拟验证。
串并模块串行化器和解串行器采用标准单元的方法设计，论文讨论了对几种时钟同步模式以及串并转换电路结构的权衡和实现，并对所设计的电路结构进行了Verilog模拟验证。
FTLVDS芯片是收发模块和串并模块的组合，其版图实现采用了全定制单元和标准单元混合的设计方法，并且进行了投片封装。
本课题对LVDS高速I／O接口单元芯片FTLVDS的自主设计研究，作为国防科技重点实验室基金项目“高速数字信号互连与信号传输技术”的一部分，一方面为进行高速数字信号传输的研究提供了不可缺少的实验依据和硬件基础，另一方面也是对IC芯片正向设计中采用全定制和半定制的混合设计方法的一次有益探索。
With the great development of the technology of computer architecture and the technology of semiconductor,the frequency of the timing clock in the 1C chips has been faster and faster. Then the difference of data transmission speed between inside and outside of current CMOS chips has been a bottleneck influencing the performance of computer systems.
LVDS(Low Voltage Differential Signaling) is an international common interface sdandard that applied to high speed signal transmitter. The high speed LVDS I/O interface cell is an important component of high performance computers and communication electronic equipments,and is helpful to solve this bottleneck problem in the extensive application fields. The high speed LVDS I/O interface chip FTLVDS that we designed in the task is an useful taste to solve the bottleneck.
We design the chip FTLVDS by means of "top-down" and "bottom-up" mixed tecknique. The chip's function includes transmitter-receiver of LVDS signal and serializer-deserializer of CMOS digital signal. The full chip can be partitioned to four modules,LVDS driver,LVDS receiver,serializer and deserializer. We implement these modules with different approaches based on their fuctions and characters.
The LVDS driver and LVDS receiver designed by the means of full custom design approach,are not only the most important circuits in the chip FTLVDS but also the emphases of the task. The paper has an emphatical discussion on the study and analysis of the circuit structure and layout structure of these two modules,and makes a lot of SPICE simulation and verification.
The serializer and deserializer moduls in the FTLVDS chip are designed by the way of standard cell design approach. The paper emphatically discusses the tradeoff and the implementation of several clock synchronization modes and circuit structures,and makes a lot of Verilog simulation and verification on the circuits designed.
The whole FTLVDS chip is a combination of LVDS driver,LVDS receiver,serializer and deserializer. It's layout is implemented by the means of full-custom and half-custom mixed design approach,and the chip is taped out.
This task of self-determination design of high speed LVDS I/O interface chip,as a part of the project "high speed digital signal interlink and transmit technology" on the foundation of National Laboratory For Parallel & Distributed Processing,on the one hand provide absolutely necessarily experiment foundation and hardware elements for the research of high speed digital signal transmission,on the other hand make an available exploration for the forward design methods of IC chips by means of full-custom and half-custom mixed design
approach.
低电压差分信号LVDS是一个用于高速信号传输的国际通用接口标准，同时具有高速度、低噪声、低功耗和低成本的突出优点。LVDS高速I／O接口单元是高性能计算机和通讯电子设备中重要的构件，能够在广泛的应用领域里解决高速数据传输的瓶颈问题。本课题所设计的LVDS高速I／O接口芯片FTLVDS，正是对解决这一瓶颈的有益尝试。
FTLVDS芯片采用了“自顶向下”和“由底向上”相结合的正向设计方法。该芯片的功能包括LVDS信号的收发以及CMOS数据的串并转换。芯片可划分为LVDS驱动器、LVDS接收器、串行化器和解串行器四个模块。根据这些模块的功能及特点，分别采用了不同的设计方法来实现。
收发模块LVDS驱动器和接收器是LVDS高速I／O接口芯片的关键电路，采用全定制的方法设计，也是本课题的重点。课题着重对这两个模块的电路结构以及版图结构进行了深入的研究和分析，并采用SPICE工具进行了模拟验证。
串并模块串行化器和解串行器采用标准单元的方法设计，论文讨论了对几种时钟同步模式以及串并转换电路结构的权衡和实现，并对所设计的电路结构进行了Verilog模拟验证。
FTLVDS芯片是收发模块和串并模块的组合，其版图实现采用了全定制单元和标准单元混合的设计方法，并且进行了投片封装。
本课题对LVDS高速I／O接口单元芯片FTLVDS的自主设计研究，作为国防科技重点实验室基金项目“高速数字信号互连与信号传输技术”的一部分，一方面为进行高速数字信号传输的研究提供了不可缺少的实验依据和硬件基础，另一方面也是对IC芯片正向设计中采用全定制和半定制的混合设计方法的一次有益探索。
With the great development of the technology of computer architecture and the technology of semiconductor,the frequency of the timing clock in the 1C chips has been faster and faster. Then the difference of data transmission speed between inside and outside of current CMOS chips has been a bottleneck influencing the performance of computer systems.
LVDS(Low Voltage Differential Signaling) is an international common interface sdandard that applied to high speed signal transmitter. The high speed LVDS I/O interface cell is an important component of high performance computers and communication electronic equipments,and is helpful to solve this bottleneck problem in the extensive application fields. The high speed LVDS I/O interface chip FTLVDS that we designed in the task is an useful taste to solve the bottleneck.
We design the chip FTLVDS by means of "top-down" and "bottom-up" mixed tecknique. The chip's function includes transmitter-receiver of LVDS signal and serializer-deserializer of CMOS digital signal. The full chip can be partitioned to four modules,LVDS driver,LVDS receiver,serializer and deserializer. We implement these modules with different approaches based on their fuctions and characters.
The LVDS driver and LVDS receiver designed by the means of full custom design approach,are not only the most important circuits in the chip FTLVDS but also the emphases of the task. The paper has an emphatical discussion on the study and analysis of the circuit structure and layout structure of these two modules,and makes a lot of SPICE simulation and verification.
The serializer and deserializer moduls in the FTLVDS chip are designed by the way of standard cell design approach. The paper emphatically discusses the tradeoff and the implementation of several clock synchronization modes and circuit structures,and makes a lot of Verilog simulation and verification on the circuits designed.
The whole FTLVDS chip is a combination of LVDS driver,LVDS receiver,serializer and deserializer. It's layout is implemented by the means of full-custom and half-custom mixed design approach,and the chip is taped out.
This task of self-determination design of high speed LVDS I/O interface chip,as a part of the project "high speed digital signal interlink and transmit technology" on the foundation of National Laboratory For Parallel & Distributed Processing,on the one hand provide absolutely necessarily experiment foundation and hardware elements for the research of high speed digital signal transmission,on the other hand make an available exploration for the forward design methods of IC chips by means of full-custom and half-custom mixed design
approach.
引文
[1] Jan M. Rabaey.Digital integrated circuits:a design perspective, Prentice-Hall, Inc.1996
[2] 艾伦 P E，霍尔伯格D R著．CMOS模拟电路设计，王正华，叶小琳译，北京：电子工业出版社，1995
[3] 甘学温编著．数字CMOSVLSI分析与设计基础，北京：北京大学出版社，1999．2
[4] 沈绪榜编著．超大规模集成系统设计，北京：科学出版社，1991
[5] 李志坚，周润德主编，ULSI器件电路与系统，北京：科学出版社，2000
[6] 贾新章，郝跃编著．微电子技术概论．北京：国防工业出版社，1995
[7] 杨之廉，申明编著．超大规模集成电路设计方法学导论，清华大学出版社，1999
[8] R．R．特劳特曼著．CMOS中的闩锁效应：问题及其解决办法，北京：科学出版社，1996
[9] D．A．帕特内尔，K．埃什拉吉安著．超大规模集成电路设计基础：系统与电路，北京：科学出版社，1996
[10] Neil,H.E Weste, Kamran, Eshraghian. VLSI设计，ADDISON WISLEY PULISHING COMPANY, 1993
[11] 李本俊编著．CMOS集成电路原理与设计，北京：北京邮电大学出版社，1997
[12] PR．格雷，KG．迈耶著．模拟集成电路的分析与设计，合肥：中国科大学出版社 1981
[13] 樊昌信编著．数字专用集成电路设计，北京：人民邮电出版社，1993．
[14] National Semiconductor, LVDS Owner's Manual:A General Design Guide for National's Low Voltage Differential Signaling (LVDS) and Bus LVDS Products,www. national.com/appinfo/lvds/
[15] Stephen Kempainen.低压差分信令(LVDS), Insight, 2000年第5卷第2期
[16] Microprocessor and Microcomputer Standards Committee of the IEEE Computer Society.IEEE Standard for Low-Voltage Differential Signals (LVDS) for Scalable Coherent Inteface (SCI),1996
[17] Barbara A. Chappell. Fast CMOS ECL Receivers With 100-mV Worst-Case Sensitivity, IEEE Journal of Solid-State Circuits,VOL.23,NO.1,February 1988
[18] 姜晶菲，倪晓强，张民选．串行链路高速I／O接口的研究，计算机工程与科学，2000年第22卷第A1期，长沙：计算机科学与工程杂志社
[19] 刘祥远，陈书明．LVDS高速I／O接口单元的设计研究，计算机工程与科学，2001年第23卷第4期，长沙：计算机科学与工程杂志社
[20] 李振涛，陈书明．预防闩锁效应的CMOS版图设计技术，国防科技大学首届研究生学术活动周论文集，长沙：国防科技大学出版社，2001年10月
[21] Victor P.Nelson.H.Troy Nagle,Bill D.Carroll,J.David Irwin.Digital Logic Circuit
Analysis&Design, Prentice Hall, Inc. 1995
[22] Andrea Boni, Andrea Pierazzi, David Vecchi. LVDS I/O Interface for Gb/s-per-Pin Operation in 0． 35-urn CMOS, IEEE Journal of Solid-State Circuits, VOL.36, NO.4, April 2001
[23] Gountis V.Kristovski, Yuri L.Pogrebnoy. New Sense Amplifier for Small-Swing CMOS Logic Circuits, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, VOL.47, N0． 6, June 2000
[24] National Semiconductor. DS92LV1023 and DS92LV1224 40-66 MHz 10 Bit Bus LVDS Serializer and Deserializer, www.national.com/appinfo/lvds/, May 2000
[25] Uwe Vogel, Rolf Jahne, Steffen Ulbricht, Gerd Bunk, Marcel Steinert, Christoph Zimmermann, Takeshi Iwamoto, Rainer Kokozinski. LVDS I/O Cells with Rail-to-Rail Receiver Input for SONET/SDH at 1． 25Gb/s, European Solid-State Circuits Conference, September 2000
[26] Douglas, J. Smith. HDL Chip Design: A Practical Guide for Designing, Synthesizing, and Simulating ASICs and FPGAs using VHDL or Verilog, Doone Publications, 1997
[27] Evelina Yeung, Mark Horowitz. A 2． 4Gb/s/pin Simultaneous Bidirectional Parallel Link with Per Pin Skew Compensation, IEEE International Solid State Circuits Conference, February 2000
[28] Vladimir Stojanovic, George Ginis, Mark A.Horowitz. Transmit Pre-emphasis for High-Speed Timing-Division-Multiplexed Serial-Link Transceiver, IEEE International Conference on Communications, April 2002
[29] http://www.national.com
[30] http://bmc.bu.edu
[31] http://www.ieee.org
[32] http://fujitsu.co.jp/index-e.html
[33] http://bwrc.eecs.berkeley.edu/Classes/IcBook/index.html
[34] http://kabuki.eecs.berkeley.edu
[35] http://velox.stanford.edu/cgi-bin/papers.cgi?paper
[36] http://www.eetchina.com
[37] http://www.chinaasic.com
[38] http://www.chinaicip.com
[39] http://www.fpga.com.cn/hdl.htm
[40] http://www.21 icbbs.com/club/default.asp
[41] http://ieeexplore.ieee.org/lpdocs/epic03
[42] http://www.ti.com
[43] http://www.dtt.com.cn
[44] http://www.ssreader.com.cn/pdg.html
[45] 张兴,黄如,刘晓彦。微电子学概论,北京:北京大学出版社,2000年1月
[46] http://www.csmc.com.cn
[2] 艾伦 P E，霍尔伯格D R著．CMOS模拟电路设计，王正华，叶小琳译，北京：电子工业出版社，1995
[3] 甘学温编著．数字CMOSVLSI分析与设计基础，北京：北京大学出版社，1999．2
[4] 沈绪榜编著．超大规模集成系统设计，北京：科学出版社，1991
[5] 李志坚，周润德主编，ULSI器件电路与系统，北京：科学出版社，2000
[6] 贾新章，郝跃编著．微电子技术概论．北京：国防工业出版社，1995
[7] 杨之廉，申明编著．超大规模集成电路设计方法学导论，清华大学出版社，1999
[8] R．R．特劳特曼著．CMOS中的闩锁效应：问题及其解决办法，北京：科学出版社，1996
[9] D．A．帕特内尔，K．埃什拉吉安著．超大规模集成电路设计基础：系统与电路，北京：科学出版社，1996
[10] Neil,H.E Weste, Kamran, Eshraghian. VLSI设计，ADDISON WISLEY PULISHING COMPANY, 1993
[11] 李本俊编著．CMOS集成电路原理与设计，北京：北京邮电大学出版社，1997
[12] PR．格雷，KG．迈耶著．模拟集成电路的分析与设计，合肥：中国科大学出版社 1981
[13] 樊昌信编著．数字专用集成电路设计，北京：人民邮电出版社，1993．
[14] National Semiconductor, LVDS Owner's Manual:A General Design Guide for National's Low Voltage Differential Signaling (LVDS) and Bus LVDS Products,www. national.com/appinfo/lvds/
[15] Stephen Kempainen.低压差分信令(LVDS), Insight, 2000年第5卷第2期
[16] Microprocessor and Microcomputer Standards Committee of the IEEE Computer Society.IEEE Standard for Low-Voltage Differential Signals (LVDS) for Scalable Coherent Inteface (SCI),1996
[17] Barbara A. Chappell. Fast CMOS ECL Receivers With 100-mV Worst-Case Sensitivity, IEEE Journal of Solid-State Circuits,VOL.23,NO.1,February 1988
[18] 姜晶菲，倪晓强，张民选．串行链路高速I／O接口的研究，计算机工程与科学，2000年第22卷第A1期，长沙：计算机科学与工程杂志社
[19] 刘祥远，陈书明．LVDS高速I／O接口单元的设计研究，计算机工程与科学，2001年第23卷第4期，长沙：计算机科学与工程杂志社
[20] 李振涛，陈书明．预防闩锁效应的CMOS版图设计技术，国防科技大学首届研究生学术活动周论文集，长沙：国防科技大学出版社，2001年10月
[21] Victor P.Nelson.H.Troy Nagle,Bill D.Carroll,J.David Irwin.Digital Logic Circuit
Analysis&Design, Prentice Hall, Inc. 1995
[22] Andrea Boni, Andrea Pierazzi, David Vecchi. LVDS I/O Interface for Gb/s-per-Pin Operation in 0． 35-urn CMOS, IEEE Journal of Solid-State Circuits, VOL.36, NO.4, April 2001
[23] Gountis V.Kristovski, Yuri L.Pogrebnoy. New Sense Amplifier for Small-Swing CMOS Logic Circuits, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, VOL.47, N0． 6, June 2000
[24] National Semiconductor. DS92LV1023 and DS92LV1224 40-66 MHz 10 Bit Bus LVDS Serializer and Deserializer, www.national.com/appinfo/lvds/, May 2000
[25] Uwe Vogel, Rolf Jahne, Steffen Ulbricht, Gerd Bunk, Marcel Steinert, Christoph Zimmermann, Takeshi Iwamoto, Rainer Kokozinski. LVDS I/O Cells with Rail-to-Rail Receiver Input for SONET/SDH at 1． 25Gb/s, European Solid-State Circuits Conference, September 2000
[26] Douglas, J. Smith. HDL Chip Design: A Practical Guide for Designing, Synthesizing, and Simulating ASICs and FPGAs using VHDL or Verilog, Doone Publications, 1997
[27] Evelina Yeung, Mark Horowitz. A 2． 4Gb/s/pin Simultaneous Bidirectional Parallel Link with Per Pin Skew Compensation, IEEE International Solid State Circuits Conference, February 2000
[28] Vladimir Stojanovic, George Ginis, Mark A.Horowitz. Transmit Pre-emphasis for High-Speed Timing-Division-Multiplexed Serial-Link Transceiver, IEEE International Conference on Communications, April 2002
[29] http://www.national.com
[30] http://bmc.bu.edu
[31] http://www.ieee.org
[32] http://fujitsu.co.jp/index-e.html
[33] http://bwrc.eecs.berkeley.edu/Classes/IcBook/index.html
[34] http://kabuki.eecs.berkeley.edu
[35] http://velox.stanford.edu/cgi-bin/papers.cgi?paper
[36] http://www.eetchina.com
[37] http://www.chinaasic.com
[38] http://www.chinaicip.com
[39] http://www.fpga.com.cn/hdl.htm
[40] http://www.21 icbbs.com/club/default.asp
[41] http://ieeexplore.ieee.org/lpdocs/epic03
[42] http://www.ti.com
[43] http://www.dtt.com.cn
[44] http://www.ssreader.com.cn/pdg.html
[45] 张兴,黄如,刘晓彦。微电子学概论,北京:北京大学出版社,2000年1月
[46] http://www.csmc.com.cn