AIN、ta-C薄膜制备及其在SOI技术中的应用研究
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摘要
SOI材料可成功的应用于微电子的大多数领域，但由于其SiO_2绝缘埋层的自热效应，使其在高温高功率器件中的应用受到局限。科学家们已经对此问题进行了大量的研究，并提出了一些可行性方案。为解决此间题，本文提出采用热传导性能较好的绝缘层取代SiO_2薄膜来解决。
为开发具有不同绝缘层材料的新型SOI材料和技术，我们首先针对传统SOI结构以及新型SOI结构，建立了适用于“电-热-结构”分析的电热模型，并分析了温度变化对迁移率、载流子浓度、阈值电压、源漏特性等SOI器件主要电学特性参数的影响情况，发现温度升高将使器件沟道迁移率和阈值电压下降，并影响器件的源漏特性及本征载流子浓度，这一观察有利于进一步从理论上探讨和研究功率器件的自热效应给器件性能带来的负面影响。
另外，本文还研究了SOI器件运行过程中，由于自身功耗而导致的自加热过程以及散热过程的特点。为定量研究不同环境温度条件下，由于器件功耗导致的晶格温度和内部热应力在器件中的分布情况，我们采用ANSYS v6.1有限元分析软件，模拟了不同器件结构受到自热效应影响的程度。分别从电-热-结构的相互作用等方面研究了自热效应对SOI结构的影响。研究结果表明，AlN、金刚石(diamond)、四面体非晶碳膜(Tetrahedral amorphous carbon，简称ta-C)等薄膜的热传导性能均远优于SiO_2薄膜；应力沼器件纵向分布的结果表明，SiO_2SOI和diamond SOI器件的应力沿纵向的变化幅度较大，采用ta-C薄膜可以有效降低此幅度。
在上述研究基础上，本文分别采用离子束增强沉积(IBED)和真空磁过滤弧源沉积(FAD)的方法在p-Si(100)衬底上成功制备了AlN薄膜和ta-C薄膜，研究了不同沉积参数对薄膜性能的影响情况，并优化了沉积工艺及参数；通过多种表征方法测试了薄膜的性能，为进一步制备SOI材料奠定了基础。
对于AlN薄膜，采用AFM、XPS等表征方法研究了薄膜的微观表面形貌、微观组织结构、化学成分等特性，研究结果表明，制备的薄膜具有纳米级别光滑的表面。研究了采用MIS电容法测试材料电学特性的理论基础、实验方法以及参数提取方法等。采用Al／AlN／Si MIS器件结构，结合SRP、C-V、I-V等
A】N、ta一C薄膜制备及其在501技术中的应用研究
巴里里里里里巴里巴里里里里里里里理组口口旦旦旦口里口旦旦巨里亘
测试手段，获得了AIN薄膜的电阻率、有效介电常数、阀值电压、击穿电场等
电学特性参数，并表征了薄膜的电绝缘性能。沉积过程中，通入适量氮气有助
于使N/Al比接近化学计量比，有效提高薄膜的电绝缘性能。AIN薄膜的击穿场
强可以达到1.42MV/cm。
对于ta一C薄膜，采用AFM、RBS、非卢瑟福背散射(non~RBs)等表征方
法研究了薄膜的微观表面形貌、微观组织结构、化学成分等特性。研究结果表
明，制备的薄膜具有很低的表面粗糙度，适合501材料制备工艺中的键合过程;
设备的磁过滤系统和高真空度使所制备的薄膜中杂质含量很低(如氧含量低于
2%)，薄膜纯度较高。采用AI/ta一C/51 Mls器‘牛结构，结合C一V、I一V等测试
手段，获得了ta一C薄膜的电阻率、有效介电常数、阂值电压、击穿电场等电学
特性参数，并表征了薄膜的电绝缘性能。ta.C薄膜的击穿场强可以达到
4 .7MV/em。
研究结果表明，制备的AIN和ta一C薄膜具有较高的电绝缘性能和热传导性
能及很低的表面粗糙度，可以结合Smart一Cut工艺制备新型501材料。
Silicon-on-insulator (SOI) is expected to become mainstream substrate for microelectronics in near future. For many applications, such as high-speed and low-power consuming ICs, SOI substrates offer numerous advantages as compared to bulk silicon, i.e. lower parasitic capacitances, improved subthreshold characteristics of transistors, and higher currert gain of amplifiers. However, application of SOI in high-temperature and high-power ICs is limited by the self-heating effect, caused by the poor thermal conductivity of the insulating SiO2 layers which will trap heat from the operating device in the operating region, then degrading operation and reducing device lifetime. Thus, to develop integrated circuit with on-chip power devices, it is important to investigate new buried insulator with good thermal conductivity.
Firstly, we built electro-thermal model for the "electro-thermal-structure" analysis of novel SOI structures with different insulating materials. In the model, the device heat flow can be well represented by the current flow in an electrical transmission line approximated by an equivalert lumped circuit consisting of the heat source and lumped thermal capacitances and resistance. Therefore, the thermal model can be represented by a series of RC-networks, the dissipated power is given by Pth(t)=V(t) I(t). The topology of the thermal network and the components of RC-networks for the calculation of temperature c istribution could be obtained by the finite element method. Using model equations and collecting all temperature dependent parameters lead to an electrical-thermal model for the device. The ambient temperature is simulated by the potential of a node in the network-model.
Then we studied the influence of temperature on main electrical parameters of SOI devices, such as mobility, carrier concentration, threshold voltage, drain-source current, etc. Our results show that the variety of temperature could influence the drain-source current and intrinsic carrier concer tration, and the channel mobility and
threshold voltage of the device decreased with increasing temperature. These results
are important for further study on the influence of self-heating effect on power devices. In details, under the same temperature, channel mobility of SiO2 SOI device is lower than that of bulk silicon device and the novel insulator SOI devices.
We also studied the self-heating and heat-dissipating process due to the power consumption during device operation. Due to considerable power dissipation and low thermal conductive SiO2 box layer, the temperalure in the SiO2 SOI device rises significantly. Analysis of the heat flow shows that the temperature rise AT in the device due to self-heating is given by , where R(t) is thermal resistance, which is dependent on thermal conductivity, area and thickness of every layer.
To study the lattice-temperature and internal thermal-stress distribution caused by power consumption under different environment temperature, we simulated the influence of self-heating effect on different device structures through the finite element software of ANSYS v6.1. We also studied the interaction among electricity, heat and structure. To better compare with each other, we choose the same size for all the SOI structures, i.e. bulk silicon LDMOSFET, SiO2 SOI LDMOSFET, A1N SOI LDMOSFET, diamond SOI LDMOSFET and ta-C SOI LDMOSFET.
For the electro-thermal model, we choose the coupled-field analysis in ANSYS v6.1, which could be divided by two parts: thermal and stress simulation. For the first part, we finished defining the element type, real constants, materials property, constrains, and creating geometry model, then began to simulate the structures, i.e. the step of "Current LS". Thus the results of thermal distribution in every structure could be obtained. For the second part, we switched the element type from "thermal" to "structure" and defined the material properties fretly, then we gave the constrains and load to the structures, i.e. readin thermal analyzing results as load, thus we could be
为开发具有不同绝缘层材料的新型SOI材料和技术，我们首先针对传统SOI结构以及新型SOI结构，建立了适用于“电-热-结构”分析的电热模型，并分析了温度变化对迁移率、载流子浓度、阈值电压、源漏特性等SOI器件主要电学特性参数的影响情况，发现温度升高将使器件沟道迁移率和阈值电压下降，并影响器件的源漏特性及本征载流子浓度，这一观察有利于进一步从理论上探讨和研究功率器件的自热效应给器件性能带来的负面影响。
另外，本文还研究了SOI器件运行过程中，由于自身功耗而导致的自加热过程以及散热过程的特点。为定量研究不同环境温度条件下，由于器件功耗导致的晶格温度和内部热应力在器件中的分布情况，我们采用ANSYS v6.1有限元分析软件，模拟了不同器件结构受到自热效应影响的程度。分别从电-热-结构的相互作用等方面研究了自热效应对SOI结构的影响。研究结果表明，AlN、金刚石(diamond)、四面体非晶碳膜(Tetrahedral amorphous carbon，简称ta-C)等薄膜的热传导性能均远优于SiO_2薄膜；应力沼器件纵向分布的结果表明，SiO_2SOI和diamond SOI器件的应力沿纵向的变化幅度较大，采用ta-C薄膜可以有效降低此幅度。
在上述研究基础上，本文分别采用离子束增强沉积(IBED)和真空磁过滤弧源沉积(FAD)的方法在p-Si(100)衬底上成功制备了AlN薄膜和ta-C薄膜，研究了不同沉积参数对薄膜性能的影响情况，并优化了沉积工艺及参数；通过多种表征方法测试了薄膜的性能，为进一步制备SOI材料奠定了基础。
对于AlN薄膜，采用AFM、XPS等表征方法研究了薄膜的微观表面形貌、微观组织结构、化学成分等特性，研究结果表明，制备的薄膜具有纳米级别光滑的表面。研究了采用MIS电容法测试材料电学特性的理论基础、实验方法以及参数提取方法等。采用Al／AlN／Si MIS器件结构，结合SRP、C-V、I-V等
A】N、ta一C薄膜制备及其在501技术中的应用研究
巴里里里里里巴里巴里里里里里里里理组口口旦旦旦口里口旦旦巨里亘
测试手段，获得了AIN薄膜的电阻率、有效介电常数、阀值电压、击穿电场等
电学特性参数，并表征了薄膜的电绝缘性能。沉积过程中，通入适量氮气有助
于使N/Al比接近化学计量比，有效提高薄膜的电绝缘性能。AIN薄膜的击穿场
强可以达到1.42MV/cm。
对于ta一C薄膜，采用AFM、RBS、非卢瑟福背散射(non~RBs)等表征方
法研究了薄膜的微观表面形貌、微观组织结构、化学成分等特性。研究结果表
明，制备的薄膜具有很低的表面粗糙度，适合501材料制备工艺中的键合过程;
设备的磁过滤系统和高真空度使所制备的薄膜中杂质含量很低(如氧含量低于
2%)，薄膜纯度较高。采用AI/ta一C/51 Mls器‘牛结构，结合C一V、I一V等测试
手段，获得了ta一C薄膜的电阻率、有效介电常数、阂值电压、击穿电场等电学
特性参数，并表征了薄膜的电绝缘性能。ta.C薄膜的击穿场强可以达到
4 .7MV/em。
研究结果表明，制备的AIN和ta一C薄膜具有较高的电绝缘性能和热传导性
能及很低的表面粗糙度，可以结合Smart一Cut工艺制备新型501材料。
Silicon-on-insulator (SOI) is expected to become mainstream substrate for microelectronics in near future. For many applications, such as high-speed and low-power consuming ICs, SOI substrates offer numerous advantages as compared to bulk silicon, i.e. lower parasitic capacitances, improved subthreshold characteristics of transistors, and higher currert gain of amplifiers. However, application of SOI in high-temperature and high-power ICs is limited by the self-heating effect, caused by the poor thermal conductivity of the insulating SiO2 layers which will trap heat from the operating device in the operating region, then degrading operation and reducing device lifetime. Thus, to develop integrated circuit with on-chip power devices, it is important to investigate new buried insulator with good thermal conductivity.
Firstly, we built electro-thermal model for the "electro-thermal-structure" analysis of novel SOI structures with different insulating materials. In the model, the device heat flow can be well represented by the current flow in an electrical transmission line approximated by an equivalert lumped circuit consisting of the heat source and lumped thermal capacitances and resistance. Therefore, the thermal model can be represented by a series of RC-networks, the dissipated power is given by Pth(t)=V(t) I(t). The topology of the thermal network and the components of RC-networks for the calculation of temperature c istribution could be obtained by the finite element method. Using model equations and collecting all temperature dependent parameters lead to an electrical-thermal model for the device. The ambient temperature is simulated by the potential of a node in the network-model.
Then we studied the influence of temperature on main electrical parameters of SOI devices, such as mobility, carrier concentration, threshold voltage, drain-source current, etc. Our results show that the variety of temperature could influence the drain-source current and intrinsic carrier concer tration, and the channel mobility and
threshold voltage of the device decreased with increasing temperature. These results
are important for further study on the influence of self-heating effect on power devices. In details, under the same temperature, channel mobility of SiO2 SOI device is lower than that of bulk silicon device and the novel insulator SOI devices.
We also studied the self-heating and heat-dissipating process due to the power consumption during device operation. Due to considerable power dissipation and low thermal conductive SiO2 box layer, the temperalure in the SiO2 SOI device rises significantly. Analysis of the heat flow shows that the temperature rise AT in the device due to self-heating is given by , where R(t) is thermal resistance, which is dependent on thermal conductivity, area and thickness of every layer.
To study the lattice-temperature and internal thermal-stress distribution caused by power consumption under different environment temperature, we simulated the influence of self-heating effect on different device structures through the finite element software of ANSYS v6.1. We also studied the interaction among electricity, heat and structure. To better compare with each other, we choose the same size for all the SOI structures, i.e. bulk silicon LDMOSFET, SiO2 SOI LDMOSFET, A1N SOI LDMOSFET, diamond SOI LDMOSFET and ta-C SOI LDMOSFET.
For the electro-thermal model, we choose the coupled-field analysis in ANSYS v6.1, which could be divided by two parts: thermal and stress simulation. For the first part, we finished defining the element type, real constants, materials property, constrains, and creating geometry model, then began to simulate the structures, i.e. the step of "Current LS". Thus the results of thermal distribution in every structure could be obtained. For the second part, we switched the element type from "thermal" to "structure" and defined the material properties fretly, then we gave the constrains and load to the structures, i.e. readin thermal analyzing results as load, thus we could be
引文
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2 石涌泉，微电子学与计算机，2(1995)1
3 W. P. Maszara, Proc. 4th International Symposium on Silicon-on-insulator Technology and Devices, 90-6 (1990) 199
4 W.A. Krull and J. C. Lee, Proceedings SOS/SOI Technology Workshop, 1989, p.69
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2 石涌泉，微电子学与计算机，2(1995)1
3 W. P. Maszara, Proc. 4th International Symposium on Silicon-on-insulator Technology and Devices, 90-6 (1990) 199
4 W.A. Krull and J. C. Lee, Proceedings SOS/SOI Technology Workshop, 1989, p.69
5 R Ratnam, Electronics Letters, 25 (1989) 536
6 W.A. Krull, J. F. Buller, G. V. Rouse and R. D.Cherne, IEEE Circuits and Devices Magazine, 1987, p.20
7 T. Letavic, E. Arnold, M. Simpson, R. Aquino, et al., Proceedings of the 1997 IEEE International SOI Conference, 1997, p.49
8 T. Letavic, E. Arnold, M. Simpson, E. Peters, R. Aquino, R. Egloff, S. Wong, S. Mukherjee, Proceedings of the 1998 IEEE International SOI Conference, 1998, p. 133
9 A. Nakagawa, N. Yasuhara, I. Omura, Y. Yamaguchie, T. Ogura, T. Matsudai, IEDM Tech. Dig., 1992, p.229
10 M. Stoisiek, K. G. Oppermaun, U. Schwalke, D. Takacs, Proceedings 7th International Symposium Power Semiconductor Devices and Ics, 1995, p.325
11 Arnold E, Letavic T, Merchant S, Bhimnathwala S, International Electron Devices Meeting Technical Digest, 1996, p.93-6
12 H.T. Lim, F. Udrea, D. M. Garner, W. I. Milne, Solid-State Electronics, 43 (1999) 1267
13 G. A. J. Amaratunga, E Udrea, R. A. McMahon, Proceedings of the 1999 Bipolar/BiCMOS Circuits and Technologies Meeting, 1999, p.75
14 K. Mitani and T. Abe, IEEE International SOI Conference Proceedings, 1992, p. 18
15 东立，微电子学，25 (1995) 63
16 S.Krause, M.Anc, P.Roitman, MRS Bulletin, 23 (1999) 25
17 A.Ogura, H.Ono, Applied Surface Science, 159 (2000) 104
18 M.Bruel, MRS Bulletin, 23 (1999) 35
19 M.Bruel, Electronics Letters, 31 (1995) 1201
20 J.R.Kaschny, P.F.P. Fichtner, A.Muechlich, U.Kreissig, R.A. Yankov, W.Skorupa, Nucler Insrt. and Methods in Phy. Research B136-138 (1998) 583
21 www.soitec.com
22 Q.Y.Tong, R.W. Bower, MRS Bulletin 23 (1998)40
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