基于时间并行交替技术的超高速高精度波形数字化研究
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摘要
在核与粒子物理试验中,探测器输出的脉冲信号波形携带有粒子最全面、最详细的物理信息。一直以来,国内外的实验物理学家都在致力研究获取粒子脉冲信号波形的方法,但是都受到了计算机技术和模拟数字变换器(ADC)芯片设计工艺方面的巨大限制。所以,为了突破ADC芯片对采样率的限制,实现更高的采样率,发展并行ADC结构变得非常的重要。本论文的重点是设计和实现了基于时间交替采样技术的超高速并行模拟数字变换系统(8Bit10Gsps)和高速高精度实时模拟数字变换系统(14Bit1600Msps)。众所周知,并行交替型模拟数字变换系统不可避免的会带来通道失配误差,从而极大的降低系统的动态和静态性能。所以,对通道失配误差的修正成为整个设计的必不可少的部分。为了实现对高速高精度并行交替模拟数字变换系统通道误差的实时修正,本论文提出基于完美重构方法多相实现的硬件并行算法。
论文的第一章介绍了粒子物理实验中波形数字化技术的发展状况,以及目前对波形数字化技术的迫切需求和所面临的困境,从而引出了可以突破单芯片限制的基于时间并行交替采样技术。
在第二章中回顾了最基本的采样定理、ADC的工作原理和性能指标,以及详细的介绍了超高速Flash ADC和高速高精度Pipeline ADC这两种ADC结构,为后面的两个并行交替系统中所选择的ADC芯片做好理论基础。
第三章首先介绍了常见的采样技术,然后给出了并行交替采样技术的详细介绍,包括通道失配误差的分析,通道失配误差对ADC输出数据的频谱贡献的仿真。
第四章在第三章的理论基础上,给出了高速高精度时间并行交替采样系统的一般硬件架构,给出了并行交替采样系统的硬件实现所面临的难点和挑战,同时给出了数字后处理算法的研究,提出了基于完美重构方法多相实现的并行修正算法,并且给出了其仿真结果。
第五章和第六章分别介绍了14Bit1600Msps高速高精度实时并行交替模拟数字变换系统和8Bit10Gsps超高速并行交替模拟数字变换系统的硬件设计和实现。对两个系统的多相时钟、前端模拟信号拆分、高速并行数据的接收和缓存、数据命令传输接口以及电源散热等设计都分别给出了详细的介绍,尤其在第五章中详细的给出了基于完美重构方法多相实现的并行修正算法在FPGA中的硬件实现。
第七章给出了两个系统的测试结果。对于14Bit1600Msps高速高精度并行交替模拟数字变换系统,分别给出了基于软件修正和硬件修正的结果。可以看到二者的修正效果基本一致,在输入信号频率低于100MHz时基本和单芯片的性能相当,但是到高频部分,由于失配误差随频率发生变化,修正效果逐渐变差。对于8Bit10Gsps超高速并行交替系统,由于ADC在整个模拟带宽范围内的频率响应一致性很好,所以在整个模拟带宽内,经过软件修正后的性能指标和单芯片手册给出的指标基本相当。
最后,在第八章给出了工作的总结和对下一步工作的展望。
In nuclear and particle physics experiments, the waveforms of the pulse signals generated by detectors carry the most comprehensive and detailed physical information. Many experimental physicists in the world have been trying their best to find an effective method to obtain the waveforms of the pulse signals generated by particles. However, the technology of the Analog-to-Digital Converter (ADC) has become a bottle-neck. Hence, to break through the limit of the ADC's sampling rate with a given resolution, it is very important to develop the parallel ADC architectures. In this dissertation, we focus on the designs and implementations of two time-interleaved based parallel ADC system (TIADC), which are ultra-high-speed (10Gsps and8-bit) ADC system and high-speed high-resolution (1600Msps and14-bit) ADC system respectively. Due to the well-known reason that the time-interleaved technique brings the channel mismatch errors, which cause the so-called pattern noises and significantly degrade the dynamic and static performance of the TIADC system, the mismatch errors correction becomes an essential part of the TIADC system. To realize a real-time correction of the high-speed high-resolution TIADC system, a new correction method named parallel multichannel-filtering approach, which is based on the poly-phase realization of the perfect reconstruction filter banks method, is proposed in this dissertation.
In chapter1, we first introduce the development, the urgent needs and the difficulties of the waveform digitization technology employed in the particle physics experiments, and then present the time-interleaved technique which can be used to break through the limits of a single ADC chip.
Chapter2includes the review of the sampling theory and ADC theory&performance, the detailed introduction of two different architecture ADCs ultra-high-speed flash ADC and high-speed high resolution Pipeline ADC, which are used in the two TIADC systems.
First, the common sampling techniques are presented in chapter3, and then the time-interleaved technique is introduced in detail, including the analysis and simulation of mismatch errors.
Based on the theory presented in the chapter3, general hardware architecture of high-speed high-resolution TIADC system is introduced in chapter4, and then we discuss the difficulties and challenges faced in the implementation of high-speed high-resolution TIADC systems. At the end of chapter4, the parallel multichannel-filtering approach is proposed and corresponding simulations are done to verify it.
In chapter5and6, we introduce the designs and implementations of a14Bit1600Msps high-speed high-resolution TIADC system and an8Bit10Gsps ultra-high-speed TIADC system respectively. We focus on the multi-phase clock, the analog input signal splitting, high-speed parallel data receiving and buffering, the implementation of the parallel multichannel-filtering approach in the FPGA, commands and data transfer interface and power and thermal considerations, especially the implementation of the parallel multichannel-filtering approach in the FPGA.
To evaluate the performance of these two TIADC systems and the accuracy of the parallel multichannel-filtering approach, the effective and detailed test is done and introduced in chapter7. For the14Bit1600Msps high-speed high-resolution TIADC system, we give the test results of software based correction and hardware real-time correction respectively. The results indicated that the hardware real-time correction working well. For the8Bit10Gsps ultra-high-speed TIADC system, we present the software based correction results, which indicate that the performance of the TIADC system in the whole analog bandwidth is nearly the same as the typical performance of a single ADC chips given by the data sheet.
At last, in chapter8, we give a summary of the work and the outlook for the next work in future.
论文的第一章介绍了粒子物理实验中波形数字化技术的发展状况,以及目前对波形数字化技术的迫切需求和所面临的困境,从而引出了可以突破单芯片限制的基于时间并行交替采样技术。
在第二章中回顾了最基本的采样定理、ADC的工作原理和性能指标,以及详细的介绍了超高速Flash ADC和高速高精度Pipeline ADC这两种ADC结构,为后面的两个并行交替系统中所选择的ADC芯片做好理论基础。
第三章首先介绍了常见的采样技术,然后给出了并行交替采样技术的详细介绍,包括通道失配误差的分析,通道失配误差对ADC输出数据的频谱贡献的仿真。
第四章在第三章的理论基础上,给出了高速高精度时间并行交替采样系统的一般硬件架构,给出了并行交替采样系统的硬件实现所面临的难点和挑战,同时给出了数字后处理算法的研究,提出了基于完美重构方法多相实现的并行修正算法,并且给出了其仿真结果。
第五章和第六章分别介绍了14Bit1600Msps高速高精度实时并行交替模拟数字变换系统和8Bit10Gsps超高速并行交替模拟数字变换系统的硬件设计和实现。对两个系统的多相时钟、前端模拟信号拆分、高速并行数据的接收和缓存、数据命令传输接口以及电源散热等设计都分别给出了详细的介绍,尤其在第五章中详细的给出了基于完美重构方法多相实现的并行修正算法在FPGA中的硬件实现。
第七章给出了两个系统的测试结果。对于14Bit1600Msps高速高精度并行交替模拟数字变换系统,分别给出了基于软件修正和硬件修正的结果。可以看到二者的修正效果基本一致,在输入信号频率低于100MHz时基本和单芯片的性能相当,但是到高频部分,由于失配误差随频率发生变化,修正效果逐渐变差。对于8Bit10Gsps超高速并行交替系统,由于ADC在整个模拟带宽范围内的频率响应一致性很好,所以在整个模拟带宽内,经过软件修正后的性能指标和单芯片手册给出的指标基本相当。
最后,在第八章给出了工作的总结和对下一步工作的展望。
In nuclear and particle physics experiments, the waveforms of the pulse signals generated by detectors carry the most comprehensive and detailed physical information. Many experimental physicists in the world have been trying their best to find an effective method to obtain the waveforms of the pulse signals generated by particles. However, the technology of the Analog-to-Digital Converter (ADC) has become a bottle-neck. Hence, to break through the limit of the ADC's sampling rate with a given resolution, it is very important to develop the parallel ADC architectures. In this dissertation, we focus on the designs and implementations of two time-interleaved based parallel ADC system (TIADC), which are ultra-high-speed (10Gsps and8-bit) ADC system and high-speed high-resolution (1600Msps and14-bit) ADC system respectively. Due to the well-known reason that the time-interleaved technique brings the channel mismatch errors, which cause the so-called pattern noises and significantly degrade the dynamic and static performance of the TIADC system, the mismatch errors correction becomes an essential part of the TIADC system. To realize a real-time correction of the high-speed high-resolution TIADC system, a new correction method named parallel multichannel-filtering approach, which is based on the poly-phase realization of the perfect reconstruction filter banks method, is proposed in this dissertation.
In chapter1, we first introduce the development, the urgent needs and the difficulties of the waveform digitization technology employed in the particle physics experiments, and then present the time-interleaved technique which can be used to break through the limits of a single ADC chip.
Chapter2includes the review of the sampling theory and ADC theory&performance, the detailed introduction of two different architecture ADCs ultra-high-speed flash ADC and high-speed high resolution Pipeline ADC, which are used in the two TIADC systems.
First, the common sampling techniques are presented in chapter3, and then the time-interleaved technique is introduced in detail, including the analysis and simulation of mismatch errors.
Based on the theory presented in the chapter3, general hardware architecture of high-speed high-resolution TIADC system is introduced in chapter4, and then we discuss the difficulties and challenges faced in the implementation of high-speed high-resolution TIADC systems. At the end of chapter4, the parallel multichannel-filtering approach is proposed and corresponding simulations are done to verify it.
In chapter5and6, we introduce the designs and implementations of a14Bit1600Msps high-speed high-resolution TIADC system and an8Bit10Gsps ultra-high-speed TIADC system respectively. We focus on the multi-phase clock, the analog input signal splitting, high-speed parallel data receiving and buffering, the implementation of the parallel multichannel-filtering approach in the FPGA, commands and data transfer interface and power and thermal considerations, especially the implementation of the parallel multichannel-filtering approach in the FPGA.
To evaluate the performance of these two TIADC systems and the accuracy of the parallel multichannel-filtering approach, the effective and detailed test is done and introduced in chapter7. For the14Bit1600Msps high-speed high-resolution TIADC system, we give the test results of software based correction and hardware real-time correction respectively. The results indicated that the hardware real-time correction working well. For the8Bit10Gsps ultra-high-speed TIADC system, we present the software based correction results, which indicate that the performance of the TIADC system in the whole analog bandwidth is nearly the same as the typical performance of a single ADC chips given by the data sheet.
At last, in chapter8, we give a summary of the work and the outlook for the next work in future.
引文
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[4]Mini-Circuits Corporation, "BFCN-2555 Data sheet"
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[6]Mini-Circuits Corporation, "QCN-27 Data sheet".
[7]Hittite Microwave Corporation, "GaAs MMIC 6-BIT DIGITAL PHASE SHIFTER,2.5-3.1 GHz".
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[14]Vectron International, "VC-820 Data sheet"
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[1]Xilinx Corporation, "Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC User Guide".
[2]远坂俊昭,“锁相环(PLL)电路设计与应用,”科学出版社,2006.
[3]Hittite Microwave Corporation, "FRACTIONAL-N SYNTHESIZER w/INTEGRATED VCO1095-1275,2190-2550,4380-5100 MHz".
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[6]Mini-Circuits Corporation, "QCN-27 Data sheet".
[7]Hittite Microwave Corporation, "GaAs MMIC 6-BIT DIGITAL PHASE SHIFTER,2.5-3.1 GHz".
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[1]"IEEE Standard for Terminology and Test Methods for Analog-to-Digital Converters," IEEE Standard 1241-2010, Jan.2011.
[2]Zhao Lei etc., "A General Purpose Test Apparatus for High-Speed, High Resolution Analog to Digital Converters Based on IEEE Standard," The Eighth International Conference on Electronic Measurement and Instruments,2006
[3]赵雷,“ADC测试平台V1.0测试平台分析软件详细设计方案,”合肥：中国科学技术大学快电子学实验室,2006.
[4]J. Blair, "Histogram Measurement of ADC Nonlinearities Using Sine Waves," IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL.43, NO.3, JUNE 1994.
[5]ROHDE & SCHWARZ Corporation, "R&S SMA100A Signal Generator Data sheet"
[6]Tektronix, "Tektronix AFG3252 Arbitrary/Function Generators Data sheet"
[7]AVTECH, "Avtech AVPP-1 Ultra High Speed Pulse Generator"
[8]LeCory Corporation, "LeCory WavePro715Zi Data sheet"
[9]LeCory Corporation, "LeCory Wave Runner 104 MXI Data sheet"