基于DLX体系结构的微处理器核的设计与实现
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摘要
本文介绍了基于DLX体系结构的微处理器核的设计和实现过程。本文的目的是开发一个CPU微体系结构研究的基础平台，为体系结构研究人员提供基础的硬、软件环境。在此基础上，可以开展深入的微处理器体系结构概念和技术研究。本文使用Verilog硬件描述语言，在modelsim SE 5.6开发平台上实现了基于DLX体系结构的微处理器核。
本文剖析了Hennessy和Patterson在《Computer Architecture: A Quantitative Approach》一书中提出的DLX体系结构，通过与其它微处理器体系结构的比较，选取了DLX体系结构作为目标，并在此基础上设计了一个完备的DLX指令集。
在完成了指令集的设计之后，微处理器设计的过程主要包括功能组织、逻辑设计、实现技术等要素。本文从这些要素的角度出发，论述了DLX体系结构的微处理器设计的过程，并给出了微处理器核的细化设计。微处理器核的实现采用了流水线技术，在五段流水线当中采用互锁机制来消除指令序列当中的相关性，即在数据相关或结构相关出现的时候，采用暂停流水线的方法来消除相关性。
本文实现了二级存储系统。存储系统包括Cache存储器、主存和存储系统与流水线核之间的存控接口。本文提供了外部存储器的一种Verilog语言模拟实现，并提供了对实际存储器件进行访问的访存接口。
本文使用Verilog硬件描述语言实现了五级静态单流水线结构的DLX微处理器核的RTL级描述，并在modelsim SE 5.6开发平台上对其完成了功能验证和流水线性能分析。
本文对体系结构研究、CPU设计、研究与教学具有一定的借鉴意义和实践意义。
This paper introduces the design and realization course of a microprocessor core based on DLX architecture. Our purpose is to develop a basic platform of CPU microarchitecture research, which providing architecture researchers a basic hardware and software environment, based on which, they can perform in-depth research of microprocessor architecture concepts and technologies. We realized a microprocessor core with the help of ModelSim SE 5.6 developing platform, in Verilog HDL.
We analyzed the DLX architecture which was brought out by Hennessy and Patterson in Computer Architecture: A Quantitative Approach. Though comparison to other micro-processor architectures, we chose DLX architecture as our goal, and designed a DLX instruction set.
Under the DLX instruction set, the design flow of a microprocessor includes functionality organizing, logic designing and realization technology. We discussed the design flow of DLX microprocessor, and bring forward the detailed design of the core. We adopt an inter-locked pipeline structure in our 5 stage CPU organization, which means when there are data hazards and structure hazards in the instruction sequence, we use the method of insert stall cycles in pipeline.
We realized a 2-level storage system including a cache memory, a main memory and the memory control interface between the storage system and the pipeline core. We provided a simulation realization of the main memory with Verilog HDL. We also provided a interface to access the external memory chip.
We accomplished the RTL level description of the DLX microprocessor core in Verilog, and completed functional verification and pipeline performance analysis on the ModelSim SE 5.6 platform.
The achievements of this paper have important practical and realistic significance to computer architecture research, CPU designing, researching and teaching.
本文剖析了Hennessy和Patterson在《Computer Architecture: A Quantitative Approach》一书中提出的DLX体系结构，通过与其它微处理器体系结构的比较，选取了DLX体系结构作为目标，并在此基础上设计了一个完备的DLX指令集。
在完成了指令集的设计之后，微处理器设计的过程主要包括功能组织、逻辑设计、实现技术等要素。本文从这些要素的角度出发，论述了DLX体系结构的微处理器设计的过程，并给出了微处理器核的细化设计。微处理器核的实现采用了流水线技术，在五段流水线当中采用互锁机制来消除指令序列当中的相关性，即在数据相关或结构相关出现的时候，采用暂停流水线的方法来消除相关性。
本文实现了二级存储系统。存储系统包括Cache存储器、主存和存储系统与流水线核之间的存控接口。本文提供了外部存储器的一种Verilog语言模拟实现，并提供了对实际存储器件进行访问的访存接口。
本文使用Verilog硬件描述语言实现了五级静态单流水线结构的DLX微处理器核的RTL级描述，并在modelsim SE 5.6开发平台上对其完成了功能验证和流水线性能分析。
本文对体系结构研究、CPU设计、研究与教学具有一定的借鉴意义和实践意义。
This paper introduces the design and realization course of a microprocessor core based on DLX architecture. Our purpose is to develop a basic platform of CPU microarchitecture research, which providing architecture researchers a basic hardware and software environment, based on which, they can perform in-depth research of microprocessor architecture concepts and technologies. We realized a microprocessor core with the help of ModelSim SE 5.6 developing platform, in Verilog HDL.
We analyzed the DLX architecture which was brought out by Hennessy and Patterson in Computer Architecture: A Quantitative Approach. Though comparison to other micro-processor architectures, we chose DLX architecture as our goal, and designed a DLX instruction set.
Under the DLX instruction set, the design flow of a microprocessor includes functionality organizing, logic designing and realization technology. We discussed the design flow of DLX microprocessor, and bring forward the detailed design of the core. We adopt an inter-locked pipeline structure in our 5 stage CPU organization, which means when there are data hazards and structure hazards in the instruction sequence, we use the method of insert stall cycles in pipeline.
We realized a 2-level storage system including a cache memory, a main memory and the memory control interface between the storage system and the pipeline core. We provided a simulation realization of the main memory with Verilog HDL. We also provided a interface to access the external memory chip.
We accomplished the RTL level description of the DLX microprocessor core in Verilog, and completed functional verification and pipeline performance analysis on the ModelSim SE 5.6 platform.
The achievements of this paper have important practical and realistic significance to computer architecture research, CPU designing, researching and teaching.
引文
[1] A Comparison of DLX, ARM/Thumb, MCORE and 80x86 Architectures
[2] ARM Architechture Reference Manual. Advanced RISC Machines, LTD, 1996-2000
[3] ARM? Datasheet. Advanced RISC Machines, LTD, 1994
[4] Altera Data Book.Altera Corporation, 1996
[5] Dave Jagger, David Seal. "ARM Architecture Reference Manual (2nd Edition)". Addison-Wesley Pub Co. ISBN:0201737191
[6] David A.Sykes and Brain A Malloy. "The Design of An Efficient Simulator for Pentium Pro Processor". Proceedings of the 1996 Winter Simulation Conference. 1996． pp. 840-847
[7] Donald E. Thomas, Philip R Moorby,The Verilog Hardware Description Language.KLUWER ACADEMIC PUBLISHERS,2001
[8] Douglas, J. Smith. HDL Chip Design: A Practical Guide for Designing, Synthesizing, and Simulating ASICs and FPGAs using VHDL or Verilog, Doone Publications, 1997
[9] Gerry Kane. "MIPS RISC Architechture". Prentice Hall, Englewood Cliffs, NJ. 1989
[10] http://www.opencores.org/
[11] http://www.enetis.net/-mitch/hdlsources.html
[12] http://www.rs.e-technik.tu-darmstadt.de/THD/res/dlxdocu/SuperscalarDLX.html
[13] http://xirisc.deis.unibo.it/description.html
[14] http://bwrc.eecs.berkeley.edu/Classes/IcBook/index.html
[15] http://kabuki.eecs.berkeley.edu/
[16] http://velox.stanford.edu/cgi-bin/papers.cgi?paper
[17] http://aether01 .cs.umbc.edu/-skumar3/reports/DLXreport.pdf
[18] http://i61 www.ira.uka.de/users/asfour/TI/ DLX-Pipeline/dlx-pipeline.html
[19] http://www.ece.uah.edu/-milenka/cpe631 /cpe631-115-6． pdf
[20] http://www.cs.utsa.edu/faculty/boppana/courses/carch-common/dlx-pipeline-events.pdf
[21] http://www.arches.uga.edu/-kaarthik/projects/dlx.html
[22] http://www.cs.umd.edu/class/falll998/cmsc411/ proj01/DLX/aboutDLX.html
[23] http://wwwl.columbia.edu/sec/bboard/ 021 /coms4824-001 /msg00116． html
[24] http://www.eetchina.com/
[25] http://www.chinaasic.com/
[26] http://www.chinaicip.com/
[27] http://www.fpga.com.cn/hdl.htm
[28] http://www.21 icbbs.com/club/default.asp
[29] Neil, H.E Weste, Kamran, Eshraghian. VLSI Design, ADDISON WISLEY PULISHING COMPANY, 1993
[30] Patterson D A, Hennessy J L. Computer Architecture: A Quantitative Approach. 2nd ed.San Francisco: Morgan Kaufmann Publish, 1996
[31] SA-110 Microprocessor Technical Reference Manual. December 2000．
[32] S.B.Furber, "VLSI RISC Architecture and Organization", Marcel Dekker, New York 1989
[33] Stalling W. " Computer Organization and Architecture " Englewood Cliffs:Prentice Hall, 1996
[34] Stephen Brown and Jonathan Rose. Architecture of FPGAs and CPLDs: A Tutorial.
Department of Electrical and Computer Engineering,University of Toronto
[35]Stephen Hill, The ARM10 family of advanced microprocessor cores, Hot Chips 13,2000
[36]Victor P. Nelson, H.Troy Nagle, Bill D.Carroll, J.David Irwin. Digital Logic Circuit Analysis&Design, Prentice Hall, Inc. 1995
[37]www.cs.iastate.edu/～prabhu/Tutorial/PIPELINE/DLXpipe.html
[38]D．A．帕特内尔，K，埃什拉吉安著．超大规模集成电路设计基础：系统与电路，北京：科学出版社，1996
[39]樊昌信编著．数字专用集成电路设计，北京：人民邮电出版社，1993．
[40]侯伯亭，顾新．VHDL硬件描述语言与数字逻辑电路设计．西安：电子科技大学出版社，1999
[41]J．Bhasker著．徐振林 等译．Verilog HDL硬件描述语言(Second Edition)．机械工业出版社．2000
[42]陆洪毅 沈立 戴葵 王志英，“一种高性能的嵌入式微处理器：银河TS-1”，电子学报，Nov．2002
[43]王金明，杨吉斌编著．数字系统设计与verilogHDL．北京：电子工业出版社，2002
[44]夏仁霖 胡传国 卢克盛 陈福生等 编．RISC技术参考大全．电子工业出版社．1992
[45]徐惠民，安德宁．单片微型计算机 原理·接口·应用．北京：北京邮电学院出版社，1990
[46]杨之廉，申明编著．超大规模集成电路设计方法学导论，清华大学出版社，1999
[47]张亮 编著．数字电路设计与Verilog HDL．人民邮电出版社．2000
[48]张奎刚，徐连海，张华．ALTERA FPGA简介及其在LED显示屏控制中的应用
[49]赵学秘，王蕾等．TS-1设计文档．长沙：国防科技大学
[50]曾繁泰，候亚宁，崔元明．可编程器件应用导论．北京：清华大学出版社．2001
[51]周明德．微型计算机原理及应用(上册修订版)．北京：清华大学出版社，1991
[2] ARM Architechture Reference Manual. Advanced RISC Machines, LTD, 1996-2000
[3] ARM? Datasheet. Advanced RISC Machines, LTD, 1994
[4] Altera Data Book.Altera Corporation, 1996
[5] Dave Jagger, David Seal. "ARM Architecture Reference Manual (2nd Edition)". Addison-Wesley Pub Co. ISBN:0201737191
[6] David A.Sykes and Brain A Malloy. "The Design of An Efficient Simulator for Pentium Pro Processor". Proceedings of the 1996 Winter Simulation Conference. 1996． pp. 840-847
[7] Donald E. Thomas, Philip R Moorby,The Verilog Hardware Description Language.KLUWER ACADEMIC PUBLISHERS,2001
[8] Douglas, J. Smith. HDL Chip Design: A Practical Guide for Designing, Synthesizing, and Simulating ASICs and FPGAs using VHDL or Verilog, Doone Publications, 1997
[9] Gerry Kane. "MIPS RISC Architechture". Prentice Hall, Englewood Cliffs, NJ. 1989
[10] http://www.opencores.org/
[11] http://www.enetis.net/-mitch/hdlsources.html
[12] http://www.rs.e-technik.tu-darmstadt.de/THD/res/dlxdocu/SuperscalarDLX.html
[13] http://xirisc.deis.unibo.it/description.html
[14] http://bwrc.eecs.berkeley.edu/Classes/IcBook/index.html
[15] http://kabuki.eecs.berkeley.edu/
[16] http://velox.stanford.edu/cgi-bin/papers.cgi?paper
[17] http://aether01 .cs.umbc.edu/-skumar3/reports/DLXreport.pdf
[18] http://i61 www.ira.uka.de/users/asfour/TI/ DLX-Pipeline/dlx-pipeline.html
[19] http://www.ece.uah.edu/-milenka/cpe631 /cpe631-115-6． pdf
[20] http://www.cs.utsa.edu/faculty/boppana/courses/carch-common/dlx-pipeline-events.pdf
[21] http://www.arches.uga.edu/-kaarthik/projects/dlx.html
[22] http://www.cs.umd.edu/class/falll998/cmsc411/ proj01/DLX/aboutDLX.html
[23] http://wwwl.columbia.edu/sec/bboard/ 021 /coms4824-001 /msg00116． html
[24] http://www.eetchina.com/
[25] http://www.chinaasic.com/
[26] http://www.chinaicip.com/
[27] http://www.fpga.com.cn/hdl.htm
[28] http://www.21 icbbs.com/club/default.asp
[29] Neil, H.E Weste, Kamran, Eshraghian. VLSI Design, ADDISON WISLEY PULISHING COMPANY, 1993
[30] Patterson D A, Hennessy J L. Computer Architecture: A Quantitative Approach. 2nd ed.San Francisco: Morgan Kaufmann Publish, 1996
[31] SA-110 Microprocessor Technical Reference Manual. December 2000．
[32] S.B.Furber, "VLSI RISC Architecture and Organization", Marcel Dekker, New York 1989
[33] Stalling W. " Computer Organization and Architecture " Englewood Cliffs:Prentice Hall, 1996
[34] Stephen Brown and Jonathan Rose. Architecture of FPGAs and CPLDs: A Tutorial.
Department of Electrical and Computer Engineering,University of Toronto
[35]Stephen Hill, The ARM10 family of advanced microprocessor cores, Hot Chips 13,2000
[36]Victor P. Nelson, H.Troy Nagle, Bill D.Carroll, J.David Irwin. Digital Logic Circuit Analysis&Design, Prentice Hall, Inc. 1995
[37]www.cs.iastate.edu/～prabhu/Tutorial/PIPELINE/DLXpipe.html
[38]D．A．帕特内尔，K，埃什拉吉安著．超大规模集成电路设计基础：系统与电路，北京：科学出版社，1996
[39]樊昌信编著．数字专用集成电路设计，北京：人民邮电出版社，1993．
[40]侯伯亭，顾新．VHDL硬件描述语言与数字逻辑电路设计．西安：电子科技大学出版社，1999
[41]J．Bhasker著．徐振林 等译．Verilog HDL硬件描述语言(Second Edition)．机械工业出版社．2000
[42]陆洪毅 沈立 戴葵 王志英，“一种高性能的嵌入式微处理器：银河TS-1”，电子学报，Nov．2002
[43]王金明，杨吉斌编著．数字系统设计与verilogHDL．北京：电子工业出版社，2002
[44]夏仁霖 胡传国 卢克盛 陈福生等 编．RISC技术参考大全．电子工业出版社．1992
[45]徐惠民，安德宁．单片微型计算机 原理·接口·应用．北京：北京邮电学院出版社，1990
[46]杨之廉，申明编著．超大规模集成电路设计方法学导论，清华大学出版社，1999
[47]张亮 编著．数字电路设计与Verilog HDL．人民邮电出版社．2000
[48]张奎刚，徐连海，张华．ALTERA FPGA简介及其在LED显示屏控制中的应用
[49]赵学秘，王蕾等．TS-1设计文档．长沙：国防科技大学
[50]曾繁泰，候亚宁，崔元明．可编程器件应用导论．北京：清华大学出版社．2001
[51]周明德．微型计算机原理及应用(上册修订版)．北京：清华大学出版社，1991