SoC测试资源优化方法研究
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摘要
深亚微米工艺下IC规模和复杂度的日益增加，向SoC测试提出了严峻的挑战。现有的外部测试设备ATE在存储容量、测试通道数等测试资源方面满足不了测试需求，因而有必要研究SoC测试资源优化方法。本文分别从节省测试通道、ATE存储空间、减少测试时间的角度研究了SoC测试数据压缩、SoC测试调度以及低功耗SoC测试。本文的主要贡献为：
首先，提出了一种适用于SoC测试数据压缩的新方法。先将不同待测核对应测试集中的测试向量最大限度地重叠起来，形成一个重叠向量，然后对这个重叠向量进行变游程编码，进一步对测试向量进行压缩。由于测试应用时间与重叠向量的长度成正比，而重叠向量的长度要远小于原始测试向量长度的总和，从而减少了测试时间。实验结果显示，算法的最高测试压缩率为67．4％，最低值为39．5％，平均测试压缩率达到56％。最好情况下，测试数据被压缩了12．3倍。除了个别情况下算法的测试时间接近最优结果外，二级测试压缩方法的测试时间均少于已有算法。
其次，提出了基于测试响应复用的SoC测试数据压缩方法STC-TR和测试调度方法STS-HC。先对各个测试集进行预处理，通过预处理，用前一个核的测试响应压缩本待测核的测试激励，然后从本待测核的测试集中删掉与它前面核的测试响应相容的测试向量。在实际测试时，对于待测核的测试序列，除了最后一个核外，直接将与后一个核的测试激励相容的本待测核的测试响应作为后一个核的测试输入，对其余的测试重复上述操作。若前一个待测核的测试响应与所要施加的测试向量都不相容，则直接从ATE中取测试数据。硬件实现上只需几个二选一的多路选择器MUX，即可控制测试数据取自何处。给出了调整待测核测试顺序及与各个待测核对应的测试向量施加顺序的启发式算法，使测试效果接近最优。提出的方法不需要解码器。考虑功耗的核测试流水降低了测试应用时间。已有SoC测试调度方法的硬件开销较大，与之相比较，采用层次聚类分析的方法STS-HC解决基于测试响应复用的SoC测试调度，算法实现起来比较简单。实验结果表明，与经典的算法比较，本文的算法STS-HC的测试应用时间最少；本算法的测试压缩率平均值高达50％左右，与以往的算法是可比较的。值得一提的是，本文的方法分别将SoC基准电路p93791和p34932的故障覆盖率提高了1．32％和5．08％。可见，算法STC-TR不但没有降低各测试集的故障覆盖率，反而提高了一些测试集的故障覆盖率。
再次，提出了基于进程代数的SoC测试调度方法。为了降低测试应用时间，可采用测试流水，然而测试过程中产生的功耗可能会毁坏待测系统，鉴于这一点，流水测试时应将测试功耗控制在允许范围之内。进程代数是处理并发进程的有力工具，以进程代数为理论基础，给出了并行测试进程的时间标记变迁系统模型(TLTS)，并形成了将前者转化为进程代数ACSR(Algebraof Communicating Shared Resources)描述的几个定理，建立了SoC测试调度模型STS-ACSR。将核的并行测试映射为并发执行的进程，把测试资源建模为ACSR资源，优先级可以解决测试冲突，从而使得功耗约束下的测试获得最大并行性同时使测试应用时间最小。实验结果证明了进程代数在处理SoC测试调度问题方面优于经典的算法。
SoC test has attracted researchers' attention for years.However with theincreasing complexity and scale of IC in VDSM(Very Deep Submicron),IC testgrows costly and time-consuming,as poses severe challenges to SoC test.Moreover test resources such as storage capacities of external equipment and thenumber of test channels don't satisfy the test requirements.Consequently SoC testresources optimization is necessary for cost-effective test.This thesis exploresSoC test data compression,SoC test scheduling and low power SoC test from theperspective of reducing test channels requirement,ATE storage requirement,testapplication time and power dissipation.The contributions of the thesis conclude:
Firstly,this thesis presents a novel approach to core-based SoC testcompression.At first setp,the test vectors from different test sets are overlappedto the maximum limit to form overlapped test vectors,then Variable-Run-Length(VRL) coding is applied to the overlapped test vectors.Hence the two-levelcompressed test data are formed.Due to the fact that the test application time is inproportional to the length of overlapped test vector,and the length of actualoverlapped vectors is far less than that of the sum of the length of test vectors,thetest application time is reduced significantly.And VRL handles both run length ofzero and run length of one,thus maximizing the coding efficiency.Experimentalresults show that the proposed method achieves the highest test compression ratioof 67.4% and the lowest 39.5%,while the average test compression ratio reaches56%.In the best case,test data is reduced by 12.3 times.In addition to a few cases,the proposed method consumes the least test time.
Secondly,this thesis presents a method for SoC test compression and testscheduling based on test response reuse idea.The test sets are preprocessed beforetest.The test responses from previous cores are used to compress the test stimuliof current cores under test through preprocessing.Then delete the test vectorsfrom the test set of current cores under test,when such test vectors are compatible with the test responses of previous cores.During the actual test procedure,for allthe cores except the last one,if their corresponding test vectors are compatiblewith the test stimuli of next cores,then take the test responses of current coresunder test as the test inputs of next cores.Then repeat the above operations untiltest vectors of all the cores are processed.If the test responses of previous core arenot compatible with the test vectors to be applied,then fetch the test data ofcurrent cores under test directly from ATE.On hardware implementation,only acouple of 2-to-1 MUXs are needed to control where the test data come from.Theadjustment heuristics for test sequences of cores under test,and those of testvectors application corresponding to each cores under test are outlined to get theoptimal test effect.The proposed method does not require decoder,thus requireslittle hardware overhead.Power constrained core test pipelining further reducestest application time.For test response reuse-based SoC test scheduling,hierarchical clustering STS-HC is adopted for test time minimization.Comparedto previous published methods,this method is easy to implement and consumeslittle hardware.Experimental results on benchmarks show that,compared to theexisting methods,STS-HC consumes the least test time and that our testcompression ratio is relatively higher.The average test compression ratio reachesup to 50%.In addition,the fault coverage for SoC benchmark circuit p93791 andp34932 is increased by 1.32% and 5.08% respectively.Therefore algorithmSTC-TR increases fault coverage of some test sets,at least it does not compromisethe fault coverage of each test set.
Thirdly,this thesis presents process algebra-based SoC test scheduling.Testpipelining can be adoPted to minimize test application time.However,in order toavoid the high test power destroying system under test,the test power occurredduring test is to be kept under control.Process algebra is known for handlingconcurrent processes.This thesis forms time-labeled-transition-system model forconcurrent processes based on process algebra,and establishes some theoremsand definitions to convert the former to the ACSR(Algebra of CommunicatingShared Resources) description.And SoC test scheduling model STS-ACSR is outlined.The concurrent SoC test is mapped into concurrently executed processes,and test resources are modeled as ACSR resources.Priority assignments avoid testconflicts.Thus the power constrained SoC test achieves maximum testconcurrency and least test application time.The experimental results prove theefficiency of process algebra in handling SoC test scheduling in comparison to theclassical algorithms.
首先，提出了一种适用于SoC测试数据压缩的新方法。先将不同待测核对应测试集中的测试向量最大限度地重叠起来，形成一个重叠向量，然后对这个重叠向量进行变游程编码，进一步对测试向量进行压缩。由于测试应用时间与重叠向量的长度成正比，而重叠向量的长度要远小于原始测试向量长度的总和，从而减少了测试时间。实验结果显示，算法的最高测试压缩率为67．4％，最低值为39．5％，平均测试压缩率达到56％。最好情况下，测试数据被压缩了12．3倍。除了个别情况下算法的测试时间接近最优结果外，二级测试压缩方法的测试时间均少于已有算法。
其次，提出了基于测试响应复用的SoC测试数据压缩方法STC-TR和测试调度方法STS-HC。先对各个测试集进行预处理，通过预处理，用前一个核的测试响应压缩本待测核的测试激励，然后从本待测核的测试集中删掉与它前面核的测试响应相容的测试向量。在实际测试时，对于待测核的测试序列，除了最后一个核外，直接将与后一个核的测试激励相容的本待测核的测试响应作为后一个核的测试输入，对其余的测试重复上述操作。若前一个待测核的测试响应与所要施加的测试向量都不相容，则直接从ATE中取测试数据。硬件实现上只需几个二选一的多路选择器MUX，即可控制测试数据取自何处。给出了调整待测核测试顺序及与各个待测核对应的测试向量施加顺序的启发式算法，使测试效果接近最优。提出的方法不需要解码器。考虑功耗的核测试流水降低了测试应用时间。已有SoC测试调度方法的硬件开销较大，与之相比较，采用层次聚类分析的方法STS-HC解决基于测试响应复用的SoC测试调度，算法实现起来比较简单。实验结果表明，与经典的算法比较，本文的算法STS-HC的测试应用时间最少；本算法的测试压缩率平均值高达50％左右，与以往的算法是可比较的。值得一提的是，本文的方法分别将SoC基准电路p93791和p34932的故障覆盖率提高了1．32％和5．08％。可见，算法STC-TR不但没有降低各测试集的故障覆盖率，反而提高了一些测试集的故障覆盖率。
再次，提出了基于进程代数的SoC测试调度方法。为了降低测试应用时间，可采用测试流水，然而测试过程中产生的功耗可能会毁坏待测系统，鉴于这一点，流水测试时应将测试功耗控制在允许范围之内。进程代数是处理并发进程的有力工具，以进程代数为理论基础，给出了并行测试进程的时间标记变迁系统模型(TLTS)，并形成了将前者转化为进程代数ACSR(Algebraof Communicating Shared Resources)描述的几个定理，建立了SoC测试调度模型STS-ACSR。将核的并行测试映射为并发执行的进程，把测试资源建模为ACSR资源，优先级可以解决测试冲突，从而使得功耗约束下的测试获得最大并行性同时使测试应用时间最小。实验结果证明了进程代数在处理SoC测试调度问题方面优于经典的算法。
SoC test has attracted researchers' attention for years.However with theincreasing complexity and scale of IC in VDSM(Very Deep Submicron),IC testgrows costly and time-consuming,as poses severe challenges to SoC test.Moreover test resources such as storage capacities of external equipment and thenumber of test channels don't satisfy the test requirements.Consequently SoC testresources optimization is necessary for cost-effective test.This thesis exploresSoC test data compression,SoC test scheduling and low power SoC test from theperspective of reducing test channels requirement,ATE storage requirement,testapplication time and power dissipation.The contributions of the thesis conclude:
Firstly,this thesis presents a novel approach to core-based SoC testcompression.At first setp,the test vectors from different test sets are overlappedto the maximum limit to form overlapped test vectors,then Variable-Run-Length(VRL) coding is applied to the overlapped test vectors.Hence the two-levelcompressed test data are formed.Due to the fact that the test application time is inproportional to the length of overlapped test vector,and the length of actualoverlapped vectors is far less than that of the sum of the length of test vectors,thetest application time is reduced significantly.And VRL handles both run length ofzero and run length of one,thus maximizing the coding efficiency.Experimentalresults show that the proposed method achieves the highest test compression ratioof 67.4% and the lowest 39.5%,while the average test compression ratio reaches56%.In the best case,test data is reduced by 12.3 times.In addition to a few cases,the proposed method consumes the least test time.
Secondly,this thesis presents a method for SoC test compression and testscheduling based on test response reuse idea.The test sets are preprocessed beforetest.The test responses from previous cores are used to compress the test stimuliof current cores under test through preprocessing.Then delete the test vectorsfrom the test set of current cores under test,when such test vectors are compatible with the test responses of previous cores.During the actual test procedure,for allthe cores except the last one,if their corresponding test vectors are compatiblewith the test stimuli of next cores,then take the test responses of current coresunder test as the test inputs of next cores.Then repeat the above operations untiltest vectors of all the cores are processed.If the test responses of previous core arenot compatible with the test vectors to be applied,then fetch the test data ofcurrent cores under test directly from ATE.On hardware implementation,only acouple of 2-to-1 MUXs are needed to control where the test data come from.Theadjustment heuristics for test sequences of cores under test,and those of testvectors application corresponding to each cores under test are outlined to get theoptimal test effect.The proposed method does not require decoder,thus requireslittle hardware overhead.Power constrained core test pipelining further reducestest application time.For test response reuse-based SoC test scheduling,hierarchical clustering STS-HC is adopted for test time minimization.Comparedto previous published methods,this method is easy to implement and consumeslittle hardware.Experimental results on benchmarks show that,compared to theexisting methods,STS-HC consumes the least test time and that our testcompression ratio is relatively higher.The average test compression ratio reachesup to 50%.In addition,the fault coverage for SoC benchmark circuit p93791 andp34932 is increased by 1.32% and 5.08% respectively.Therefore algorithmSTC-TR increases fault coverage of some test sets,at least it does not compromisethe fault coverage of each test set.
Thirdly,this thesis presents process algebra-based SoC test scheduling.Testpipelining can be adoPted to minimize test application time.However,in order toavoid the high test power destroying system under test,the test power occurredduring test is to be kept under control.Process algebra is known for handlingconcurrent processes.This thesis forms time-labeled-transition-system model forconcurrent processes based on process algebra,and establishes some theoremsand definitions to convert the former to the ACSR(Algebra of CommunicatingShared Resources) description.And SoC test scheduling model STS-ACSR is outlined.The concurrent SoC test is mapped into concurrently executed processes,and test resources are modeled as ACSR resources.Priority assignments avoid testconflicts.Thus the power constrained SoC test achieves maximum testconcurrency and least test application time.The experimental results prove theefficiency of process algebra in handling SoC test scheduling in comparison to theclassical algorithms.
引文
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