摘要
深亚微米工艺下IC规模和复杂度的日益增加,向SoC测试提出了严峻的挑战。现有的外部测试设备ATE在存储容量、测试通道数等测试资源方面满足不了测试需求,因而有必要研究SoC测试资源优化方法。本文分别从节省测试通道、ATE存储空间、减少测试时间的角度研究了SoC测试数据压缩、SoC测试调度以及低功耗SoC测试。本文的主要贡献为:
首先,提出了一种适用于SoC测试数据压缩的新方法。先将不同待测核对应测试集中的测试向量最大限度地重叠起来,形成一个重叠向量,然后对这个重叠向量进行变游程编码,进一步对测试向量进行压缩。由于测试应用时间与重叠向量的长度成正比,而重叠向量的长度要远小于原始测试向量长度的总和,从而减少了测试时间。实验结果显示,算法的最高测试压缩率为67.4%,最低值为39.5%,平均测试压缩率达到56%。最好情况下,测试数据被压缩了12.3倍。除了个别情况下算法的测试时间接近最优结果外,二级测试压缩方法的测试时间均少于已有算法。
其次,提出了基于测试响应复用的SoC测试数据压缩方法STC-TR和测试调度方法STS-HC。先对各个测试集进行预处理,通过预处理,用前一个核的测试响应压缩本待测核的测试激励,然后从本待测核的测试集中删掉与它前面核的测试响应相容的测试向量。在实际测试时,对于待测核的测试序列,除了最后一个核外,直接将与后一个核的测试激励相容的本待测核的测试响应作为后一个核的测试输入,对其余的测试重复上述操作。若前一个待测核的测试响应与所要施加的测试向量都不相容,则直接从ATE中取测试数据。硬件实现上只需几个二选一的多路选择器MUX,即可控制测试数据取自何处。给出了调整待测核测试顺序及与各个待测核对应的测试向量施加顺序的启发式算法,使测试效果接近最优。提出的方法不需要解码器。考虑功耗的核测试流水降低了测试应用时间。已有SoC测试调度方法的硬件开销较大,与之相比较,采用层次聚类分析的方法STS-HC解决基于测试响应复用的SoC测试调度,算法实现起来比较简单。实验结果表明,与经典的算法比较,本文的算法STS-HC的测试应用时间最少;本算法的测试压缩率平均值高达50%左右,与以往的算法是可比较的。值得一提的是,本文的方法分别将SoC基准电路p93791和p34932的故障覆盖率提高了1.32%和5.08%。可见,算法STC-TR不但没有降低各测试集的故障覆盖率,反而提高了一些测试集的故障覆盖率。
再次,提出了基于进程代数的SoC测试调度方法。为了降低测试应用时间,可采用测试流水,然而测试过程中产生的功耗可能会毁坏待测系统,鉴于这一点,流水测试时应将测试功耗控制在允许范围之内。进程代数是处理并发进程的有力工具,以进程代数为理论基础,给出了并行测试进程的时间标记变迁系统模型(TLTS),并形成了将前者转化为进程代数ACSR(Algebraof Communicating Shared Resources)描述的几个定理,建立了SoC测试调度模型STS-ACSR。将核的并行测试映射为并发执行的进程,把测试资源建模为ACSR资源,优先级可以解决测试冲突,从而使得功耗约束下的测试获得最大并行性同时使测试应用时间最小。实验结果证明了进程代数在处理SoC测试调度问题方面优于经典的算法。
SoC test has attracted researchers' attention for years.However with theincreasing complexity and scale of IC in VDSM(Very Deep Submicron),IC testgrows costly and time-consuming,as poses severe challenges to SoC test.Moreover test resources such as storage capacities of external equipment and thenumber of test channels don't satisfy the test requirements.Consequently SoC testresources optimization is necessary for cost-effective test.This thesis exploresSoC test data compression,SoC test scheduling and low power SoC test from theperspective of reducing test channels requirement,ATE storage requirement,testapplication time and power dissipation.The contributions of the thesis conclude:
Firstly,this thesis presents a novel approach to core-based SoC testcompression.At first setp,the test vectors from different test sets are overlappedto the maximum limit to form overlapped test vectors,then Variable-Run-Length(VRL) coding is applied to the overlapped test vectors.Hence the two-levelcompressed test data are formed.Due to the fact that the test application time is inproportional to the length of overlapped test vector,and the length of actualoverlapped vectors is far less than that of the sum of the length of test vectors,thetest application time is reduced significantly.And VRL handles both run length ofzero and run length of one,thus maximizing the coding efficiency.Experimentalresults show that the proposed method achieves the highest test compression ratioof 67.4% and the lowest 39.5%,while the average test compression ratio reaches56%.In the best case,test data is reduced by 12.3 times.In addition to a few cases,the proposed method consumes the least test time.
Secondly,this thesis presents a method for SoC test compression and testscheduling based on test response reuse idea.The test sets are preprocessed beforetest.The test responses from previous cores are used to compress the test stimuliof current cores under test through preprocessing.Then delete the test vectorsfrom the test set of current cores under test,when such test vectors are compatible with the test responses of previous cores.During the actual test procedure,for allthe cores except the last one,if their corresponding test vectors are compatiblewith the test stimuli of next cores,then take the test responses of current coresunder test as the test inputs of next cores.Then repeat the above operations untiltest vectors of all the cores are processed.If the test responses of previous core arenot compatible with the test vectors to be applied,then fetch the test data ofcurrent cores under test directly from ATE.On hardware implementation,only acouple of 2-to-1 MUXs are needed to control where the test data come from.Theadjustment heuristics for test sequences of cores under test,and those of testvectors application corresponding to each cores under test are outlined to get theoptimal test effect.The proposed method does not require decoder,thus requireslittle hardware overhead.Power constrained core test pipelining further reducestest application time.For test response reuse-based SoC test scheduling,hierarchical clustering STS-HC is adopted for test time minimization.Comparedto previous published methods,this method is easy to implement and consumeslittle hardware.Experimental results on benchmarks show that,compared to theexisting methods,STS-HC consumes the least test time and that our testcompression ratio is relatively higher.The average test compression ratio reachesup to 50%.In addition,the fault coverage for SoC benchmark circuit p93791 andp34932 is increased by 1.32% and 5.08% respectively.Therefore algorithmSTC-TR increases fault coverage of some test sets,at least it does not compromisethe fault coverage of each test set.
Thirdly,this thesis presents process algebra-based SoC test scheduling.Testpipelining can be adoPted to minimize test application time.However,in order toavoid the high test power destroying system under test,the test power occurredduring test is to be kept under control.Process algebra is known for handlingconcurrent processes.This thesis forms time-labeled-transition-system model forconcurrent processes based on process algebra,and establishes some theoremsand definitions to convert the former to the ACSR(Algebra of CommunicatingShared Resources) description.And SoC test scheduling model STS-ACSR is outlined.The concurrent SoC test is mapped into concurrently executed processes,and test resources are modeled as ACSR resources.Priority assignments avoid testconflicts.Thus the power constrained SoC test achieves maximum testconcurrency and least test application time.The experimental results prove theefficiency of process algebra in handling SoC test scheduling in comparison to theclassical algorithms.
引文
[1] The National Technology Roadmap for Semiconductors (ITRS), 2007 Edition.Semiconductor Industry Association.
[2] H. Date, T. Hosokawa, M. Muraoka. A SoC test strategy based on a non-scan DFT method. Proceedings of 11th Asian Test Symposium (ATS'02),2002:305-310P
[3] S. Nagai, S. Ohotake, H. Fujiwara. A DFT method for RTL data paths based on strong testability to reduce test application time. Technical Report of IEICE DC2002-84,2003:31-36P
[4] E. Marinissen, R. Arendsen, G Bos et al. A structured and scalable mechanism for test access to embedded reusable cores. Proceedings of International Test Conference (ITC'98),1998:284-293P
[5] P. Varna, S. Bhatia. A structured test re-use methodology for core-based system chips. Proceedings of International Test Conference (ITC'98),1998: 294-302P
[6] N. A. Touba, B. Pouya. Testing embedded cores using partial isolation rings. Proceedings of VLSI Test Symposium,1997:10-16P
[7] L. Whetsel. An IEEE 1149.1 based test access architecture for ICs with embedded cores. Proceedings of International Test Conference (ITC'97),1997: 69-78P
[8] M. Nourani, C. A. Papachristou. Structural fault testing of embedded cores using pipelining. Journal of Electronic Testing: Theory and Applications, 1999,15(1-2):129-144P
[9] I. Ghosh, S. Dey, N. K. Jha. A fast and low cost testing technique for core-based System-on-Chip. Proceedings of 35th Design Automation Conference,1998:542-547P
[10] I. Ghosh, S. Dey, N. K. Jha. A low overhead design for testability and test generation technique for core-based system-on-a-chip. IEEE Transactions on Computer-Aided Design,1999,18(11):1661-1676P
[11] T. Yoneda, H. Fujiwara. A DFT method for core-based Systems-on-a-Chip based on consecutive testability. Proceedings of 10th Asian Test Symposium (ATS'01),2001:193-198P
[12] V. Iyengar, K. Chakrabarty, E. J. Marinissen. Test wrapper and test access mechanism co-optimization for System-on-Chip. Journal of Electronic Testing: Theory and Applications,2002,18(2):213-230P
[13] IEEE standard testability method for embedded core-based integrated circuits. IEEE Std 1500, 2005:11-13P
[14] IEEE P1500 Standard for Embedded Core Test. http://grouper.ieee.org/groups /1500/
[15] Touba N A. Survey of test vector compression techniques.IEEE Design & Test of Computers,2006,23(4):294-303P
[16] A. Chandra, K. Chakrabarty. System-on-a-Chip test-data compression and decompression architectures based on Golomb codes. IEEE Transactions on Computer-Aided Design,2001,20(3):355-368P
[17] A. Chandra, K. Chakrabarty. Test data compression and test resource partitioning for System-on-a-Chip using frequency-directed Run-Length (FDR) codes. IEEE Transactions on Computers,2003,52(8):1076-1088P
[18] A. Jas, N. A. Touba. Test vector compression via cyclical scan chains and its application to testing core-based designs. Proceedings of IEEE International Test Conference (ITC'98),1998:458-464P
[19] A. Jas, J. Ghosh-Dastidar, M. Ng et al. An efficient test vector compression scheme using selective Huffman coding. IEEE Transactions on Computer-Aided Design,2003,22(6):797-806P
[20] A. El-Maleh, S. Zahir, E. Kham. A geometric-primitives-based compression scheme for testing Systems-on-a-Chip. Proceedings of IEEE VLSI Test Symposium,2001:54-59P
[21] F. G. Wolff, C. Papachristou. Multiscan-based test compression and hardware decompression using LZ77. Proceedings of IEEE International Test Conference(ITC'02),2002:331-339P
[22]Yinhe Han,Yongjun Xu,Xiaowei Li.Co-optimization for testing power and test data compression based on variable-tail code.Proceedings of IEEE International Conference on ASIC,2003:105-108P
[23]梁华国,蒋翠云.基于交替与连续长度码的有效测试数据压缩和解压.计算机学报,2004,27(4):548-554页
[24]韩银和,李晓维,徐勇军,李华伟.应用Variable-Tail编码压缩的测试资源划分方法.电子学报,2004,32(8):1346-1350页
[25]方建平,郝跃,刘红侠,李康.应用混合游程编码的SOC测试数据压缩方法.电子学报,2005,33(11):1973-977页
[26]韩银和,李晓维.测试数据压缩和测试功耗协同优化技术.计算机辅助设计与图形学学报,2005,17(6):1307-1311页
[27]董婕,胡瑜,韩银和,李晓维.基于组合解压缩电路的多扫描链测试方法.计算机研究与发展,2006,43(6):1001-1007页
[28]欧阳一鸣,肖祝红,梁华国.数据块前向相容标记码的测试数据压缩方法.计算机辅助设计与图形学学报,2007,19(8):986-990页
[29]于静,梁华国,蒋翠云.基于测试向量压缩的多核并行测试.计算机辅助设计与图形学学报,2007,19(2):201-214页
[30]彭喜元,俞洋.基于变游程编码的测试数据压缩算法.电子学报,2007,35(2):197-201页
[31]欧阳一鸣,成丽丽,梁华国.一种基于变长数据块相关性统计的测试数据压缩和解压缩方法.电子学报,2008,36(2):298-302页
[32]S.Reda,A.Orailoglu.Reducing test application time through test data mutation encoding.Proceedings of Design,Automation,and Test in Europe,Conference and Exhibition(DATE'02),2002:387-393P
[33]B.Koenemann.LFSR-coded test patterns for scan designs.Proceedings of European Test Conference(ETC'91),1991:237-242P
[34]Krishna C V,Touba N A.Adjustable width linear combinational scan vector decompression.IEEE/ACM International Conference on Computer Aided Design(ICCAD'03),2003:863-866P
[35]G.Mrugalski,J.Rajski,J.Tyszer.Ring generators-new devices for embedded test applications.IEEE Transactions on Computer-Aided Design,2004,23(9):1306-1320P
[36]P.Wohl et al.Efficient compression and application of deterministic patterns in a logic BIST architecture.Proceedings of 41st Design Automation Conference(DAC'03),2003:566-569P
[37]E.H.Volkerink,S.Mitra.Efficient seed utilization for reseeding based compression.Proceedings of 21st VLSI Test Symposium,2003:232-237P
[38]C.V.Krishna,A.Jas,N.A.Touba.Reducing test data volume using LFSR reseeding with seed compression.Proceedings of International Test Conference,2002:321-330P
[39]P.Wohl et al.Efficient compression of deterministic patterns into multiple PRPG seeds.Proceedings of International Test Conference(ITC'05),2005:916-925P
[40]B.K(?)enemann et al.A smart BIST variant with guaranteed encoding.Proceedings of 10th Asian Test Symposium(ATS'01),2001:325-330P
[41]C.V.Krishna,A.Jas,N.A.Touba.Test vector encoding using partial LFSR reseeding.Proceedings of International Test Conference(ITC'01),2001:885-893P
[42]J.Rajski et al.Embedded deterministic test.IEEE Transactions on Computer-Aided Design,2004,23(5):776-792P
[43]梁华国,聚贝勒·海伦布昂特,汉斯-耶西姆·冯特利希.一种基于折叠计数器重新播种的确定自测试方案.计算机研究与发展,2001,38(8):931-938页
[44]梁华国,蒋翠云.使用双重种子压缩的混合模式自测试.计算机研究与发展,2004,41(1):214-220页
[45]K.-J.Lee,J.J.Chen,C.H.Huang.Using a single input to support multiple scan chains.Proceedings of International Conference on Computer-Aided Design(ICCAD'98),1998:74-78P
[46]I.Hamzaoglu,J.H.Patel.Reducing test application time for full scan embedded cores.Proceedings of IEEE International Symposium on Fault-Tolerant Computing,1999:260-267P
[47]S.Samaranayake,E.Gizdarski,N.Sitchinava et al.A reconfigurable shared scan-in architecture.Proceedings of IEEE VLSI Test Symposium,2003:9-14P
[48]Y.Han,S.Swaminathan,Y.Hu et al.Scan data volume reduction using periodically alterable MUXs decompressor.Proceedings of IEEE Asian Test Symposium(ATS'05),2005:372-377P
[49]K.J.Lee,J.J.Chen,C.H.Huang.Broadcasting test patterns to multiple circuits.IEEE Transactions on Computer-Aided Design,1999,18(12):1793-1802P
[50]Mitra S,Kee S K.X-compact:an efficient response compaction technique.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2004,23(3):421-432P
[51]韩银和.数字电路测试压缩方法研究.中国科学院博士学位论文.2005:13-27页
[52]韩银和,李华伟,李晓维.基于卷积编码的SOC测试响应压缩研究.中国科E辑:信息科学,2006,36(6):686-697页
[53]韩银和,李晓维,李华伟.适用于扫描测试中的测试响应压缩电路设计.计算机研究与发展,2005,42(7):1277-1282页
[54]叶益群,梁华国,詹凯华.基于响应分块相容的测试数据编码压缩方案.计算机辅助设计与图形学学报,2008,20(4):446-451页
[55]E.Larsson,K.Arvidsson,H.Fujiwara et al.Integrated test scheduling,test parallelization and TAM design.Proceedings of 11th Asian Test Symposium(ATS'02),2002:397-404P
[56]Y.Huang,W.T.Cheng,C.C.Tsai et al.Resource allocation and test scheduling for concurrent test of core-based SOC design.Proceedings of 10th Asian Test Symposium(ATS'01),2001:265-270P
[57]H.S.Hsu,J.R.Hung,K.L.Cheng et al.Test scheduling and test access architecture optimization for System-on-Chip.Proceedings of 11th Asian Test Symposium(ATS'02),2002:411-416P
[58]V.Iyengar,K.Chakrabarty,E.J.Marinissen.On using rectangle packaging for SOC wrapper/TAM co-optimization. Proceedings of VLSI Test Symposium,2002:253-258P
[59] Y. Huang, N. Mukherjee, S. Reddy et al. Optimal core wrapper width selection and SOC test scheduling based on 3-dimensional bin packing algorithm. Proceedings of International Test Conference (ITC'02),2002:74-82P
[60] K.Chakrabarty. Optimal test access architectures for System-on-a-Chip. ACM Transactions on Design Automation of Electronic System,2001,6(l):26-49P
[61] K.Chakrabarty. Design of System-on-a-Chip test access architectures using integer linear programming. VLSI Test Symposium,2000:127-134P
[62] K.Chakrabarty. Test scheduling for core-based systems using mixed-integer linear programming. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2000,19(10):1163-1174P
[63] S. Chattopadhyay, K.S. Reddy. Genetic algorithm based test scheduling and test access mechanism design for system-on-chips. 16th International Conference on VLSI Design,2003:341-346P
[64] W.Zou.S. M. Reddy, I. Pomeranz et al. SOC test scheduling using simulated annealing. Proceedings of VLSI Test Symposium,2003:325-330P
[65] Y.Xia, M. Chrzanowska-Jeske, Benyi Wang et al. Using a distributed rectangle bin-packing approach for core-based SOC test scheduling with power constraints. Proceedings of International Conference on Computer- Aided Design,2003:100-105P
[66] Y. Hu, Y. Han, H. Li et al. Pair balance-based test scheduling for SOCs. Proceedings of Asian Test Symposium,2004:236-241P
[67] C. P. Su, C. W. Wu. A graph-based approach to power-constrained SOC test scheduling. Journal of Electronic Testing: Theory and Applications,2004,20(1):45-60P
[68] V. Iyengar, K. Chakrabarty. Precedence-based, preemptive, and power- constrained test scheduling for System-on-a-Chip. Proceedings of the 19th VLSI Test Symposium,2001:368-374P
[69]T.Yoneda,M.Imanishi,H.Fujiwara.Interactive presentation:an SoC test scheduling algorithm using reconfigurable union wrappers.Proceedings of the Conference on Design,Automation and Test in Europe,2007:231-236P
[70]S.Koranne.Design of reconfigurable access wrappers for embedded core based SoC test.IEEE Transactions on Very Large Scale Integration Systems,2003,11(5):955-960P
[71]D.Zhao,S.J.Upadhyaya.A generic resource distribution and test scheduling scheme for embedded core-based SoCs.IEEE Transactions on Instrumentation and Measurement,2004,53(2):318-329P
[72]胡瑜,韩银和,李华伟,吕涛,李晓维.基于双核扫描链平衡的SoC测试调度.计算机辅助设计与图形学学报,2005,17(10):2203-2208页
[73]杨军,罗岚.基于TCG图和模拟退火算法的SoC测试调度.电路与系统学报.2006,11(5):37-43页,36页
[74]张弘,徐东明,李玉山.多相测试时钟低功耗BIST调度.系统工程与电子技术.2004,26(9):1162-1164页,1191页
[75]K.Roy,P.Sharat.Low power CMOS VLSI circuit design.New York:A Wiley Interscience Publication,2000
[76]F.Nekoogar,F.Nekoogar.From ASICs to SOCs.New Jersey:Prentice Hall PTR,2003
[77]Y.Zorian.A distributed BIST control scheme for complex VLSI devices.Proceedings of 11th IEEE VLSI Test S ymposium(VTS'93),1993:4-9P
[78]J.Rajski,J.Tyszer.Arithmetic Built-In Self-Test for embedded systems.Prentice Hall PTR,Upper Saddle River,N.J.,1998
[79]M.L.Bushnell,V.D.Agrawal.Essentials of Electronic Testing.Kluwer Academic,Boston,2000.14P
[80]S.Wang,S.K.Gupta.DS-LFSR:A new BIST TPG for low heat dissipation.Proceedings of International Test Conference(ITC'97),1997:848-857P
[81]J.Monzel et al.Power dissipation during testing:should we worry about it?Proceedings of the 15th IEEE VLSI Test Symposium(VTS'97),1997.456P
[82]T.W.Williams et al.IDDQ Test:Sensitivity analysis of scaling.Proceedings of International Test Conference(ITC'96),1996:786-792P
[83]P.Girard.Survey of low-power testing of VLSI circuits.IEEE Design & Test of Computers,2002,19(3):82-92P
[84]T.Shinogi,Y.Yamada,T.Hayashi et al.Between-core vector overlapping for test cost reduction in core testing.Proceedings of the Twelfth Asian Symposium(ATS'03),2003:268-273P
[85]T.Shinogi,Y.Yamada,T.Hayashi et al.Parallel core testing with multiple scan chains by test vector overlapping.International Symposium on VLSI Design,Automation and Test,2005:204-207P
[86]T.Shinogi,H.Yamada,T.Hayashi et al.A test cost reduction method by test response and test vector overlapping for full-scan test architecture.Proceedings of the Asian Test Symposium(ATS'05),2005:366-369P
[87]胡兵,陈光蹻,谢永乐.使用重复播种和Golomb编码的二维测试数据压缩.计算机辅助设计与图形学学报,2005,17(3):394-399页
[88]O.Sinanoglu,A.Orailoglu.Pipelined test of SOC cores through test data transformations.Ninth IEEE European Test Symposium(ETS'04),2004:86-91P
[89]李伟男,鄂跃鹏,葛敬国,钱华林.多模式匹配算法及硬件实现.软件学报,2006,17(12):2403-2415页
[90]Quming Zhou,Kedarnath J.Balakrishnan.Test cost reduction for SoC using a combined approach to test data compression and test scheduling.Proceedings of the Conference on Design,Automation and Test in Europe(DATE'07),2007:39-44P
[91]V.Iyengar,K.Chakrabarty.A unified SOC test approach based on test data compression and TAM design.18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems,2003:511-518P
[92]V.Iyengar,K.Chakrabarty.System-on-a-chip test scheduling with precedence relationships,preemption,and power constraints.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.2002,21(9):1088-1094P
[93] I. Hamzaoglu, J.H. Patel. Test Set Compaction Algorithms for Combinational Circuits. Proceeding of. International Conference on Computer-Aided Design,1998,283-289P
[94] A. K. Jain, M. N. Murty, P. J Flynn. Data clusering: a review. ACM Computing Surveys (CSUR),1999:264-323P
[95] J. C. M. Baeten. A brief history of process algebra. Theoretical Computer Science,2005,335:131-146P
[96] I. Lee, A. Philippou, O. Sokolsky. A family of resource-bound real-time process algebras. Electronic Notes in Theoretical Computer Science,2006,162:221-226P
[97] S. Koranne. A novel reconfigurable wrapper for testing of embedded core-based SOCs and its associated scheduling algorithm. Journal of Electronic Testing: Theory and Applications,2002,18(4-5):415-434P
[98] H. Aydin, R. Melhem, D.Mosse et al. Power-aware acheduling for periodic real-time tasks. IEEE Transactions on computers,2004,53(5):584-600P
[99] D. Clarke, I. Lee, H. Xie. VERSA: A tool for the specification and analysis of resource-bound real-time systems. Proceedings of the 8th International Conference on Computer Aided Verification. 1996,1102:402-405P
[100] G. Zeng, H.Ito. Concurrent core test for test cost reduction using merged test set and scan trees. IEEE International Conference on Computer Design:VLSI in Computers and Processors,2005,143-146P
[100] Y. Huang, W. T. Cheng, C. C. et al. On concurrent test of core-based SOC design.Journal of Electronic Testing: Theory and Applications (JETTA),2002, 18(4-5):401-414P
[101] T. Yoneda, K. Masuda, H. Fujiwara. Power-constrained test scheduling for multi-clock domain SoCs. Proceedings of the Conference on Design, Automation and Test in Europe (DATE'06),2006:297-302P
[102] Qiang Xu. Nicola Nicolici. Wrapper design for testing IP cores with multiple clock domains. Proceedings of Design, Automation and Test in Europe Conference and Exhibition,2004:416-421P
[103] Arasu T, Senthil Ravikumar, C.P. et al.A low power and low cost scan test architecture for multi-clock domain SoCs using virtual divide and conquer. Proceedings of International Test Conference (ITC'05),2005:369-377P
[104] Dorigo M et al. Guest editorial: special section on ant colony optimization. IEEE Transactions on Evolutionary Computation,2002,6(4):317-319P
[105] M.A. Cirit. Estimating dynamic power consumption of CMOS circuits. Proceedings of International Conference on Computer-Aided Design (ICCAD' 87), 1987:534-537P
[106] C.Y. Wang, K. Roy. Maximum power estimation for CMOS circuits using deterministic and statistical approaches. Proceedings of the 9th IEEE VLSI Conference,1995:364-369P
[107] A. Krstic, K.T. Cheng, S.T. Chakradhar. Testing high speed VLSI devices using slower testers. Proceedings of the 17th VLSI Test Symposium (VTS'99),1999:16-21P
[108] R. Parkar. Bare die test. Proceedings of IEEE Multi-Chip Module Conference,1992:24-27P
[109] S. Wang, S.K. Gupta. ATPG for heat dissipation minimization during test application. IEEE Transactions on Computers, 1998,47(2):256-262P
[110] S. Wang, S.K. Gupta. ATPG for heat dissipation minimization for scan testing. Proceedings of 34th ACM/IEEE Design Automation Conference (DAC'97),1997:614-619P
[111] F. Corno et al. A Test pattern generation methodology for low power consumption. Proceedings of 16th VLSI Test Symposium (VTS'98),1998:453-459P
[112] S. Chakravarty, V. Dabholkar. Minimizing power dissipation in scan circuits during test application. Proceedings of IEEE International Workshop on Low Power Design,1994:51-56P
[113] P. Girard et al. Reducing power consumption during test application by test vector ordering. Proceedings of International Symposium on Circuits and Systems (1SCAS'98),1998:296-299P
[114] V. Dabholkar et al. Techniques for reducing power dissipation during test application in full scan circuits. IEEE Transactions on Computer-Aided Design,1998,17(12):1325-1333P
[115] Y. Bonhomme et al. Scan cell ordering for low power scan testing. Proceedings of 7th European Test Workshop (ETW'02),2002:281-284P
[116] T.C. Huang, K.J. Lee. An input control technique for power reduction in scan circuits during test application. Proceedings of the 8th Asian Test Symposium (ATS'99),1999:315-320P
[117] R. Sankaralingam, R. Oruganti, N.A. Touba. Static compaction techniques to control scan vector power dissipation. Proceedings of the 18th VLSI Test Symposium (VTS'00),2000:35-42P
[118] A. Chandra, K. Chakrabarty. Combining low-power scan testing and test data compression for System-on-a-Chip. Proceedings of the 38th ACM/ IEEE Design Automation Conference (DAC'01),2001:166-169P
[119] D.Czysz, G..Mrugalski, J.Rajski et al. Low power embedded deterministic test. Proceedings of IEEE VLSI Test Symposium, 2007:75-83P
[120] L. Whetsel. Adapting scan architectures for low power operation. Proceedings of International Test Conference (ITC'00),2000:863-872P
[121] K.-J. Lee, T.-C. Huang, J.-J. Chen. Peak-power reduction for multiple-scan circuits during test application. Proceedings of 9th Asian Test Symposium (ATS'00),2000:453-458P
[122] B. Pouya, A. Crouch.Optimization trade-offs for vector volume and test Power. Proceedings of International Test Conference (ITC'00),2000:873-881P
[123] R. Sankaralingam, B. Pouya, N.A. Touba. Reducing power dissipation during test using Scan chain disable. Proceedings of 19th VLSI Test Symposium (VTS'01),2001:319-324P
[124] Y. Bonhomme et al. A gated clock scheme for low power scan testing of logic ICs or embedded cores. Proceedings of 10th Asian Test Symposium (ATS'01),2001:253-258P
[125] R.M. Chou, K.K. Saluja, V.D. Agrawal. Power constraint scheduling of tests. Proceedings of 7th International Conference on VLSI Design,1994: 271-274P
[126] J. Rajski, J. Tyszer, M. Kassab, N. Mukherjee, R.Thompson, Kun-Han Tsai, A. Hertwig, N.Tamarapalli, G.Mrugalski, G.Eider, Qian. Jun. Embedded deterministic test for low cost manufacturing test. Proceedings of International Test Conference (ITC'02),2002:301-310P
[127] P. Girard et al. A modified clock scheme for a low power BIST test pattern generator. Proceedings of the 19th VLSI Test Symposium (VTS'01), 2001:306-3 IIP
[128] X. Zhang, K. Roy, S. Bhawmik.POWERTEST: A tool for energy conscious weighted random pattern testing. Proceedings of 12th International Test Conference (ITC'99),1999:416-422P
[129] D Gizopoulos et al. Low power/energy BIST scheme for datapaths. Proceedings of the 18th VLSI Test Symposium,2000:23-28P
[130] A. Hertwig, H.J. Wunderlich. Low power serial Built-in Self-Test. Proceedings of 3rd European Test Workshop (ETW'98),1998:49-53P
[131] P. Girard et al. Low energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity. Proceedings of IEEE International Symposium on Circuits and Systems, 1999:110-113P
[132] P. Girard et al. A test vector inhibiting technique for low energy BIST design. Proceedings of the 17th VLSI Test Symposium,1999:407-412P
[133] S. Manich et al. Low Power BIST by filtering non-detecting vectors. Journal of Electronic Testing: Theory and Applications (JETTA),2000,16(3):193-202P
[134] S. Gerstend(?)rfer, H.J. Wunderlich. Minimized power consumption for scan-based BIST. Proceedings of International Test Conference (ITC'99), 1999:77-84P
[135] P. Girard et al. Low power BIST design by hypergraph partitioning: methodology and architectures. Proceedings of International Test Conference,2000:652-661P
[136] H. Cheung, S. Gupta. A BIST methodology for comprehensive testing of RAM with reduced heat dissipation. Proceedings of International Test Conference (ITC'96),1996:22-32P
[137] D. S. Ha. ATALANTA: An atpg tool. ftped from Bradley Department of Electrical Engineering, Virginia Polytechnic and State University, Blacksburg, Va, 1994.