数字集成电路测试生成算法研究
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摘要
随着现代科技的快速发展,数字集成电路已经被广泛应用于各行各业,于此同时数字集成电路的测试问题也就越来越受到人们的重视。数字集成电路设计、生产、应用的各个必要阶段都离不开测试,设计者为了验证其设计的正确性要进行测试;生产者为了保证产品的合格率要进行测试;用户为了实现正确的功能要进行测试。因此数字集成电路测试生成方法的研究在科技迅速发展的今天具有十分重要的意义。
尽管国内外学者不断提出各种数字集成电路的测试生成方法,但测试耗费在电路生产过程中仍占很大比重。从现有关于测试生成的研究来看,测试生成的主要困难在于难测故障的测试、得到的测试集尺寸较大、时序电路在测试前需要进行初始化。为此,本文在并行故障模拟的基础上,研究了基于模拟的数字集成电路测试生成方法,将新型的智能优化算法应用于电路的测试生成、测试集优化和时序电路初始化,降低了测试复杂度,减少了需要的存储空间,提高了测试效率。
首先,针对组合电路测试生成方法的研究现状,提出利用粒子群优化算法、混沌粒子群算法和文化粒子群算法实现组合电路的测试生成。整个测试算法由两部分组成:以易测故障为目标的多故障测试和以难测故障为目标的单故障测试,定义了新的适应度函数。同时提出采用半随机产生初始群体、反矢量故障模拟、逻辑相关的故障分组和排序等加速方法。分别实现了粒子群优化算法、混沌粒子群算法、文化粒子群算法在采用加速方法和不采用加速方法时ISCAS'85组合电路的测试生成。实验结果表明,这3种算法都能得到文献最好水平的故障覆盖率,同时加速方法大大提高了测试效率,其中基于加速方法的文化粒子群算法得到了最好结果。
其次,针对时序电路在测试前必须进行初始化使触发器到达确定的状态,提出利用粒子群优化算法、混沌粒子群算法和文化粒子群算法实现时序电路的逻辑初始化。并在初始化的基础上实现时序电路的测试生成,定义了新的适应度函数。以ISCAS'89时序电路为实验电路进行仿真,实验结果表明,这3种算法能生成较短的初始化序列、达到较高的故障覆盖率,其中混沌粒子群算法的故障覆盖率最高。
再次,针对常规测试方法得到的测试集尺寸较大问题,提出利用粒子群算法、混沌粒子群算法和文化粒子群算法实现电路测试集的静态优化。先对测试集进行预处理,如果测试集含有冗余矢量,则进行测试集优化。算法实现时可以采用两种编码方式:针对测试矢量编码和针对故障编码,相应地有两种适应度函数定义形式,并提出利用混沌搜索产生初始群体、对测试集进行倒序排列模拟。利用这3种算法针对不同电路进行了3个仿真实验。仿真结果表明,这3种算法均能不同程度地减小完备测试集的尺寸,其中基于故障编码的文化粒子群算法能得到最小尺寸的完备测试集。
最后,针对现有的可测性设计方法需要施加额外硬件问题,研究只需已知电路逻辑表达式、不需要施加额外硬件的基于多元症候群的组合电路可测性设计,指出它不适用于具有对于所有原始输入都对称的逻辑函数的电路。提出故障值直接前向进行逻辑运算来识别时序电路的冗余故障。利用实例证明了它们的可行性。
综上所述,本论文研究了基于智能优化算法的数字集成电路的测试矢量生成、测试集优化和可测性设计。主要采用粒子群优化算法、混沌粒子群算法和文化粒子群算法,并提出了几种加速方法。仿真实验证实,本文所应用的算法和提出的加速方法能够获得很好的效果。
With the rapid improvement of modern science and technology, digital integrated circuits have been applied in various fields broadly, and at the same time, the test generation (TG) problem of digital integrated circuits was considered more and more important by people. Digital integrated circuits can not depart from test in design, production, and application essential stages. Designers test them to confirm their correctness, producers test them to guarantee product eligibility, and users test them to carry out their right function. So researches on TG method of digital integrated circuits are significant in science and technology rapid development today.
Although domestic and foreign scholars have presented many different TG methods constantly, test spending still took up a large proportion in the circuit production process. From existent researches on TG, we can know that the difficulty of TG lies in testing difficult-detected faults, the size of test set being large and the sequential circuits having to be initialized in advance. So this paper studied on simulation-based test pattern generation (STPG) for digital integrated circuits, applied new intelligent optimization algorithms to TG、test set compaction and initialization for sequential circuits, which reduced test complexity, moreover decreased required storage space, and improved test efficiency.
Firstly, in view of the actuality of TG methods, new TG methods based on particle swarm optimization (PSO), chaotic particle swarm optimization (CHPSO) and cultural particle swarm optimization (CUPSO) for combinational circuits were proposed. The whole algorithm was mainly constructed of two parts: multiple faults test pattern generation regarding easy-detected faults as goal and single fault test pattern generation regarding a difficult-detected fault as goal, and a new fitness function was defined. Besides, several speedup methods were put forward that the initial population was produced half-randomly, introduced inverse test vector fault simulation, and adopted logical correlative fault grouping and ordering. TG for ISCAS'85 combinational circuits based on PSO, CHPSO and CUPSO algorithms when adopting these speedup methods and not adopting these speedup methods have been implemented. The experimental results indicated that these three algorithms attained the same fault coverage as the best results in references and the speedup methods improved test efficiency greatly, and CUPSO with speedup methods attained the best result.
Secondly, in view of sequential circuits having to be initialized before TG to set flip-flops to certain states, the logical initialization methods based on PSO, CHPSO and CUPSO were presented. On the base of initialization, TG for sequential circuits was carried out, and new fitness function was defined. Considering ISCAS'89 sequential circuits as object, the experimental results indicated that these three algorithms generated minimal-length initialization sequence and higher fault coverage, and CHPSO attained the highest fault coverage.
Thirdly, in view of test set from usual TG methods being larger, minimizing test set statically based on PSO, CHPSO and CUPSO was brought forward. Pretreated test set, and if the test set included redundant test vectors, we optimized the test set to attain minimal complete one. Test-vector-coding or fault-coding can be adopted, and two kinds of fitness function definitions can be adopted accordingly. And initializing population with chaotic optimization, and inversing test vectors in test set to simulate have been put forward. Three experiments have been done to different circuits with PSO, CHPSO and CUPSO. The experimental results indicated that they shortened size of complete test set to different extent, and CUPSO with fault-coding attained the minimal size complete test set.
Finally, in view of design for testability (DFT) of circuits needing extra components, combinational circuits DFT based on high-order syndrome was studied who implemented test generation depending on logical function, not needing to put extra components. That the method is not applicable in the circuit whose logical function is symmetrical to its all primitive inputs have been pointed out. Identifying redundant faults for sequential circuits by fault-value logical simulating forward was proposed. They have been proved feasible by examples.
In conclusion, on the base of intelligent optimization algorithm, this paper have researched on test pattern generation, test set optimization, and DFT for digital integrated circuits. PSO, CHPSO and CUPSO have been applied, at the same time several speedup methods have been applied too. Experimental results indicated that the adopted intelligent optimization algorithms and the proposed speedup methods could attain good results.
尽管国内外学者不断提出各种数字集成电路的测试生成方法,但测试耗费在电路生产过程中仍占很大比重。从现有关于测试生成的研究来看,测试生成的主要困难在于难测故障的测试、得到的测试集尺寸较大、时序电路在测试前需要进行初始化。为此,本文在并行故障模拟的基础上,研究了基于模拟的数字集成电路测试生成方法,将新型的智能优化算法应用于电路的测试生成、测试集优化和时序电路初始化,降低了测试复杂度,减少了需要的存储空间,提高了测试效率。
首先,针对组合电路测试生成方法的研究现状,提出利用粒子群优化算法、混沌粒子群算法和文化粒子群算法实现组合电路的测试生成。整个测试算法由两部分组成:以易测故障为目标的多故障测试和以难测故障为目标的单故障测试,定义了新的适应度函数。同时提出采用半随机产生初始群体、反矢量故障模拟、逻辑相关的故障分组和排序等加速方法。分别实现了粒子群优化算法、混沌粒子群算法、文化粒子群算法在采用加速方法和不采用加速方法时ISCAS'85组合电路的测试生成。实验结果表明,这3种算法都能得到文献最好水平的故障覆盖率,同时加速方法大大提高了测试效率,其中基于加速方法的文化粒子群算法得到了最好结果。
其次,针对时序电路在测试前必须进行初始化使触发器到达确定的状态,提出利用粒子群优化算法、混沌粒子群算法和文化粒子群算法实现时序电路的逻辑初始化。并在初始化的基础上实现时序电路的测试生成,定义了新的适应度函数。以ISCAS'89时序电路为实验电路进行仿真,实验结果表明,这3种算法能生成较短的初始化序列、达到较高的故障覆盖率,其中混沌粒子群算法的故障覆盖率最高。
再次,针对常规测试方法得到的测试集尺寸较大问题,提出利用粒子群算法、混沌粒子群算法和文化粒子群算法实现电路测试集的静态优化。先对测试集进行预处理,如果测试集含有冗余矢量,则进行测试集优化。算法实现时可以采用两种编码方式:针对测试矢量编码和针对故障编码,相应地有两种适应度函数定义形式,并提出利用混沌搜索产生初始群体、对测试集进行倒序排列模拟。利用这3种算法针对不同电路进行了3个仿真实验。仿真结果表明,这3种算法均能不同程度地减小完备测试集的尺寸,其中基于故障编码的文化粒子群算法能得到最小尺寸的完备测试集。
最后,针对现有的可测性设计方法需要施加额外硬件问题,研究只需已知电路逻辑表达式、不需要施加额外硬件的基于多元症候群的组合电路可测性设计,指出它不适用于具有对于所有原始输入都对称的逻辑函数的电路。提出故障值直接前向进行逻辑运算来识别时序电路的冗余故障。利用实例证明了它们的可行性。
综上所述,本论文研究了基于智能优化算法的数字集成电路的测试矢量生成、测试集优化和可测性设计。主要采用粒子群优化算法、混沌粒子群算法和文化粒子群算法,并提出了几种加速方法。仿真实验证实,本文所应用的算法和提出的加速方法能够获得很好的效果。
With the rapid improvement of modern science and technology, digital integrated circuits have been applied in various fields broadly, and at the same time, the test generation (TG) problem of digital integrated circuits was considered more and more important by people. Digital integrated circuits can not depart from test in design, production, and application essential stages. Designers test them to confirm their correctness, producers test them to guarantee product eligibility, and users test them to carry out their right function. So researches on TG method of digital integrated circuits are significant in science and technology rapid development today.
Although domestic and foreign scholars have presented many different TG methods constantly, test spending still took up a large proportion in the circuit production process. From existent researches on TG, we can know that the difficulty of TG lies in testing difficult-detected faults, the size of test set being large and the sequential circuits having to be initialized in advance. So this paper studied on simulation-based test pattern generation (STPG) for digital integrated circuits, applied new intelligent optimization algorithms to TG、test set compaction and initialization for sequential circuits, which reduced test complexity, moreover decreased required storage space, and improved test efficiency.
Firstly, in view of the actuality of TG methods, new TG methods based on particle swarm optimization (PSO), chaotic particle swarm optimization (CHPSO) and cultural particle swarm optimization (CUPSO) for combinational circuits were proposed. The whole algorithm was mainly constructed of two parts: multiple faults test pattern generation regarding easy-detected faults as goal and single fault test pattern generation regarding a difficult-detected fault as goal, and a new fitness function was defined. Besides, several speedup methods were put forward that the initial population was produced half-randomly, introduced inverse test vector fault simulation, and adopted logical correlative fault grouping and ordering. TG for ISCAS'85 combinational circuits based on PSO, CHPSO and CUPSO algorithms when adopting these speedup methods and not adopting these speedup methods have been implemented. The experimental results indicated that these three algorithms attained the same fault coverage as the best results in references and the speedup methods improved test efficiency greatly, and CUPSO with speedup methods attained the best result.
Secondly, in view of sequential circuits having to be initialized before TG to set flip-flops to certain states, the logical initialization methods based on PSO, CHPSO and CUPSO were presented. On the base of initialization, TG for sequential circuits was carried out, and new fitness function was defined. Considering ISCAS'89 sequential circuits as object, the experimental results indicated that these three algorithms generated minimal-length initialization sequence and higher fault coverage, and CHPSO attained the highest fault coverage.
Thirdly, in view of test set from usual TG methods being larger, minimizing test set statically based on PSO, CHPSO and CUPSO was brought forward. Pretreated test set, and if the test set included redundant test vectors, we optimized the test set to attain minimal complete one. Test-vector-coding or fault-coding can be adopted, and two kinds of fitness function definitions can be adopted accordingly. And initializing population with chaotic optimization, and inversing test vectors in test set to simulate have been put forward. Three experiments have been done to different circuits with PSO, CHPSO and CUPSO. The experimental results indicated that they shortened size of complete test set to different extent, and CUPSO with fault-coding attained the minimal size complete test set.
Finally, in view of design for testability (DFT) of circuits needing extra components, combinational circuits DFT based on high-order syndrome was studied who implemented test generation depending on logical function, not needing to put extra components. That the method is not applicable in the circuit whose logical function is symmetrical to its all primitive inputs have been pointed out. Identifying redundant faults for sequential circuits by fault-value logical simulating forward was proposed. They have been proved feasible by examples.
In conclusion, on the base of intelligent optimization algorithm, this paper have researched on test pattern generation, test set optimization, and DFT for digital integrated circuits. PSO, CHPSO and CUPSO have been applied, at the same time several speedup methods have been applied too. Experimental results indicated that the adopted intelligent optimization algorithms and the proposed speedup methods could attain good results.
引文
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