高性能sigma-delta ADC的设计与研究
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摘要
高性能的模数转换器是当今微电子模拟领域研究的热点之一。基于过采样技术和sigma-delta调制机制的模数转换器(Analog to Digital Converter, ADC)广泛使用在数字音频、综合业务数字网(Integrated Services Digital Network, ISDN)、数字电话等系统中。这种高精度的模数转换器,通过采用过采样技术,增加调制器系统的信噪比,提高其实现的精度；通过使用sigma-delta噪声整形技术,降低了信号带内的量化噪声功率。
sigma-delta ADC由模拟调制器和数字抽取滤波器组成,而模拟调制器的噪声整形性能决定了整个转换器系统的精度。本文首先对sigma-delta ADC的系统设计进行了深入的研究,采用MATLAB软件进行系统建模和仿真,并由此总结了一套完整的系统设计方法。根据过采样率、精度和动态性能的要求,得出调制器所需的阶数以及前馈因子、反馈因子和积分器增益因子等参数。然后再通过MATLAB系统仿真,预测出实际调制器可以达到的性能。在模拟调制器的设计中,各种非理想因素会极大地影响模拟调制器的性能。因此,对各种非理想因素进行系统的、量化的分析是必要的。本文对各种非理想因素,如运放有限直流增益、有限带宽和摆率、输出摆幅限制、开关非线性,时钟抖动、采样电容kT/C噪声等都进行了量化分析,从而为随后的电路设计提供了设计依据。sigma-delta ADC的结构主要分为单环(Single-Loop)结构和级联结构(Multi-stAge-noise-SHaping, MASH)两种,这两种结构具有各自的优缺点。针对这两种结构,本文分别设计了一个高阶单环一位结构的sigma-delta ADC和一个级联多位(MASH24b-24b)结构的sigma-delta ADC。
在各种过采样sigma-delta调制器的类型中,在较高信噪比(SNR),较好谐波失真性能要求的应用中,高阶单环结构的调制器结构得到了许多设计者的青睐。尽管多位量化器的使用可以消除由于积分器过载所引起的系统不稳定现象,但是一位量化器是固有线性的,因此,在线性度要求较高的情况下得到了广泛的使用。本文中设计了一款4阶单环1位的调制器以及其后的降采样数字抽取滤波器(Decimation filter or Decimator),整个芯片采用TSMC0.18μm CMOS工艺实现,芯片面积1mm×2mm,功耗为56mW。调制器采用1.8V全差分电路结构,在过采样率64,时钟频率81.92MHz,带宽640kHz内,实测精度达到了15.31位,动态范围93.9dB。降采样数字滤波器的通带波纹小于0.01dB,阻带衰减80dB,过渡带为640kHz-740kHz。数字抽取滤波器采用全数字CMOS电路实现,因此面积和功耗成为其设计的难点所在。而数字抽取滤波器采用多级结构实现,能够显著的减少数字电路的运算量和所需的存储单元,分解后的多级滤波器的运算量和存储量要远小于未分解的单个滤波器。经过数字滤波器后的信号采样频率为奈奎斯特频率,为随后的数字信号处理降低了运算量。由于芯片中既有模拟电路,又有数字电路,为了防止数字电路的噪声影响模拟电路的性能,版图的设计也至关重要。
然而,单环结构的sigma-delta ADC难以做到高速的性能。因此,未来的sigma-delta ADC将面临同时具备高速、高精度和低功耗性能的挑战。有鉴于此,本文对于宽带级联结构,提出了一个应用于无线本地局域网(Wireless Local Area Networks, WLAN)的改进型低失真sigma-delta ADC。采用前馈MASH24b-24b多位级联结构,在第二级加入反馈因子,并且每级都使用四位的量化器以减少量化噪声,从而得到较好的系统性能。由于所采用的四位DAC(Digital-to-Analog-Conve-rter)具有非线性的缺点,需要使用数字校正技术对其进行优化。目前,较为流行的数字校正技术为动态元件匹配(Dynamic Elements Match, DEM)技术,而其中以数据权重平均(Data Weighted Averaging, DWA)技术最为简单和实用。整个调制器采用0.18μm CMOS工艺设计,工作电压1.8V。测试结果表明：对于-6dBFS@1.25MHz的输入信号,采样频率160MHz时,调制器的信噪失真比(Signal-to-Noise-and-Distortion-Ratio, SNDR)峰值为80.9dB,无杂波动态范围(Spur-Free-Dynamic-Range, SFDR)为87dB,有效位数(Effect-Number-of-bit, ENOB)为13.15位。
The research of high performance, low power analog-to-digital converters (ADC) is one of the most popular discussion points in microelectronic analog design domain. By adopting oversampling technique, noise shaping and digital filtering, sigma-delta ADC has been widely used in digital audio, ISDN (Integrated Services Digital Network) and digital telephone systems. The sigma-delta modulation mechanism could decrease the quantization noise in the bandwidth and the oversampling mechanism could increase the SNR (Signal-to-Noise-Rate) and therefore increase the resolution of the converters.
Consisted with analog modulator and digital decimation filter, the sigma-delta ADC has a resolution which is determined by the performance of the noise shaping. This paper makes a deep analysis on the systematic design of the whole ADC by using MATLAB and summarizes a complete design method. According to the sampling rate, resolution and the dynamic characteristics, the feed-forward factors, feedback factors and the gain factors of the integrators can be established. Then, the performance of the modulator can be predicted by using MATLAB. The non-idealities of the analog circuits could dramatically decrease the performance of the modulator. It is necessary therefore, to make a systematic and quantized analysis of these non-idealities. The non-idealities include finite dc gain of the operation amplifier, finite unit gain bandwidth, finite slew rate, saturation, non-linearity of sampling switch, jittering, KT/C noise and so on.
There are mainly two types architecure belong to sigma-delta ADC:Single-loop and MASH (Multi-stAge-noise-SHaping), and they have their own advantages and disadvantages. Therefore, a high-order single-loop multi-bit sigma-delta modulator and a MASH24b-24b have been designed in this paper.
Generally speaking, the high-order single-loop sigma-delta modulator is popular in many applications such as systems which require high SNR ADC, simple analog circuits design and nice distortion performance. Although, multi-bit quantizer can ensure the stability of the modulator since the quantization noise is decreased, one-bit quantizer has the advantage of inherent linearity. When the requirement of high linearity is needed, one-bit quantizer is widely used in these systems. This paper presents an oversampled high-order single-loop single-bit sigma-delta analog-to-digital converter followed by a multi-stage decimation filter. Design details and measurement results of the whole chip are presented for a TSMC0.18μm CMOS implementation to achieve an ENOB of15.31-b performance over a baseband of640kHz. The modulator in this work is a fully differential circuit that operates from a single1.8-V power supply. With an oversampling ratio of64and a clock rate of81.92MHz, the modulator achieves a94dB dynamic range. The decimator achieves a pass-band ripple of less than0.01dB, a stop-band attenuation of80dB and a transition band from640kHz to740kHz. The whole chip consumes only56mW for a1.28MHz output rate and occupies a die area of1mm×2mm. Since the decimation filter is implemented in all CMOS circuits, the main problem is area and power dissipation. Designed in a cascaded structure, the storage and calculation of the decimator can be decreased and simplified. The sampling rate after filtered by the decimation becomes Nyquist rate. The layout is important as well since the chip includes not only analog circuits but also digital circuits which could influence the performance of the analog part.
However, there is a main disadvantage in sigma-delta ADC:low speed or low bandwidth. Therefore, high speed, high resolution and low power for the one modulator are the main problems in the future. An improved low distortion sigma-delta ADC for WLAN (Wireless Local Area Network) standards is presented in this paper. A feed-forward MASH24b-24b multi-bit cascaded sigma-delta ADC is adopted. However, this work has a much better performance than the ADCs which had been presented up to date by adding a feedback factor in the second stage to improve the performance of in-band SNDR (Signal-to-Noise-and-Distortion-Ratio), using4-bit ADCs in both stages to minimize the quantization noise and, therefore, DWA(Data Weighted Averaging) technology is used to decrease the mismatch noise induced by the4-bit DACs which improves the SFDR of the ADC. The modulator has been implemented by a0.18μm CMOS process and operates at a single1.8V supply voltage. Experimental results show that:for a-6dBFS@1.25MHz input signal at160MHz sampling frequency, the improved ADC with all non-idealities being considered achieves a peak SNDR of80.9dB and a SFDR of87dB. the ENOB (Effective-Number-of-bit) is13.15-bit.
sigma-delta ADC由模拟调制器和数字抽取滤波器组成,而模拟调制器的噪声整形性能决定了整个转换器系统的精度。本文首先对sigma-delta ADC的系统设计进行了深入的研究,采用MATLAB软件进行系统建模和仿真,并由此总结了一套完整的系统设计方法。根据过采样率、精度和动态性能的要求,得出调制器所需的阶数以及前馈因子、反馈因子和积分器增益因子等参数。然后再通过MATLAB系统仿真,预测出实际调制器可以达到的性能。在模拟调制器的设计中,各种非理想因素会极大地影响模拟调制器的性能。因此,对各种非理想因素进行系统的、量化的分析是必要的。本文对各种非理想因素,如运放有限直流增益、有限带宽和摆率、输出摆幅限制、开关非线性,时钟抖动、采样电容kT/C噪声等都进行了量化分析,从而为随后的电路设计提供了设计依据。sigma-delta ADC的结构主要分为单环(Single-Loop)结构和级联结构(Multi-stAge-noise-SHaping, MASH)两种,这两种结构具有各自的优缺点。针对这两种结构,本文分别设计了一个高阶单环一位结构的sigma-delta ADC和一个级联多位(MASH24b-24b)结构的sigma-delta ADC。
在各种过采样sigma-delta调制器的类型中,在较高信噪比(SNR),较好谐波失真性能要求的应用中,高阶单环结构的调制器结构得到了许多设计者的青睐。尽管多位量化器的使用可以消除由于积分器过载所引起的系统不稳定现象,但是一位量化器是固有线性的,因此,在线性度要求较高的情况下得到了广泛的使用。本文中设计了一款4阶单环1位的调制器以及其后的降采样数字抽取滤波器(Decimation filter or Decimator),整个芯片采用TSMC0.18μm CMOS工艺实现,芯片面积1mm×2mm,功耗为56mW。调制器采用1.8V全差分电路结构,在过采样率64,时钟频率81.92MHz,带宽640kHz内,实测精度达到了15.31位,动态范围93.9dB。降采样数字滤波器的通带波纹小于0.01dB,阻带衰减80dB,过渡带为640kHz-740kHz。数字抽取滤波器采用全数字CMOS电路实现,因此面积和功耗成为其设计的难点所在。而数字抽取滤波器采用多级结构实现,能够显著的减少数字电路的运算量和所需的存储单元,分解后的多级滤波器的运算量和存储量要远小于未分解的单个滤波器。经过数字滤波器后的信号采样频率为奈奎斯特频率,为随后的数字信号处理降低了运算量。由于芯片中既有模拟电路,又有数字电路,为了防止数字电路的噪声影响模拟电路的性能,版图的设计也至关重要。
然而,单环结构的sigma-delta ADC难以做到高速的性能。因此,未来的sigma-delta ADC将面临同时具备高速、高精度和低功耗性能的挑战。有鉴于此,本文对于宽带级联结构,提出了一个应用于无线本地局域网(Wireless Local Area Networks, WLAN)的改进型低失真sigma-delta ADC。采用前馈MASH24b-24b多位级联结构,在第二级加入反馈因子,并且每级都使用四位的量化器以减少量化噪声,从而得到较好的系统性能。由于所采用的四位DAC(Digital-to-Analog-Conve-rter)具有非线性的缺点,需要使用数字校正技术对其进行优化。目前,较为流行的数字校正技术为动态元件匹配(Dynamic Elements Match, DEM)技术,而其中以数据权重平均(Data Weighted Averaging, DWA)技术最为简单和实用。整个调制器采用0.18μm CMOS工艺设计,工作电压1.8V。测试结果表明：对于-6dBFS@1.25MHz的输入信号,采样频率160MHz时,调制器的信噪失真比(Signal-to-Noise-and-Distortion-Ratio, SNDR)峰值为80.9dB,无杂波动态范围(Spur-Free-Dynamic-Range, SFDR)为87dB,有效位数(Effect-Number-of-bit, ENOB)为13.15位。
The research of high performance, low power analog-to-digital converters (ADC) is one of the most popular discussion points in microelectronic analog design domain. By adopting oversampling technique, noise shaping and digital filtering, sigma-delta ADC has been widely used in digital audio, ISDN (Integrated Services Digital Network) and digital telephone systems. The sigma-delta modulation mechanism could decrease the quantization noise in the bandwidth and the oversampling mechanism could increase the SNR (Signal-to-Noise-Rate) and therefore increase the resolution of the converters.
Consisted with analog modulator and digital decimation filter, the sigma-delta ADC has a resolution which is determined by the performance of the noise shaping. This paper makes a deep analysis on the systematic design of the whole ADC by using MATLAB and summarizes a complete design method. According to the sampling rate, resolution and the dynamic characteristics, the feed-forward factors, feedback factors and the gain factors of the integrators can be established. Then, the performance of the modulator can be predicted by using MATLAB. The non-idealities of the analog circuits could dramatically decrease the performance of the modulator. It is necessary therefore, to make a systematic and quantized analysis of these non-idealities. The non-idealities include finite dc gain of the operation amplifier, finite unit gain bandwidth, finite slew rate, saturation, non-linearity of sampling switch, jittering, KT/C noise and so on.
There are mainly two types architecure belong to sigma-delta ADC:Single-loop and MASH (Multi-stAge-noise-SHaping), and they have their own advantages and disadvantages. Therefore, a high-order single-loop multi-bit sigma-delta modulator and a MASH24b-24b have been designed in this paper.
Generally speaking, the high-order single-loop sigma-delta modulator is popular in many applications such as systems which require high SNR ADC, simple analog circuits design and nice distortion performance. Although, multi-bit quantizer can ensure the stability of the modulator since the quantization noise is decreased, one-bit quantizer has the advantage of inherent linearity. When the requirement of high linearity is needed, one-bit quantizer is widely used in these systems. This paper presents an oversampled high-order single-loop single-bit sigma-delta analog-to-digital converter followed by a multi-stage decimation filter. Design details and measurement results of the whole chip are presented for a TSMC0.18μm CMOS implementation to achieve an ENOB of15.31-b performance over a baseband of640kHz. The modulator in this work is a fully differential circuit that operates from a single1.8-V power supply. With an oversampling ratio of64and a clock rate of81.92MHz, the modulator achieves a94dB dynamic range. The decimator achieves a pass-band ripple of less than0.01dB, a stop-band attenuation of80dB and a transition band from640kHz to740kHz. The whole chip consumes only56mW for a1.28MHz output rate and occupies a die area of1mm×2mm. Since the decimation filter is implemented in all CMOS circuits, the main problem is area and power dissipation. Designed in a cascaded structure, the storage and calculation of the decimator can be decreased and simplified. The sampling rate after filtered by the decimation becomes Nyquist rate. The layout is important as well since the chip includes not only analog circuits but also digital circuits which could influence the performance of the analog part.
However, there is a main disadvantage in sigma-delta ADC:low speed or low bandwidth. Therefore, high speed, high resolution and low power for the one modulator are the main problems in the future. An improved low distortion sigma-delta ADC for WLAN (Wireless Local Area Network) standards is presented in this paper. A feed-forward MASH24b-24b multi-bit cascaded sigma-delta ADC is adopted. However, this work has a much better performance than the ADCs which had been presented up to date by adding a feedback factor in the second stage to improve the performance of in-band SNDR (Signal-to-Noise-and-Distortion-Ratio), using4-bit ADCs in both stages to minimize the quantization noise and, therefore, DWA(Data Weighted Averaging) technology is used to decrease the mismatch noise induced by the4-bit DACs which improves the SFDR of the ADC. The modulator has been implemented by a0.18μm CMOS process and operates at a single1.8V supply voltage. Experimental results show that:for a-6dBFS@1.25MHz input signal at160MHz sampling frequency, the improved ADC with all non-idealities being considered achieves a peak SNDR of80.9dB and a SFDR of87dB. the ENOB (Effective-Number-of-bit) is13.15-bit.
引文
[1.1]R. H. Walden, Performance trends for analog-to-digital converters, IEEE Communication Magazine, February 1999,37:96-101.
[1.2]刘益成,罗维炳。信号处理与过采样转换器,电子工业出版社,1997.
[1.3]G. E. Moore, No exponential is forever but forever can be delayed, IEEE International Solid-State Circuits Conference,2003,1:20-23.
[1.4]K. Poulton, A 4GSamples/s 8b ADC in 0.35um CMOS, IEEE International Solid-State Circuits Conference,2002:166-167.
[1.5]H. Chen, B. Song, K. Bacrania, A 14-b 20-MSamples/s CMOS pipelined ADC, IEEE Journal of Solid-State Circuits,2001,36:997-1001.
[1.6]H. Pan, A 3.3-V 12-b 50-MS/s A/D converter in 0.6um CMOS with over 80-dB SFDR, IEEE Journal of Solid-State Circuits,2000,35:1769-1783.
[1.7]J. C. Candy, G. C. Temes, Oversampling delta-sigma data converters, IEEE Press, New York,1992.
[1.8]R. Norsworthy, R. Schreier, G. C. Temes, Delta-sigma data converters, IEEE Press, Piscataway, NJ,1997.
[1.9]Aziz, P. M. Sorensen, V. D. Spiegel, An overview of sigma-delta converters, IEEE Signal Processing Magazine,1996:61-84.
[1.10]R. Veldhoven, A tri-mode continuous time sigma delta modulator with switched-capacitor DAC for a GSM-EDGE/CDMA2000/UMTS receiver, IEEE International Solid-State Circuits Conference,2003:60-61.
[1.11]T. Kuo, K. Chen, H. Yeng, A wideband CMOS sigma-delta modulator with incremental data weighted averaging, IEEE Journal of Solid-State Circuits, 2002,37:11-17.
[1.12]C. C. Cutler, Transmission system employing quantization[P]. U S Patent, No 2927962. March 8,1960.
[1.13]F. D. Jager, Delta modulation-a method of PCM transmission using the one unit code,Philips Res.Rep.,1952,7:442-466.
[1.14]H. Inose, Y.Yasuda, J.Murakami, A telemetering system by code modulation △-∑ modulation, IRE Trans.Space Electron.Telemetry,1962,8:204-209.
[1.15]G. R. Ritchie, Higher order interpolation analog to digital converters, Ph.D. Dissertation, University of Pennsylvania,1977.
[1.16]J. C. Candy, A use of double integration in sigma-delta modulation, IEEE transactions on communications,1985:249-258.
[1.17]T. Hayashi, Y. Inabe, K. Uchimura, et al, A multistage delta-sigma modulator without double integration loop, IEEE International Solid-State Circuits Conference,1986,182-183.
[1.18]W. L. Lee, A novel higher order interpolative modulator topology for high resolution oversampling, Master thesis, MIT, Cambridge, MA,987.
[1.19]L. E. Larson, T, Cataltepe, G. C.Temes, Multi-bit oversampled sigma-delta A/D converter with digital error correction, Electron.Lett.,1988:1051-1052.
[1.20]L. R. Carley, A noise-shaping coder topology for 15-Bit converters, IEEE Journal of Solid-State Circuits,1989,24:267-273.
[1.21]T. C. Leslie, B. Siggh, An improved sigma-delta modulator architecture, IEEE International Symposium on Circuits and Systems,1990,1:372-375.
[1.22]L. A. Williams II, B. A. Wooley, Third-order cascade sigma-delta modulators, IEEE Transactions on Circuits and Systems,1991,38(5):489-498.
[1.23]N. Bridgett, C. Lewis, Effect of initial conditions on limit cycle performance of second order sampled data sigma-delta modulator, Electron.Lett.,1990,26: 817-819.
[1.24]R. Ledzius, J. I. rwin, The basis and architecture for the reduction of tones in a sigma-delta DAC, IEEE Trans. Circuits and System-II:Analog and Digital Signal Proc.,1993,40(7):429-439.
[1.25]T. H. Kuo, S. Y. Lee, D.J. Lu,3.3 V mixed-mode IC design using switched-current techniques for speech applications, IEE Proceeding-Circuits, Devices and Systems,1997,144(6):367-374.
[1.26]R. Schreier, J. Lloyd, L. Singer, et al,A 50Mw bandpass sigma delta ADC with 333kHz BW and 90dB DR, International Solid-State Circuits Conference,2002:216-217.
[1.27]K. Nguyen, R. Adams, K. Sweetland, et al, A 106-dB SNR hybrid oversamp-ling analog-to-digital converter for digital audio, IEEE Journal of Solid-State Circuits,40(12):2408-2415.
[1.28]R. D. Rio, J. M. Rosa, B. P. Verdu, et al, highly linear 2.5-V CMOS ∑△ modulator for ADSL, IEEE Transactions on Circuits and Systems,2004, 51:47-62.
[1.29]R. Gaggl, A. Wiesbauer, G. Fritz, et al, A 85-dB dynamic range multibit delta-sigma ADC for ADSL-CO applications in 0.18-μm CMOS, IEEE Journal of Solid-State Circuits,2003,38:1105-1114.
[1.30]苟曦,李怡然,陈建球,等,一个0.9V电源电压16位300μW音频ΣΔ调制器,复旦学报(自然科学版),2008,47(6)：763-768.
[1.31]Z. Li, H. Z. Yang, A 3V 5.88mW 13b 400kHz sigma-delta modulator with 84dB dynamic range,半导体学报,2008,29(11)：2232-2237.
[1.32]M. R. Miller, C. S. A. Petrie, A multibit sigma-delta ADC for multimode receivers, IEEE Journal of Solid-State Circuits,2003,38(3):475-482.
[1.33]Y. Q. Yang, T. Sculley, J. Abraham, A single die 124dB stereo audio delta sigma ADC with 111dB THD,33rd European Solid State Circuits Conference, 2007:252-255.
[1.34]K. Vleugels, S. Rabii, B. Wooley, A 2.5-V sigma-delta modulator for broadband communications applications, IEEE Journal of Solid-State Circuits, 2001,36:1887-1899.
[1.35]J. Y. Wu, Z. Y. Zhang, R. Subramoniam, et.al, A 107.4dB SNR mulit-bit sigma delta ADC with 1-PPM THD at -0.12dB from full scale input, IEEE Journal of Solid-State Circuits,2009,44(11):3060-3066.
[1.36]Y. Q. Yang, T. Sculley, J. Abraham, A 128dB dynamic range 1kHz bandwidth stereo ADC with 114dB THD, very large scale integration,2007.VLSI-SoC 2007. IFIP International Conference on 15-17:248-251.
[1.37]Z. F. Wang, Z. H Li, A Charge delta-sigma modulator for differential-capacitance sensors,传感技术学报,2006,19(5)：2252-2254.
[1.38]J. M. Rose, S. Escalera, B. P. Verdu, et al, A CMOS 110-dB@40-kS/s programmable-gain chopper-stabilized third-order 2-1 cascade sigma-delta modulator for low-power high-linearity automotive sensor ASICs, IEEE Journal of Solid-State Circuits,2005,40(11):2246-2264.
[1.39]Y. Q. Yang, T. Sculley, J. Abraham, A single die 124dB stereo audio delta sigma ADC with 111dB THD,33rd European Solid State Circuits Conference, 2007:252-255.
[1.40]J. Y. Wu, Z. Y. Zhang, R. Subramoniam, et.al, A 107.4dB SNR mulit-bit sigma delta ADC with 1-PPM THD at -0.12dB from full scale input, IEEE Journal of Solid-State Circuits,2009,44(11):3060-3066.
[1.41]I. Fujimori, L. Longo, A. Hairapetian, et al, A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8x oversampling Ratio, IEEE Journal of Solid-State Circuits,2000, 35:1820-1828.
[1.42]R. D. Rio, J. M. Rosa, B. P. Verdu, et al, highly linear2.5-V CMOS modulator for ADSL, IEEE Transactions on Circuits and Systems,2004, 51:47-62.
[1.43]K. Vleugels, S. Rabii, B. Wooley, A 2.5-V sigma-delta modulator for broadband communications applications, IEEE Journal of Solid-State Circuits, 2001,36:1887-1899.
[1.44]K. Nguyen, R. Adams, K. Sweetland, et al, A 106-dB SNR hybrid oversampling analog-to-digital converter for digital audio, IEEE Journal of Solid-State Circuits,40(12):2408-2415.
[1.45]Rebeschini M. Delta Sigma Data Converters:Theory, Design, and Simulation[M]. New York, NY:IEEE Press,1996,32-60.
[1.46]C. Ying, R. T. long, H. Z. Hang, A 16bit 96kHz chopper-stabilized sigma-delta ADC,半导体学报,2007,28(8)：1204-1209.
[1.47]Z. Li, H. Z. Yang, A 3V 5.88mW 13b 400kHz sigma-delta modulator with 84dB dynamic range,半导体学报,2008,29(11)：2232-2237.
[1.48]褚炜路,戎蒙恬,李萍,等,二阶多比特sigma-delta ADC中的自适应量化算法,上海交通大学学报,2008,42(2)：308-311.
[1.49]马绍宇,韩雁,黄小伟,等,一种高性能、低功耗音频ΣΔ调制器,半导体学报,2008,29(10)：2050-2056.
[1.50]W. Ou, X. B. Wu, High-consistency behavior modeling of a switched-capacitor sigma-delta modulator in simulink,半导体学报,2008,29(11):2209-2217.
[1.51]X. Zhang, D. S. Yu, S. M. Sheng, et al, A behavioral simulation method and an optimized design of sigma-delta ADC,北京大学学报(自然科学版),2009,45(2)：209-214.
[1.52]Z. F. Wang, Z. H Li, A Charge delta-sigma modulator for differential-capacitance sensors,传感技术学报,2006,19(5)：2252-2254.
[1.53]杨骁,陈贵灿,程军,等,一种新型级联ΣΔ调制器系统结构,西安交通大学学报,2008,42(12)：1541-1545.
[1.54]L. Chen, Y. F. Zhao, D. Y. Gao, et al, A 16 bit stereo audio ∑ △ A/D converter,半导体学报,2006,27(7)：1183-1188.
[1.55]陈雷,高精度ΣΔADC的研究,西北工业大学博士学位论文,2006.
[1.56]丁晓燕,16-bit 100ksps sigma-delta模数转换中数字滤波器的设计,西安电子科技大学硕士学位论文,2009.
[1.57]王其超,一种16位音频sigma-delta模数转换器的研究与设计,西安电子 科技大学硕士学位论文,2009.
[1.58]李梁,李儒章,张俊安,等,一种适合Σ-△A/D转换器的FIR数字滤波器,微电子学,2006,36(3)：340-343.
[2.1]M. P. Flynn, B. Sheahan, A 400MSample/s 6b COMS folding and interp-olating ADC., IEEE International Solid-State Circuits Conference,1998: 150-151.
[2.2]P. Vorenkamp, R. Roovers, A 12-b.60-MSample/s cascaded folding and interpolating ADC, IEEE Journal of Solid-State Circuits,1997,32(12): 1876-1886.
[2.3]K. Bult, A. Bauchwald, An embedded 240-mW 10-b 50MS/S CMOS ADC in 1-mm2., IEEE Journal of Solid-State Circuits,1997,32(12):1887-1895.
[2.4]H. Kimura, A. Matsuzawa, T. Natamura et al., A 10-b 300-MHZ interpolated parallel A/D converter, IEEE Journal of Solid-State Circuits,1993, SC-28(4):438-446.
[2.5]J. V. Valburg, R J. van de Plassche, An 8-b 650-MHz folding ADC, IEEE Journal of Solid-State Circuits,1992,SC-27(12):1662-1666.
[2.6]T. Wakimoto, Y. AKazawa, S. Kanaka, Si bipolar 2Gs/s 6b flash A/D converter, IEEE Journal of Solid-State Circuits,1988,SC-23(6):1345-1350.
[2.7]K. Poulton, K. L. Knudsen, J. J. Corcoan, et al, A 6-b.4 GBa/s GaAs HBT ADC, IEEE Journal of Solid-State Circuits,1995,30(10):1109-1118.
[2.8]C. Hammerschmied, Q. Huang, A MOSFET-only 10b.200ksample/s A/D converter capable of 12b untrimmed linearity, IEEE International Solid-State Circuits Conference,1997:132-133.
[2.9]S. Ramet, A 13bit 160 kHz differential analog to digital converter, IEEE International Solid-State Circuits Conference,1989:20-21.
[2.10]H. S. Lee, D. A. Hodges, P. R. Gray, A self-calibrating 15 bit CMOS A/D conterter, IEEE Journal of Solid-State Circuits,1994,SC-19(6):813-819.
[2.11]J. Yuan, C. Swensson, A 10-b 5-MS/s successive approximation ADC cell used in a 70MS/s ADC array in 1.2μm CMOS, IEEE Journal of Solid-State Circuits,1994,29. (8):866-872.
[2.12]M. Yotsuyanagi, A. Yakawa, K. Hino-oka, et al, A 12 bit 5μsec CMOS recursive ADC with 25 mW power consumption, IEEE International Solid-State Circuits Conference,1989:641-6496.
[2.13]A. Khagawa, M. Kokubo, T. Tsukada, et al, A 10b 3MSample/s CMOS cyclic ADC, IEEE International Solid-State Circuits Conference,1995:280-281.
[2.14]吴大正,信号与线性系统分析,高等教育出版社,2003.
[2.15]W. R. Bennett, Spectra of quantized signals, Bell System Technical Journal 1948,27:446-472.
[2.16]R. M. Gray, Quantization noise spectra, IEEE Transactions on Information Theory,1990,36:1220-1244.
[2.17]A. B. Sripad, D. L. Snyder, A necessary and sufficient condition for quantization errors to be uniform and white, IEEE Trans. Acoust., Speech, Signal Processing,1977, ASSP-25:442-448.
[2.18]B. Widrow, Statistical analysis of amplitude-quantized sample-data systems, Trans. AIEE-Part II:Applications and Industry,1960,79:555-568.
[2.19]R. V. Plassche, integrated analog-to-digital and digital-to-analog converters. Kluwer Academic Publishers,1994.
[2.20]刘益成,罗维炳。信号处理与过采样转换器,电子工业出版社,1997,
[2.21]J. C. Candy and 0. J. Benjamin, The structure of quantization noise from sigma-delta modulation. IEEE Trans.Commun., vol. COM-29, pp:1316-132-3, Sept.1981.
[3.1]程佩青,数字滤波与快速傅立叶变换,清华大学出版社,1990.
[3.2]郑君里等,信号与系统,高等教育出版社,1981.
[3.3]R. M. Gray, Oversampled sigma-delta modulation, IEEE Trans. Commun., vol. COM-35:pp:481-489, May,1987.
[3.4]D. Johns, K. Martin, Analog integrated circuit design, New York:Wiley, 1997.
[3.5]R. D. Rio, Reliable analysis of settling errors in SC integrators:application to △∑ modulators, Electron. Lett.,2000,36:503-504.
[3.6]Y. Geerts, M. S. J. Steyaert, W. Sansen, A high-performance multi-bit △∑ CMOS ADC, IEEE Journal of Solid-State Circuits,2000,35(12):1829-1840.D. Johns, K. Martin, Analog integrated circuit design, New York:Wiley, 1997.
[3.7]S. Rabii, B. A. Wooley, The design of low-voltage, low-power sigma-delta modulators, Norwell, MA:Kluwer,1999.
[3.8]F. Medeiro, Modeling opamp-induced harmonic distortion for switched-capacitor SD modulator design, IEEE Transactions on Circuits and Systems, 1994,5:445-448.
[3.9]S. R. Northworthy, R. Schreier, G. C. Temes, Delta-sigma data converters, Piscataway, NJ:IEEE Press,1997.
[3.10]B. E. Boser, B. A. Wooley, The design of sigma-delta modulation analog-to-digital converters, IEEE J. Solid-State Circuits,1988,22(12):1298-1308.
[3.11]J. Shieh, M. Patil, A. J. Sheu, Measurement and analysis of charge injection in MOS analog switches, IEEE Journal of Solid-State Circuits,1987, SSC-22(4):277-281.
[3.12]R. M. Gray, Spectral analysis of quantization noise in a single-loop sigma-delta modulation with dc input. IEEE Trans. Commun., vol. COM-37: 956-968. June 1989.
[3.13]P. Malcovati, S. Brigati, F. Francesconi, et al, Behavioral modeling of switched-capacitor sigma delta modulators, IEEE Transactions on Circuits and Systems,2003,50 (3):352-2364.
[3.14]T. Ritoniemi, T. Karema, H. Tenhunen, Design of stable high order 1-bit sigma-delta modulators, IEEE International Solid-State Circuits Conference, 1990,4:3267-3270.
[3.15]R. Schreier, G. C. Temes, Understanding delta-sigma data converters, Piscata-way, NJ:IEEE Press,2005.
[3.16]J. C. Candy, G. C. Temes, Oversampling delta-sigma data converters theory, design and simulation, IEEE Press, Piscataway, NJ (1992).
[3.17]J. G. Kenney, L. R. Carley, Design of multibit noise-shaping data converters, Analog Int. Circuits Signal Processing Journal,1993,3:259-272.
[3.18]M. Rizzi, Efficiency of simulation tools in designing sigma-delta ADC, AEU, 2006,60 (4).
[3.19]S. R. Norsworthy, R. Schreier, and G. C. Temes, Delta-Sigma Data Converters, Theory, Design, and Simulation, IEEE Press,1997.
[3.20]R. H. Allen, Complex Analog Filters Obtained from Shifted LowPass Prototypes, M. A. Sc. thesis, University of Toronto,1985.
[3.21]R. M. Gray, W. Chou and P. W. Wong, Quantization noise in a single-loop sigma-delta modulation with sinusoidal input. IEEE Trans. Commun., vol. COM-37:956-968.1990.
[3.22]R. M. Gray, Quantization noise spectra. IEEE Trans Information Theory, vol. IT-36:1220-1244.1990.
[3.23]R. Schreier and W. M. Snelgrove, Bandpass Sigma-Delta Modulation. Electron. Lett., vol.25, no.23, pp:1560-1561, November 9,1989.
[3.24]K. C. H. Chao, S. Nadeem, W. L. Lee, et al, A higher order topology for inter-polative modulator for oversampling A/D converter, IEEE Transactions on Circuits and Systems,1990,37(3):309-318.
[3.25]W. L. Lee, A novel higher order interpolative modulator topology for high resolution oversampling A/D converters, Master's Thesis, Massachusetts Institute of Technology, Cambridge, MA. June 1987.
[4.1]B. E. Boser, B. A. Wooley. The design of sigma-delta modulation analog-to-digital converters. IEEE J. Solid-State Circuits,1988, SC-23:1298;
[4.2]G. Paul, R. Meyer, analysis and design of analog integrated circuits, John Wiley and Sons, New York,1993.
[4.3]J. C. Candy, G. C. Temes. Oversampling methods for A/D and D/A conversion. New York, IEEE Press,1992.
[4.4]J. Wieser, R. Reed, Current source frequency compensation for a CMOS amplifier, US Patent No 4315223, November 1984.
[4.5]R. W. Adams, P. F. Ferguson, A. Ganesan, et al. Theory and practical imple-mentation of a fifth-order sigma-delta A/D converter. J. Audio Eng. Soc., 1991,39:515.
[4.6]T. Ritoniemi, T. Karema, H. Tenhumen. The design of stable high order 1-bit sigma-delta modulators. Proc.1990 IEEE Int. Symp. Circuits Sys.,1990,4: 3267.
[4.7]A. Feldman, High-speed, low-power sigma-delta modulators for RF base-band applications, Ph.D. dissertation, University of California at Berkeley, 1997.
[4.8]R. Schreier, G. C. Temes. Understanding Delta-Sigma Data Converters, John Wiley & Sons. New York,2004.
[4.9]Steven R. Norsworthy, Richard Schreier, Gabor C. Temes. Delta-Sigma Data Converters:Theory, Design, and Simulations. New York:John Wiley&Sons, 1990.
[4.10]R. Schreier. An empirical study of high-order single-bit delta-sigma modulators. IEEE Trans. Circuits Sys.,1987,40:459.
[4.11]M. Dessouky, A. Kaiser, Input switch configuration for rail-to-rail operation of switched opamp circuits, Electronics Letters,1999,35 (1):8-10.
[4.12]A. R. Feldman, "High-speed, Low-power Sigma-Delta Modulators for RF Base-band Channel Applications", PhD Dissertation, University of Californ- ia, Berkeley,1997.
[4.13]M. Dessouky, A. Kaiser, Very low-voltage digital-audio ∑-△ modulator with 88-dB dynamic range using local switch bootstrapping, IEEE Journal of Solid-State Circuits,2001,36 (3):349-355.
[4.14]Y. Geerts, M. S. J. Steyaert, and W. Sansen, "A High-performance Multi-bit? ∑△ CMOS ADC", IEEE Journal of Solid-State Circuits, Vol.35, pp.1829-1840, Dec.2000.
[4.15]T. Ritoniemi, E. Pajarre, S. Ingalsuo, et al., "A Stereo 97dB Audio Sigma-Delta ADC", ISSCC Digest of Technical Papers, pp.198-199, Feb. 1994.
[4.16]C. D. Thomposon and S. R. Bernadas, "A Digitally-corrected 20b Delta-Sigma Modulator", ISSCC Digest of Technical Papers, pp.194-195, Feb.1994.
[4.17]T. Ritoniemi, T. Karema, H. Tenhunen, Design of stable high order 1-bit sigma-delta modulators, IEEE International Solid-State Circuits Conference, 1990,4:3267-3270.
[4.18]R. Schreier, G. C. Temes, Understanding delta-sigma data converters, Pis-cataway, NJ:IEEE Press,2005.
[4.19]K. C. H. Chao, S. Nadeem, W. L. Lee, et al, A higher order topology for interpolative modulator for oversampling A/D converter, IEEE Transactions on Circuits and Systems,1990,37(3):309-318.
[4.20]Y. Geerts, M. S. J. Steyaert, and W. Sansen, "A High-performance Multi-bit ∑-△ CMOS ADC", IEEE Journal of Solid-State Circuits, Vol.35, pp.1829-1840, Dec.2000.
[4.21]B. Razavi, "Principles of Data Conversion System Design", IEEE Circuits and Systems Society, ISBN 0-7803-1093-4,1994.
[4.22]M. Waltari, K. Halonen, Bootstrapped switch without bulk effect in standard CMOS technology, Electronics Letters,2002,38 (12):555-557.
[4.23]T. S. Lee, C. C. Lu, Design techniques for low-voltage high-speed pseudo-differential CMOS track-and-hold circuit with low hold pedestal, Electronics Letters,2004,40 (9):519-520.
[4.24]T. S. Lee, C. C. Lu, A 1.5V 50-MHz CMOS pseudo-differential sample-and-hold circuit with low hold pedestal, IEEE Transaction on Circuit and Systems,2005,52 (9):1752-1757.
[4.25]C. J. B. Fayomi, G. W. Roberts, M. Sawan, low-voltage CMOS analog bootstrapped switch for sample-and-hold circuit:design and chip characterization[C]//Proceedings of IEEE International Symposium on Circuits and Systems,2005:2200-2203.
[4.26]H. Movahedian, B. Sedighi, M. Sharif, wide-range single-ended CMOS track-and-hold circuit, IEICE Electronics Express,2007,4(12):400-405.
[4.27]何开全,谭开洲,李荣强,高性能模拟集成电路工艺技术,微电子学,2004,34(4)：398-401.
[4.28]R. H. Allen, Complex Analog Filters Obtained from Shifted LowPass Prototypes, M. A. Sc. thesis, University of Toronto,1985.
[4.29]Aziz, P. M. Sorensen, V. D. Spiegel, An overview of sigma-delta converters, IEEE Signal Processing Magazine,1996:61-84.
[4.30]M. R. Miller, C. S. A. Petrie, A multibit sigma-delta ADC for multimode receivers, IEEE Journal of Solid-State Circuits,2003,38(3):475-482.
[4.31]P. Vorenkamp, R. Roovers, A 12-b.60-MSample/s cascaded folding and interpolating ADC, IEEE Journal of Solid-State Circuits,1997,32(12):1876-1886.
[4.32]J. C. Candy, G. C. Temes, Oversampling delta-sigma data converters, IEEE Press, New York,1992.
[4.33]刘益成,信号处理与过抽样转换器,电子工业出版社,1997.
[4.34]胡广书,数字信号处理,清华大学出版社,2003.
[4.35]J. C. Candy and 0. J. Benjamin, The structure of quantization noise from sigma-delta modulation. IEEE Trans.Commun., vol. COM-29, pp:1316-1323, Sept.1981.
[4.36]程佩青,数字滤波与快速傅立叶变换,清华大学出版社,1990年10月.
[4.37]郑君里等,信号与系统,高等教育出版社,1981年7月.
[4.38]R. M. Gray, Oversampled sigma-delta modulation, IEEE Trans. Commun., vol. COM-35:pp:481-489, May,1987.
[4.39]张应中等,数字通信工程基础,人民邮电出版社,1987.
[4.40]Chu. S and Burrus. C. Multirate filter designs using comb filters[J]. IEEE Trans, on Circuits and Systems,1984, CAS-31,913-924.
[4.41]R. M. Gray, Spectral analysis of quantization noise in a single-loop sigma-delta modulation with dc input. IEEE Trans. Commun., vol. COM-37: 956-968. June 1989.
[4.42]R. M. Gray, W. Chou and P. W. Wong, Quantization noise in a single-loop sigma-delta modulation with sinusoidal input. IEEE Trans. Commun., vol. COM-37:956-968.1990.
[4.43]P. R. Gray, P. J. Hurst, Analysis and design of analog integrated circuits, New York:John Wiley & Sons, Inc.2001:849-850.
[4.44]Jebalia M, Rebai C, Le Gai B, et al. Optimized decimation filter architecture for 5th order sigma delta converter in GSM/UMTS/Wi-max radio receiver[C]. //International Conference on Signals Circuits and Systems. Monatir: CIETACOM Res. Lab,2008:1-6.
[4.45]Kirschenbaum H. F, De La Plaza. A. Sigma delta based receiver[C].//IEEE Argentine School of Micro-Nonaelectronics, Technology and Applications. Buenos Aires,2008:99-102.
[4.46]Laulainen. E., Kosunen. M., Koskinen. L., et al, Decimation filter for alow-power sensor-interface system[C].//IEEE Norchip, Aalborg,2007:1-4.
[4.47]Candy J, and Temes G. Oversampling Delta-Sigma Data Converters[M]. New York, NY:IEEE Press,1992:1-10.
[4.48]Shahein A, Becher M, Lotze N, et al. Optimized scheme for power-of-two coefficient approximation for low power decimation filters in sigma delta ADCs[C].//51st Midwest Symposium on Circuits and Systems. Knoxvile: Eng.IMTEK Univ. of Freiburg,2008:1548-3746.
[4.49]Hsieh C M, Chiu H W. Sigma Delta Modulator Design Automation[C].//IEEE International Conference on Communications, Circuits and Systems. Kokura: Nat. Taipei Univ. of Techno., Taipei,2007:1034-1038.
[4.50]Khalid H, Shailesh B, Stephen C. Design and Implementation of a Decimation Filter For High Performance Audio Applications [J]. IEEE International Symposium on Circuits and Systems,2007,32(2):812-815.
[4.51]Shahana T K, James R K, Jose. B. R., et al. Polyphase Implementatio of Non-recursive Comb Decimators forSigma-Delta A/D Converters[C].//IEEE Conference on Electron Devices and Solid-Stage Circuits. Tainan,2007: 825-828.
[4.52]Dolecek G J, Mitra S K. On Design of CIC Decimation Filter with Improved Response[C].//3rd International Symposium on Communications, Control and Signal Processing. St Julians:Inst. INAOE,2008:1072-1076.
[4.53]Zhang Y Y, Jiang Y F. Noise shaping sigma delta modulation techniques and models simulation[C].//International Conferences on Solid-State and Integrated Circuit Technology. Shanghai:North China Univ. of Technol., 2006:23-26.
[4.54]Suarez Penaloza M L, Calenta V, Baudoin G, et al. Study of modified Polar Sigma-Delta transmitter architecture for multi-radio applications[C]. //European Conference on Wireless Technology. Amsterdam:ESYCOM, Univ. Paris-Est, Noise-le-Grand,2008:222-225.
[4.55]Huang R M, Lotze N, Manoli Y. On Design a High Speed Sigma Delta DAC Modulator for a Digital Communication Transceiver on Chip[C]. //EUROMICRO Conference on Digital System Design Architectures, Methods and Tools. Parma:Eng. Univ. of Freiburg,2008:53-60.
[4.56]Rebeschini M. Delta Sigma Data Converters:Theory, Design, and Simulation[M]. New York, NY:IEEE Press,1996,32-60.
[4.57]M. Keskin, U. Moon, G. C. Temes. A 1-V 10-MHz clock-rate 13-bit CMOS modulator using unity-gain-reset opamps. IEEE J. Solid-State Circuits,2002, 38:817;
[4.58]R. E. Crochiere, L.R. Rabiner. Interpolation and decimation of digital signals-a tutorial review. Proc. IEEE,1981,69:300.
[4.59]S.chu, C. S. Burrus. Multirate filter designs using comb filters. IEEE tran. Ckt. And Sys.1984, CAS-31:913;
[4.60]S. Park. Multistage decimation filter design technique for high-resolution sigma-delta A/D converters. IEEE Trans. Instr. Measurement,1992,41:863;
[4.61]裴昌幸,刘乃安,刘彦明.高阶滤波器最佳设计与实现[J].西安电子科技大学学报,1996,23(2)：12-18.Pei Changxing, Liu Naian, Liu Yanming. The best design and realization of high-order filters[J]. Journal of Xidian University,1996,23(2):12-18.
[4.62]Xihuitl J, Kumar A, Bayoumi M. Low complexity Decimation filters for Multi-standard Digital Receivers[J]. IEEE International Symposium on Circuits and Systems,2005,1:552-555.
[4.63]Laulainen. E., Kosunen. M., Koskinen. L., et al, Decimation filter for alow-power sensor-interface system[C].//IEEE Norchip, Aalborg,2007:1-4.
[4.64]Shahein A, Becher M, Lotze N, et al. Optimized scheme for power-of-two coefficient approximation for low power decimation filters in sigma delta ADCs[C].//51st Midwest Symposium on Circuits and Systems. Knoxvile: Eng.IMTEK Univ. of Freiburg,2008:1548-3746.
[4.65]Jebalia M, Rebai C, Le Gai B, et al. Optimized decimation filter architecture for 5th order sigma delta converter in GSM/UMTS/Wi-max radio receiver[C]. //International Conference on Signals Circuits and Systems. Monatir: CIETACOM Res. Lab,2008:1-6.
[4.66]Xu Nini, Hou Zhengxin. All Phase Half Band Filter and Its Application. Journal of Tianjin University,2005,38(3):7-13.
[4.67]何开全,谭开洲,李荣强,高性能模拟集成电路工艺技术,微电子学,2004,34(4)：398-401
[4.68]王志功,集成电路设计与九天EDA工具应用,东南大学出版社,2004.
[4.69]C. Saint, J. Saint,集成电路版图设计[影印版],清华大学出版社,2004.
[4.70]王燕,张莉,集成电路器件电子学(第三版),电子工业出版社,2004.
[4.71]石春琦,LVS版图验证方法的研究,电子器件,2002,25(2)：165-169.
[4.72]蒋安平,超大规模集成电路测试,电子工业出版社,2005：100-310.
[4.73]Oppenheim A and Schafer R. W. Discrete-Time Signal Processing[M]. New York, Prentice-Hall,1989,23.
[5.1]X. P. Li, and M. Ismail, Multi-standard CMOS Wireless Receivers:Analysis and Design. New York:Kluwer Academic Publisher,2002.
[5.2]I. Galton, Delta-Sigma Data Conversion in Wireless Transceivers. IEEE J. Solid-State Circuits,2002,37:302.
[5.3]Horn R. and Demian P., Cellular and WLAN Convergence. Wireless Broadband Forum, Cambridge, UK,2002.
[5.4]L. B. Yao, M. Steyaert W. Sansen. A 1-V,1-MS/s,88-dB Sigma-Delta Modulator in 0.13-μm Digital CMOS Technology. Symposium on VLSI Circuits Digest of Technical Papers,2005,4:180.
[5.5]Steven R. Norsworthy, Richard Schreier, Gabor C. Temes. Delta-Sigma Data Converters:Theory, Design, and Simulations. New York:John Wiley&Sons, 1990.
[5.6]T. Christen, T. Burger, Huang Qiuting. A 0.13nm CMOS EDGE/UMTS/ WLAN Tri-Mode △∑ADC with -92dB THD. IEEE International Solid-State Circuits Conference,2007,240:242.
[5.7]B. R. Jose, M. P, J. Mathew, D. K. Paradhan. Wideband Low-Distortion Sigma-Delta ADC for WLAN. IEEE Information, Communication & Signal Processing,2007,10:1.
[5.8]A. Rusu, D. R. de Llers Gonzalez, M. Ismail, et al. The design of a Low-Distortion Sigma-Delta ADC for WLAN Standards. IEEE Signals, Circuits and systems,2005,1:151.
[5.9]M. Keskin, U. Moon, G. C. Temes. A 1-V 10-MHz clock-rate 13-bit CMOS modulator using unity-gain-reset opamps. IEEE J. Solid-State Circuits,2002, 38:817.
[5.10]T. B. Cho and P. R. Gray. A 10 b,20 Msample/s,35mW pipeline A/D converter. IEEE J. Solid-State Circuits,1995,30:166.
[5.11]O. Nys, R. Henderson, E. Dijkstra. Low power high resolution A/D converters. Proc.38th Midwest Symp. Circuits and Systems, Rio de Janeiro, Brazi,1 1995,2:734.
[5.12]F. Maloberti, F. Francesconi, P. Malcovati, et al. Design considerations on low-voltage low-power data converters. IEEE Trans. Circuits Syst.I,1995:42: 853.
[5.13]L. E. Larson, T. Cataltepe, G. C. Temes. Multibit over-sampled sigma-delta A/D convertor with digital error correction. IEEE, Electron. Lett.,1988: 24(16):1051.
[5.14]Zhu Zhangming, Li Yani, Yang Yintang. An embedded 1.8V 10bit 120MS/s CMOS Current Steering Digital-to-Analog Converter IP Core. Journal of Semiconductors,2008,29(3):588(in Chinese)[朱樟明,李亚妮,杨银堂.一种1.8V 10位120MS/s CMOS电流舵D/A转换器IP核.半导体学报,2008,29(3)：588].
[5.15]O. Nys, R. Henderson. An analysis of dynamic element matching techniques in sigma-delta modulation. Proc. CICC'94, San Diego, CA,1994,1:519.
[5.16]B. H. Leung, S. Sutarja. Multibit △∑ A/D converter incorporating a novel class of dynamic element matching techniques. IEEE Trans.Circuits Syst. II, 1992,39:35.
[5.17]L. R. Carley. A noise shaping coder topology for 15+bit converters. IEEE J. Solid-state Circuits,1989:24:267.
[5.18]Dai Lan, Zhou Yumei, Hu Xiaoyu, et al. Implementation of a Digital Calibration Algorithm for Pipelined Analog-to-Digital Converters. Journal of Semiconductors,2008,29(5):993(in Chinese)[戴澜,周玉梅,胡晓宇等.一种流水线ADC数字基准算法实现.半导体学报,2008,29(5)：993]
[5.19]S. Brigati, F. Francesconi, P. Malcovai, et al, Modeling sigma-delta modulator non-idealities in SIMULINK(R). Proc. IEEE International Symposium on Circuits and Systems,2002,2:384.
[5.20]P. Malcovati. Behavioral modeling of switched capacitor sigma-delta modul-ators. IEEE Trans. Circuits Syst. II,2003,50(3):352.
[5.21]L. A. Williams, B. A. Wooley, Third-order cascade sigma-delta modulators, IEEE International Solid-State Circuits Conference,1991:489-498.
[5.22]O. Nys, R. K. Henderson. A 19-Bit Low-Power Multibit Sigma-Delta ADC Based on Data Weighted Averaging. IEEE J. Solid-State Circuits,1997,7: 933.
[1.2]刘益成,罗维炳。信号处理与过采样转换器,电子工业出版社,1997.
[1.3]G. E. Moore, No exponential is forever but forever can be delayed, IEEE International Solid-State Circuits Conference,2003,1:20-23.
[1.4]K. Poulton, A 4GSamples/s 8b ADC in 0.35um CMOS, IEEE International Solid-State Circuits Conference,2002:166-167.
[1.5]H. Chen, B. Song, K. Bacrania, A 14-b 20-MSamples/s CMOS pipelined ADC, IEEE Journal of Solid-State Circuits,2001,36:997-1001.
[1.6]H. Pan, A 3.3-V 12-b 50-MS/s A/D converter in 0.6um CMOS with over 80-dB SFDR, IEEE Journal of Solid-State Circuits,2000,35:1769-1783.
[1.7]J. C. Candy, G. C. Temes, Oversampling delta-sigma data converters, IEEE Press, New York,1992.
[1.8]R. Norsworthy, R. Schreier, G. C. Temes, Delta-sigma data converters, IEEE Press, Piscataway, NJ,1997.
[1.9]Aziz, P. M. Sorensen, V. D. Spiegel, An overview of sigma-delta converters, IEEE Signal Processing Magazine,1996:61-84.
[1.10]R. Veldhoven, A tri-mode continuous time sigma delta modulator with switched-capacitor DAC for a GSM-EDGE/CDMA2000/UMTS receiver, IEEE International Solid-State Circuits Conference,2003:60-61.
[1.11]T. Kuo, K. Chen, H. Yeng, A wideband CMOS sigma-delta modulator with incremental data weighted averaging, IEEE Journal of Solid-State Circuits, 2002,37:11-17.
[1.12]C. C. Cutler, Transmission system employing quantization[P]. U S Patent, No 2927962. March 8,1960.
[1.13]F. D. Jager, Delta modulation-a method of PCM transmission using the one unit code,Philips Res.Rep.,1952,7:442-466.
[1.14]H. Inose, Y.Yasuda, J.Murakami, A telemetering system by code modulation △-∑ modulation, IRE Trans.Space Electron.Telemetry,1962,8:204-209.
[1.15]G. R. Ritchie, Higher order interpolation analog to digital converters, Ph.D. Dissertation, University of Pennsylvania,1977.
[1.16]J. C. Candy, A use of double integration in sigma-delta modulation, IEEE transactions on communications,1985:249-258.
[1.17]T. Hayashi, Y. Inabe, K. Uchimura, et al, A multistage delta-sigma modulator without double integration loop, IEEE International Solid-State Circuits Conference,1986,182-183.
[1.18]W. L. Lee, A novel higher order interpolative modulator topology for high resolution oversampling, Master thesis, MIT, Cambridge, MA,987.
[1.19]L. E. Larson, T, Cataltepe, G. C.Temes, Multi-bit oversampled sigma-delta A/D converter with digital error correction, Electron.Lett.,1988:1051-1052.
[1.20]L. R. Carley, A noise-shaping coder topology for 15-Bit converters, IEEE Journal of Solid-State Circuits,1989,24:267-273.
[1.21]T. C. Leslie, B. Siggh, An improved sigma-delta modulator architecture, IEEE International Symposium on Circuits and Systems,1990,1:372-375.
[1.22]L. A. Williams II, B. A. Wooley, Third-order cascade sigma-delta modulators, IEEE Transactions on Circuits and Systems,1991,38(5):489-498.
[1.23]N. Bridgett, C. Lewis, Effect of initial conditions on limit cycle performance of second order sampled data sigma-delta modulator, Electron.Lett.,1990,26: 817-819.
[1.24]R. Ledzius, J. I. rwin, The basis and architecture for the reduction of tones in a sigma-delta DAC, IEEE Trans. Circuits and System-II:Analog and Digital Signal Proc.,1993,40(7):429-439.
[1.25]T. H. Kuo, S. Y. Lee, D.J. Lu,3.3 V mixed-mode IC design using switched-current techniques for speech applications, IEE Proceeding-Circuits, Devices and Systems,1997,144(6):367-374.
[1.26]R. Schreier, J. Lloyd, L. Singer, et al,A 50Mw bandpass sigma delta ADC with 333kHz BW and 90dB DR, International Solid-State Circuits Conference,2002:216-217.
[1.27]K. Nguyen, R. Adams, K. Sweetland, et al, A 106-dB SNR hybrid oversamp-ling analog-to-digital converter for digital audio, IEEE Journal of Solid-State Circuits,40(12):2408-2415.
[1.28]R. D. Rio, J. M. Rosa, B. P. Verdu, et al, highly linear 2.5-V CMOS ∑△ modulator for ADSL, IEEE Transactions on Circuits and Systems,2004, 51:47-62.
[1.29]R. Gaggl, A. Wiesbauer, G. Fritz, et al, A 85-dB dynamic range multibit delta-sigma ADC for ADSL-CO applications in 0.18-μm CMOS, IEEE Journal of Solid-State Circuits,2003,38:1105-1114.
[1.30]苟曦,李怡然,陈建球,等,一个0.9V电源电压16位300μW音频ΣΔ调制器,复旦学报(自然科学版),2008,47(6)：763-768.
[1.31]Z. Li, H. Z. Yang, A 3V 5.88mW 13b 400kHz sigma-delta modulator with 84dB dynamic range,半导体学报,2008,29(11)：2232-2237.
[1.32]M. R. Miller, C. S. A. Petrie, A multibit sigma-delta ADC for multimode receivers, IEEE Journal of Solid-State Circuits,2003,38(3):475-482.
[1.33]Y. Q. Yang, T. Sculley, J. Abraham, A single die 124dB stereo audio delta sigma ADC with 111dB THD,33rd European Solid State Circuits Conference, 2007:252-255.
[1.34]K. Vleugels, S. Rabii, B. Wooley, A 2.5-V sigma-delta modulator for broadband communications applications, IEEE Journal of Solid-State Circuits, 2001,36:1887-1899.
[1.35]J. Y. Wu, Z. Y. Zhang, R. Subramoniam, et.al, A 107.4dB SNR mulit-bit sigma delta ADC with 1-PPM THD at -0.12dB from full scale input, IEEE Journal of Solid-State Circuits,2009,44(11):3060-3066.
[1.36]Y. Q. Yang, T. Sculley, J. Abraham, A 128dB dynamic range 1kHz bandwidth stereo ADC with 114dB THD, very large scale integration,2007.VLSI-SoC 2007. IFIP International Conference on 15-17:248-251.
[1.37]Z. F. Wang, Z. H Li, A Charge delta-sigma modulator for differential-capacitance sensors,传感技术学报,2006,19(5)：2252-2254.
[1.38]J. M. Rose, S. Escalera, B. P. Verdu, et al, A CMOS 110-dB@40-kS/s programmable-gain chopper-stabilized third-order 2-1 cascade sigma-delta modulator for low-power high-linearity automotive sensor ASICs, IEEE Journal of Solid-State Circuits,2005,40(11):2246-2264.
[1.39]Y. Q. Yang, T. Sculley, J. Abraham, A single die 124dB stereo audio delta sigma ADC with 111dB THD,33rd European Solid State Circuits Conference, 2007:252-255.
[1.40]J. Y. Wu, Z. Y. Zhang, R. Subramoniam, et.al, A 107.4dB SNR mulit-bit sigma delta ADC with 1-PPM THD at -0.12dB from full scale input, IEEE Journal of Solid-State Circuits,2009,44(11):3060-3066.
[1.41]I. Fujimori, L. Longo, A. Hairapetian, et al, A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8x oversampling Ratio, IEEE Journal of Solid-State Circuits,2000, 35:1820-1828.
[1.42]R. D. Rio, J. M. Rosa, B. P. Verdu, et al, highly linear2.5-V CMOS modulator for ADSL, IEEE Transactions on Circuits and Systems,2004, 51:47-62.
[1.43]K. Vleugels, S. Rabii, B. Wooley, A 2.5-V sigma-delta modulator for broadband communications applications, IEEE Journal of Solid-State Circuits, 2001,36:1887-1899.
[1.44]K. Nguyen, R. Adams, K. Sweetland, et al, A 106-dB SNR hybrid oversampling analog-to-digital converter for digital audio, IEEE Journal of Solid-State Circuits,40(12):2408-2415.
[1.45]Rebeschini M. Delta Sigma Data Converters:Theory, Design, and Simulation[M]. New York, NY:IEEE Press,1996,32-60.
[1.46]C. Ying, R. T. long, H. Z. Hang, A 16bit 96kHz chopper-stabilized sigma-delta ADC,半导体学报,2007,28(8)：1204-1209.
[1.47]Z. Li, H. Z. Yang, A 3V 5.88mW 13b 400kHz sigma-delta modulator with 84dB dynamic range,半导体学报,2008,29(11)：2232-2237.
[1.48]褚炜路,戎蒙恬,李萍,等,二阶多比特sigma-delta ADC中的自适应量化算法,上海交通大学学报,2008,42(2)：308-311.
[1.49]马绍宇,韩雁,黄小伟,等,一种高性能、低功耗音频ΣΔ调制器,半导体学报,2008,29(10)：2050-2056.
[1.50]W. Ou, X. B. Wu, High-consistency behavior modeling of a switched-capacitor sigma-delta modulator in simulink,半导体学报,2008,29(11):2209-2217.
[1.51]X. Zhang, D. S. Yu, S. M. Sheng, et al, A behavioral simulation method and an optimized design of sigma-delta ADC,北京大学学报(自然科学版),2009,45(2)：209-214.
[1.52]Z. F. Wang, Z. H Li, A Charge delta-sigma modulator for differential-capacitance sensors,传感技术学报,2006,19(5)：2252-2254.
[1.53]杨骁,陈贵灿,程军,等,一种新型级联ΣΔ调制器系统结构,西安交通大学学报,2008,42(12)：1541-1545.
[1.54]L. Chen, Y. F. Zhao, D. Y. Gao, et al, A 16 bit stereo audio ∑ △ A/D converter,半导体学报,2006,27(7)：1183-1188.
[1.55]陈雷,高精度ΣΔADC的研究,西北工业大学博士学位论文,2006.
[1.56]丁晓燕,16-bit 100ksps sigma-delta模数转换中数字滤波器的设计,西安电子科技大学硕士学位论文,2009.
[1.57]王其超,一种16位音频sigma-delta模数转换器的研究与设计,西安电子 科技大学硕士学位论文,2009.
[1.58]李梁,李儒章,张俊安,等,一种适合Σ-△A/D转换器的FIR数字滤波器,微电子学,2006,36(3)：340-343.
[2.1]M. P. Flynn, B. Sheahan, A 400MSample/s 6b COMS folding and interp-olating ADC., IEEE International Solid-State Circuits Conference,1998: 150-151.
[2.2]P. Vorenkamp, R. Roovers, A 12-b.60-MSample/s cascaded folding and interpolating ADC, IEEE Journal of Solid-State Circuits,1997,32(12): 1876-1886.
[2.3]K. Bult, A. Bauchwald, An embedded 240-mW 10-b 50MS/S CMOS ADC in 1-mm2., IEEE Journal of Solid-State Circuits,1997,32(12):1887-1895.
[2.4]H. Kimura, A. Matsuzawa, T. Natamura et al., A 10-b 300-MHZ interpolated parallel A/D converter, IEEE Journal of Solid-State Circuits,1993, SC-28(4):438-446.
[2.5]J. V. Valburg, R J. van de Plassche, An 8-b 650-MHz folding ADC, IEEE Journal of Solid-State Circuits,1992,SC-27(12):1662-1666.
[2.6]T. Wakimoto, Y. AKazawa, S. Kanaka, Si bipolar 2Gs/s 6b flash A/D converter, IEEE Journal of Solid-State Circuits,1988,SC-23(6):1345-1350.
[2.7]K. Poulton, K. L. Knudsen, J. J. Corcoan, et al, A 6-b.4 GBa/s GaAs HBT ADC, IEEE Journal of Solid-State Circuits,1995,30(10):1109-1118.
[2.8]C. Hammerschmied, Q. Huang, A MOSFET-only 10b.200ksample/s A/D converter capable of 12b untrimmed linearity, IEEE International Solid-State Circuits Conference,1997:132-133.
[2.9]S. Ramet, A 13bit 160 kHz differential analog to digital converter, IEEE International Solid-State Circuits Conference,1989:20-21.
[2.10]H. S. Lee, D. A. Hodges, P. R. Gray, A self-calibrating 15 bit CMOS A/D conterter, IEEE Journal of Solid-State Circuits,1994,SC-19(6):813-819.
[2.11]J. Yuan, C. Swensson, A 10-b 5-MS/s successive approximation ADC cell used in a 70MS/s ADC array in 1.2μm CMOS, IEEE Journal of Solid-State Circuits,1994,29. (8):866-872.
[2.12]M. Yotsuyanagi, A. Yakawa, K. Hino-oka, et al, A 12 bit 5μsec CMOS recursive ADC with 25 mW power consumption, IEEE International Solid-State Circuits Conference,1989:641-6496.
[2.13]A. Khagawa, M. Kokubo, T. Tsukada, et al, A 10b 3MSample/s CMOS cyclic ADC, IEEE International Solid-State Circuits Conference,1995:280-281.
[2.14]吴大正,信号与线性系统分析,高等教育出版社,2003.
[2.15]W. R. Bennett, Spectra of quantized signals, Bell System Technical Journal 1948,27:446-472.
[2.16]R. M. Gray, Quantization noise spectra, IEEE Transactions on Information Theory,1990,36:1220-1244.
[2.17]A. B. Sripad, D. L. Snyder, A necessary and sufficient condition for quantization errors to be uniform and white, IEEE Trans. Acoust., Speech, Signal Processing,1977, ASSP-25:442-448.
[2.18]B. Widrow, Statistical analysis of amplitude-quantized sample-data systems, Trans. AIEE-Part II:Applications and Industry,1960,79:555-568.
[2.19]R. V. Plassche, integrated analog-to-digital and digital-to-analog converters. Kluwer Academic Publishers,1994.
[2.20]刘益成,罗维炳。信号处理与过采样转换器,电子工业出版社,1997,
[2.21]J. C. Candy and 0. J. Benjamin, The structure of quantization noise from sigma-delta modulation. IEEE Trans.Commun., vol. COM-29, pp:1316-132-3, Sept.1981.
[3.1]程佩青,数字滤波与快速傅立叶变换,清华大学出版社,1990.
[3.2]郑君里等,信号与系统,高等教育出版社,1981.
[3.3]R. M. Gray, Oversampled sigma-delta modulation, IEEE Trans. Commun., vol. COM-35:pp:481-489, May,1987.
[3.4]D. Johns, K. Martin, Analog integrated circuit design, New York:Wiley, 1997.
[3.5]R. D. Rio, Reliable analysis of settling errors in SC integrators:application to △∑ modulators, Electron. Lett.,2000,36:503-504.
[3.6]Y. Geerts, M. S. J. Steyaert, W. Sansen, A high-performance multi-bit △∑ CMOS ADC, IEEE Journal of Solid-State Circuits,2000,35(12):1829-1840.D. Johns, K. Martin, Analog integrated circuit design, New York:Wiley, 1997.
[3.7]S. Rabii, B. A. Wooley, The design of low-voltage, low-power sigma-delta modulators, Norwell, MA:Kluwer,1999.
[3.8]F. Medeiro, Modeling opamp-induced harmonic distortion for switched-capacitor SD modulator design, IEEE Transactions on Circuits and Systems, 1994,5:445-448.
[3.9]S. R. Northworthy, R. Schreier, G. C. Temes, Delta-sigma data converters, Piscataway, NJ:IEEE Press,1997.
[3.10]B. E. Boser, B. A. Wooley, The design of sigma-delta modulation analog-to-digital converters, IEEE J. Solid-State Circuits,1988,22(12):1298-1308.
[3.11]J. Shieh, M. Patil, A. J. Sheu, Measurement and analysis of charge injection in MOS analog switches, IEEE Journal of Solid-State Circuits,1987, SSC-22(4):277-281.
[3.12]R. M. Gray, Spectral analysis of quantization noise in a single-loop sigma-delta modulation with dc input. IEEE Trans. Commun., vol. COM-37: 956-968. June 1989.
[3.13]P. Malcovati, S. Brigati, F. Francesconi, et al, Behavioral modeling of switched-capacitor sigma delta modulators, IEEE Transactions on Circuits and Systems,2003,50 (3):352-2364.
[3.14]T. Ritoniemi, T. Karema, H. Tenhunen, Design of stable high order 1-bit sigma-delta modulators, IEEE International Solid-State Circuits Conference, 1990,4:3267-3270.
[3.15]R. Schreier, G. C. Temes, Understanding delta-sigma data converters, Piscata-way, NJ:IEEE Press,2005.
[3.16]J. C. Candy, G. C. Temes, Oversampling delta-sigma data converters theory, design and simulation, IEEE Press, Piscataway, NJ (1992).
[3.17]J. G. Kenney, L. R. Carley, Design of multibit noise-shaping data converters, Analog Int. Circuits Signal Processing Journal,1993,3:259-272.
[3.18]M. Rizzi, Efficiency of simulation tools in designing sigma-delta ADC, AEU, 2006,60 (4).
[3.19]S. R. Norsworthy, R. Schreier, and G. C. Temes, Delta-Sigma Data Converters, Theory, Design, and Simulation, IEEE Press,1997.
[3.20]R. H. Allen, Complex Analog Filters Obtained from Shifted LowPass Prototypes, M. A. Sc. thesis, University of Toronto,1985.
[3.21]R. M. Gray, W. Chou and P. W. Wong, Quantization noise in a single-loop sigma-delta modulation with sinusoidal input. IEEE Trans. Commun., vol. COM-37:956-968.1990.
[3.22]R. M. Gray, Quantization noise spectra. IEEE Trans Information Theory, vol. IT-36:1220-1244.1990.
[3.23]R. Schreier and W. M. Snelgrove, Bandpass Sigma-Delta Modulation. Electron. Lett., vol.25, no.23, pp:1560-1561, November 9,1989.
[3.24]K. C. H. Chao, S. Nadeem, W. L. Lee, et al, A higher order topology for inter-polative modulator for oversampling A/D converter, IEEE Transactions on Circuits and Systems,1990,37(3):309-318.
[3.25]W. L. Lee, A novel higher order interpolative modulator topology for high resolution oversampling A/D converters, Master's Thesis, Massachusetts Institute of Technology, Cambridge, MA. June 1987.
[4.1]B. E. Boser, B. A. Wooley. The design of sigma-delta modulation analog-to-digital converters. IEEE J. Solid-State Circuits,1988, SC-23:1298;
[4.2]G. Paul, R. Meyer, analysis and design of analog integrated circuits, John Wiley and Sons, New York,1993.
[4.3]J. C. Candy, G. C. Temes. Oversampling methods for A/D and D/A conversion. New York, IEEE Press,1992.
[4.4]J. Wieser, R. Reed, Current source frequency compensation for a CMOS amplifier, US Patent No 4315223, November 1984.
[4.5]R. W. Adams, P. F. Ferguson, A. Ganesan, et al. Theory and practical imple-mentation of a fifth-order sigma-delta A/D converter. J. Audio Eng. Soc., 1991,39:515.
[4.6]T. Ritoniemi, T. Karema, H. Tenhumen. The design of stable high order 1-bit sigma-delta modulators. Proc.1990 IEEE Int. Symp. Circuits Sys.,1990,4: 3267.
[4.7]A. Feldman, High-speed, low-power sigma-delta modulators for RF base-band applications, Ph.D. dissertation, University of California at Berkeley, 1997.
[4.8]R. Schreier, G. C. Temes. Understanding Delta-Sigma Data Converters, John Wiley & Sons. New York,2004.
[4.9]Steven R. Norsworthy, Richard Schreier, Gabor C. Temes. Delta-Sigma Data Converters:Theory, Design, and Simulations. New York:John Wiley&Sons, 1990.
[4.10]R. Schreier. An empirical study of high-order single-bit delta-sigma modulators. IEEE Trans. Circuits Sys.,1987,40:459.
[4.11]M. Dessouky, A. Kaiser, Input switch configuration for rail-to-rail operation of switched opamp circuits, Electronics Letters,1999,35 (1):8-10.
[4.12]A. R. Feldman, "High-speed, Low-power Sigma-Delta Modulators for RF Base-band Channel Applications", PhD Dissertation, University of Californ- ia, Berkeley,1997.
[4.13]M. Dessouky, A. Kaiser, Very low-voltage digital-audio ∑-△ modulator with 88-dB dynamic range using local switch bootstrapping, IEEE Journal of Solid-State Circuits,2001,36 (3):349-355.
[4.14]Y. Geerts, M. S. J. Steyaert, and W. Sansen, "A High-performance Multi-bit? ∑△ CMOS ADC", IEEE Journal of Solid-State Circuits, Vol.35, pp.1829-1840, Dec.2000.
[4.15]T. Ritoniemi, E. Pajarre, S. Ingalsuo, et al., "A Stereo 97dB Audio Sigma-Delta ADC", ISSCC Digest of Technical Papers, pp.198-199, Feb. 1994.
[4.16]C. D. Thomposon and S. R. Bernadas, "A Digitally-corrected 20b Delta-Sigma Modulator", ISSCC Digest of Technical Papers, pp.194-195, Feb.1994.
[4.17]T. Ritoniemi, T. Karema, H. Tenhunen, Design of stable high order 1-bit sigma-delta modulators, IEEE International Solid-State Circuits Conference, 1990,4:3267-3270.
[4.18]R. Schreier, G. C. Temes, Understanding delta-sigma data converters, Pis-cataway, NJ:IEEE Press,2005.
[4.19]K. C. H. Chao, S. Nadeem, W. L. Lee, et al, A higher order topology for interpolative modulator for oversampling A/D converter, IEEE Transactions on Circuits and Systems,1990,37(3):309-318.
[4.20]Y. Geerts, M. S. J. Steyaert, and W. Sansen, "A High-performance Multi-bit ∑-△ CMOS ADC", IEEE Journal of Solid-State Circuits, Vol.35, pp.1829-1840, Dec.2000.
[4.21]B. Razavi, "Principles of Data Conversion System Design", IEEE Circuits and Systems Society, ISBN 0-7803-1093-4,1994.
[4.22]M. Waltari, K. Halonen, Bootstrapped switch without bulk effect in standard CMOS technology, Electronics Letters,2002,38 (12):555-557.
[4.23]T. S. Lee, C. C. Lu, Design techniques for low-voltage high-speed pseudo-differential CMOS track-and-hold circuit with low hold pedestal, Electronics Letters,2004,40 (9):519-520.
[4.24]T. S. Lee, C. C. Lu, A 1.5V 50-MHz CMOS pseudo-differential sample-and-hold circuit with low hold pedestal, IEEE Transaction on Circuit and Systems,2005,52 (9):1752-1757.
[4.25]C. J. B. Fayomi, G. W. Roberts, M. Sawan, low-voltage CMOS analog bootstrapped switch for sample-and-hold circuit:design and chip characterization[C]//Proceedings of IEEE International Symposium on Circuits and Systems,2005:2200-2203.
[4.26]H. Movahedian, B. Sedighi, M. Sharif, wide-range single-ended CMOS track-and-hold circuit, IEICE Electronics Express,2007,4(12):400-405.
[4.27]何开全,谭开洲,李荣强,高性能模拟集成电路工艺技术,微电子学,2004,34(4)：398-401.
[4.28]R. H. Allen, Complex Analog Filters Obtained from Shifted LowPass Prototypes, M. A. Sc. thesis, University of Toronto,1985.
[4.29]Aziz, P. M. Sorensen, V. D. Spiegel, An overview of sigma-delta converters, IEEE Signal Processing Magazine,1996:61-84.
[4.30]M. R. Miller, C. S. A. Petrie, A multibit sigma-delta ADC for multimode receivers, IEEE Journal of Solid-State Circuits,2003,38(3):475-482.
[4.31]P. Vorenkamp, R. Roovers, A 12-b.60-MSample/s cascaded folding and interpolating ADC, IEEE Journal of Solid-State Circuits,1997,32(12):1876-1886.
[4.32]J. C. Candy, G. C. Temes, Oversampling delta-sigma data converters, IEEE Press, New York,1992.
[4.33]刘益成,信号处理与过抽样转换器,电子工业出版社,1997.
[4.34]胡广书,数字信号处理,清华大学出版社,2003.
[4.35]J. C. Candy and 0. J. Benjamin, The structure of quantization noise from sigma-delta modulation. IEEE Trans.Commun., vol. COM-29, pp:1316-1323, Sept.1981.
[4.36]程佩青,数字滤波与快速傅立叶变换,清华大学出版社,1990年10月.
[4.37]郑君里等,信号与系统,高等教育出版社,1981年7月.
[4.38]R. M. Gray, Oversampled sigma-delta modulation, IEEE Trans. Commun., vol. COM-35:pp:481-489, May,1987.
[4.39]张应中等,数字通信工程基础,人民邮电出版社,1987.
[4.40]Chu. S and Burrus. C. Multirate filter designs using comb filters[J]. IEEE Trans, on Circuits and Systems,1984, CAS-31,913-924.
[4.41]R. M. Gray, Spectral analysis of quantization noise in a single-loop sigma-delta modulation with dc input. IEEE Trans. Commun., vol. COM-37: 956-968. June 1989.
[4.42]R. M. Gray, W. Chou and P. W. Wong, Quantization noise in a single-loop sigma-delta modulation with sinusoidal input. IEEE Trans. Commun., vol. COM-37:956-968.1990.
[4.43]P. R. Gray, P. J. Hurst, Analysis and design of analog integrated circuits, New York:John Wiley & Sons, Inc.2001:849-850.
[4.44]Jebalia M, Rebai C, Le Gai B, et al. Optimized decimation filter architecture for 5th order sigma delta converter in GSM/UMTS/Wi-max radio receiver[C]. //International Conference on Signals Circuits and Systems. Monatir: CIETACOM Res. Lab,2008:1-6.
[4.45]Kirschenbaum H. F, De La Plaza. A. Sigma delta based receiver[C].//IEEE Argentine School of Micro-Nonaelectronics, Technology and Applications. Buenos Aires,2008:99-102.
[4.46]Laulainen. E., Kosunen. M., Koskinen. L., et al, Decimation filter for alow-power sensor-interface system[C].//IEEE Norchip, Aalborg,2007:1-4.
[4.47]Candy J, and Temes G. Oversampling Delta-Sigma Data Converters[M]. New York, NY:IEEE Press,1992:1-10.
[4.48]Shahein A, Becher M, Lotze N, et al. Optimized scheme for power-of-two coefficient approximation for low power decimation filters in sigma delta ADCs[C].//51st Midwest Symposium on Circuits and Systems. Knoxvile: Eng.IMTEK Univ. of Freiburg,2008:1548-3746.
[4.49]Hsieh C M, Chiu H W. Sigma Delta Modulator Design Automation[C].//IEEE International Conference on Communications, Circuits and Systems. Kokura: Nat. Taipei Univ. of Techno., Taipei,2007:1034-1038.
[4.50]Khalid H, Shailesh B, Stephen C. Design and Implementation of a Decimation Filter For High Performance Audio Applications [J]. IEEE International Symposium on Circuits and Systems,2007,32(2):812-815.
[4.51]Shahana T K, James R K, Jose. B. R., et al. Polyphase Implementatio of Non-recursive Comb Decimators forSigma-Delta A/D Converters[C].//IEEE Conference on Electron Devices and Solid-Stage Circuits. Tainan,2007: 825-828.
[4.52]Dolecek G J, Mitra S K. On Design of CIC Decimation Filter with Improved Response[C].//3rd International Symposium on Communications, Control and Signal Processing. St Julians:Inst. INAOE,2008:1072-1076.
[4.53]Zhang Y Y, Jiang Y F. Noise shaping sigma delta modulation techniques and models simulation[C].//International Conferences on Solid-State and Integrated Circuit Technology. Shanghai:North China Univ. of Technol., 2006:23-26.
[4.54]Suarez Penaloza M L, Calenta V, Baudoin G, et al. Study of modified Polar Sigma-Delta transmitter architecture for multi-radio applications[C]. //European Conference on Wireless Technology. Amsterdam:ESYCOM, Univ. Paris-Est, Noise-le-Grand,2008:222-225.
[4.55]Huang R M, Lotze N, Manoli Y. On Design a High Speed Sigma Delta DAC Modulator for a Digital Communication Transceiver on Chip[C]. //EUROMICRO Conference on Digital System Design Architectures, Methods and Tools. Parma:Eng. Univ. of Freiburg,2008:53-60.
[4.56]Rebeschini M. Delta Sigma Data Converters:Theory, Design, and Simulation[M]. New York, NY:IEEE Press,1996,32-60.
[4.57]M. Keskin, U. Moon, G. C. Temes. A 1-V 10-MHz clock-rate 13-bit CMOS modulator using unity-gain-reset opamps. IEEE J. Solid-State Circuits,2002, 38:817;
[4.58]R. E. Crochiere, L.R. Rabiner. Interpolation and decimation of digital signals-a tutorial review. Proc. IEEE,1981,69:300.
[4.59]S.chu, C. S. Burrus. Multirate filter designs using comb filters. IEEE tran. Ckt. And Sys.1984, CAS-31:913;
[4.60]S. Park. Multistage decimation filter design technique for high-resolution sigma-delta A/D converters. IEEE Trans. Instr. Measurement,1992,41:863;
[4.61]裴昌幸,刘乃安,刘彦明.高阶滤波器最佳设计与实现[J].西安电子科技大学学报,1996,23(2)：12-18.Pei Changxing, Liu Naian, Liu Yanming. The best design and realization of high-order filters[J]. Journal of Xidian University,1996,23(2):12-18.
[4.62]Xihuitl J, Kumar A, Bayoumi M. Low complexity Decimation filters for Multi-standard Digital Receivers[J]. IEEE International Symposium on Circuits and Systems,2005,1:552-555.
[4.63]Laulainen. E., Kosunen. M., Koskinen. L., et al, Decimation filter for alow-power sensor-interface system[C].//IEEE Norchip, Aalborg,2007:1-4.
[4.64]Shahein A, Becher M, Lotze N, et al. Optimized scheme for power-of-two coefficient approximation for low power decimation filters in sigma delta ADCs[C].//51st Midwest Symposium on Circuits and Systems. Knoxvile: Eng.IMTEK Univ. of Freiburg,2008:1548-3746.
[4.65]Jebalia M, Rebai C, Le Gai B, et al. Optimized decimation filter architecture for 5th order sigma delta converter in GSM/UMTS/Wi-max radio receiver[C]. //International Conference on Signals Circuits and Systems. Monatir: CIETACOM Res. Lab,2008:1-6.
[4.66]Xu Nini, Hou Zhengxin. All Phase Half Band Filter and Its Application. Journal of Tianjin University,2005,38(3):7-13.
[4.67]何开全,谭开洲,李荣强,高性能模拟集成电路工艺技术,微电子学,2004,34(4)：398-401
[4.68]王志功,集成电路设计与九天EDA工具应用,东南大学出版社,2004.
[4.69]C. Saint, J. Saint,集成电路版图设计[影印版],清华大学出版社,2004.
[4.70]王燕,张莉,集成电路器件电子学(第三版),电子工业出版社,2004.
[4.71]石春琦,LVS版图验证方法的研究,电子器件,2002,25(2)：165-169.
[4.72]蒋安平,超大规模集成电路测试,电子工业出版社,2005：100-310.
[4.73]Oppenheim A and Schafer R. W. Discrete-Time Signal Processing[M]. New York, Prentice-Hall,1989,23.
[5.1]X. P. Li, and M. Ismail, Multi-standard CMOS Wireless Receivers:Analysis and Design. New York:Kluwer Academic Publisher,2002.
[5.2]I. Galton, Delta-Sigma Data Conversion in Wireless Transceivers. IEEE J. Solid-State Circuits,2002,37:302.
[5.3]Horn R. and Demian P., Cellular and WLAN Convergence. Wireless Broadband Forum, Cambridge, UK,2002.
[5.4]L. B. Yao, M. Steyaert W. Sansen. A 1-V,1-MS/s,88-dB Sigma-Delta Modulator in 0.13-μm Digital CMOS Technology. Symposium on VLSI Circuits Digest of Technical Papers,2005,4:180.
[5.5]Steven R. Norsworthy, Richard Schreier, Gabor C. Temes. Delta-Sigma Data Converters:Theory, Design, and Simulations. New York:John Wiley&Sons, 1990.
[5.6]T. Christen, T. Burger, Huang Qiuting. A 0.13nm CMOS EDGE/UMTS/ WLAN Tri-Mode △∑ADC with -92dB THD. IEEE International Solid-State Circuits Conference,2007,240:242.
[5.7]B. R. Jose, M. P, J. Mathew, D. K. Paradhan. Wideband Low-Distortion Sigma-Delta ADC for WLAN. IEEE Information, Communication & Signal Processing,2007,10:1.
[5.8]A. Rusu, D. R. de Llers Gonzalez, M. Ismail, et al. The design of a Low-Distortion Sigma-Delta ADC for WLAN Standards. IEEE Signals, Circuits and systems,2005,1:151.
[5.9]M. Keskin, U. Moon, G. C. Temes. A 1-V 10-MHz clock-rate 13-bit CMOS modulator using unity-gain-reset opamps. IEEE J. Solid-State Circuits,2002, 38:817.
[5.10]T. B. Cho and P. R. Gray. A 10 b,20 Msample/s,35mW pipeline A/D converter. IEEE J. Solid-State Circuits,1995,30:166.
[5.11]O. Nys, R. Henderson, E. Dijkstra. Low power high resolution A/D converters. Proc.38th Midwest Symp. Circuits and Systems, Rio de Janeiro, Brazi,1 1995,2:734.
[5.12]F. Maloberti, F. Francesconi, P. Malcovati, et al. Design considerations on low-voltage low-power data converters. IEEE Trans. Circuits Syst.I,1995:42: 853.
[5.13]L. E. Larson, T. Cataltepe, G. C. Temes. Multibit over-sampled sigma-delta A/D convertor with digital error correction. IEEE, Electron. Lett.,1988: 24(16):1051.
[5.14]Zhu Zhangming, Li Yani, Yang Yintang. An embedded 1.8V 10bit 120MS/s CMOS Current Steering Digital-to-Analog Converter IP Core. Journal of Semiconductors,2008,29(3):588(in Chinese)[朱樟明,李亚妮,杨银堂.一种1.8V 10位120MS/s CMOS电流舵D/A转换器IP核.半导体学报,2008,29(3)：588].
[5.15]O. Nys, R. Henderson. An analysis of dynamic element matching techniques in sigma-delta modulation. Proc. CICC'94, San Diego, CA,1994,1:519.
[5.16]B. H. Leung, S. Sutarja. Multibit △∑ A/D converter incorporating a novel class of dynamic element matching techniques. IEEE Trans.Circuits Syst. II, 1992,39:35.
[5.17]L. R. Carley. A noise shaping coder topology for 15+bit converters. IEEE J. Solid-state Circuits,1989:24:267.
[5.18]Dai Lan, Zhou Yumei, Hu Xiaoyu, et al. Implementation of a Digital Calibration Algorithm for Pipelined Analog-to-Digital Converters. Journal of Semiconductors,2008,29(5):993(in Chinese)[戴澜,周玉梅,胡晓宇等.一种流水线ADC数字基准算法实现.半导体学报,2008,29(5)：993]
[5.19]S. Brigati, F. Francesconi, P. Malcovai, et al, Modeling sigma-delta modulator non-idealities in SIMULINK(R). Proc. IEEE International Symposium on Circuits and Systems,2002,2:384.
[5.20]P. Malcovati. Behavioral modeling of switched capacitor sigma-delta modul-ators. IEEE Trans. Circuits Syst. II,2003,50(3):352.
[5.21]L. A. Williams, B. A. Wooley, Third-order cascade sigma-delta modulators, IEEE International Solid-State Circuits Conference,1991:489-498.
[5.22]O. Nys, R. K. Henderson. A 19-Bit Low-Power Multibit Sigma-Delta ADC Based on Data Weighted Averaging. IEEE J. Solid-State Circuits,1997,7: 933.