功率集成电路中高压ESD防护表面电流抑制模型与器件研究
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摘要
高压功率集成电路中静电放电（Electro-Static Discharge，ESD）防护，对于系统的稳定性和可靠性起到了至关重要的作用。研究功率集成电路ESD防护核心器件工作机理、提高高压ESD器件防护能力，对缩短功率集成电路设计周期和缩减设计成本具有十分重要的现实意义。然而，高压ESD防护器件在高压高电场的作用下易产生电流集中问题，使器件出现晶格温度恶化、泄漏电流增加、导通电阻增大，进而诱发软击穿、泄放能力低下、强回扫等问题。国内外众多学者提出包括深N阱纵向泄放LDMOS（Lateral Double-diffusion MOS）、槽栅LDMOS等一系列高压ESD防护器件的新结构以优化泄放路径、提高泄放能力。但高压器件ESD特性受工艺参数影响很大，所提出的优化手段在不同工艺间迁移时一致性很差，难以建立普适模型以指导ESD防护器件性能优化；此外，工艺的调整也将降低兼容性并带来制造成本的增加。
本文对功率集成电路中高压ESD防护器件表面电流集中问题进行研究，提出了一个模型和两项技术，即：提出表面电流抑制模型，并藉此发展了表面产生电流和表面输运电流的抑制技术。基于表面电流抑制模型和技术，对20V/40V外延工艺、190V SOI（Silicon On Insulator）工艺、700V单晶工艺条件下的不同器件进行了优化。此外，提出了LDMOS-SCR（Silicon Controlled Rectifer）器件二次回扫发生判据，并以此对其双回扫特性进行优化。本文主要有以下工作：
1、提出ESD防护器件表面电流抑制模型。基于器件体内温度分布及电-热模型，结合二次击穿发生条件，分析了表面电流集中造成的晶格温度升高以及与此伴生的热点（Hot Pot）问题；基于表面隧穿产生机理，分析了泄漏电流增加与表面电流集中的关系；阐述了表面电流集中导致的导通电阻增大，以及由此引起的ESD泄放能力降低问题。通过分析LDMOS器件在ESD应力下的泄放原理，研究并总结了表面电流集中的产生原因，提出抑制表面电流来提高器件ESD泄放能力的优化模型，并发展出抑制表面电流集中的两项技术：表面产生电流抑制技术和表面输运电流抑制技术。
2、基于表面电流抑制模型和技术，指导高压ESD防护器件性能优化。
（1）表面产生电流抑制技术，即通过抑制表面电场峰值，降低表面碰撞电离产生率；或通过增强寄生器件电流增益，降低维持同样泄放电流中雪崩倍增电流分量，以抑制表面局部产生电流。针对外延型20V/40V LDMOS，采用表面产生电流抑制技术，解决了由于隧穿和局部热熔丝导致的软击穿问题。实验证实，优化后20V LDMOS泄漏电流恒定在1nA甚至0.05nA，二次击穿电流由原始器件的2.2A上升至4.0A；优化后40V LDMOS泄漏电流恒定在约1nA，二次击穿电流由原始器件的1.17A提升至1.62A。讨论了LDMOS器件衬底寄生电阻与ESD特性的关系，通过增大衬底寄生电阻可增强寄生NPN电流增益，降低维持同样泄放电流中雪崩倍增电流分量，从而抑制表面产生电流。设计了具有分段隔离式P+注入的器件源-衬结构。实验证实，优化后器件二次击穿电流由1.0A提升至1.88A，将优化结构运用到芯片ESD防护中时，其HBM（Human Body Model）ESD能力由3KV上升至5.5KV。
（2）表面输运电流抑制技术，即通过增强纵向寄生器件电流能力，以纵向分流来抑制表面横向电流分量；或通过抑制纵向电场对自由载流子向表面吸附作用，来减小电流在表面的输运量。针对单晶型700V LDMOS器件出现的强回扫，通过设计新的体内纵向寄生器件VPNP，以分流来达到来抑制表面横向电流分量的目的，避免因寄生NPN开启导致强回扫发生。仿真结果显示，新结构电流泄放能力较原始器件提高约一倍。针对SOI基190V PDP（Plasma Display Panels）驱动芯片高压电源钳位，综合运用抑制表面电流的两项技术，采用深体泄放LIGBT（LateralInsulated Gate Bipolar Transistor）替代常规HV（High Voltage） Diode器件。其寄生PNP参与导电以降低雪崩倍增分量，从而抑制表面产生电流；其纵向电场将漂移区中的自由空穴推离器件表面，以抑制表面输运电流。实验证实，器件二次击穿电压由251V下降至217V，二次击穿电流则由0.39A上升至0.52A。将深体泄放LIGBT应用在PDP驱动IC中作为高压电源钳位，获得了8KV的HBM ESD能力。
3、研究并优化LDMOS-SCR器件双回扫特性。分析单晶型5V CMOS工艺条件下LDMOS-SCR器件双回扫现象产生机理，提出其二次回扫发生判据。通过降低二次回扫电压和电流，以减小器件在低ESD应力下的功耗，从而获得更强的ESD泄放能力。实验证实，优化后器件的二次击穿电流由0.57A上升至3.1A。
In integrated smart power application, the robustness of ESD (Electro-StaticDischarge) is one of determining factors for stability and reliability of the system. Withstronger ESD robustness, the design cycle and design cost of HV （high Voltage）power IC can be cut down. Therefore, it's very important and useful to study theworking mechanisms of the ESD protection devices and improve their protectionabilities. However, surface current integration easily occurs with high voltage and highelectric field, and worsens the lattice temperature, rises up leakage current, andincreases the discharge resistance. Therefore, A series of HV ESD protection deviceshave been designed and optimized at home and abroad to optimize the discharge path,and improve the discharge ability.
However, the characteristics of HV ESD protection devices are sensitive withmanufactory process parameters, and the optimize methods for one process may notavailable for other processes. It’s very hard to set up a universality theory for ESDrobustness optimization. Meanwhile, the modification of manufactory process willlower down the compatibility and increase the cost.
In this thesis, the surface current integration problem is studied, and the main workis as follows.
1. Surface current reduce model is proposed. The problems caused by surfacecurrent integration are studied. Based on the temperature distribution andelectro-thermal model, the lattice temperature increasing and the hot pot problem withsurface current integration are analyzed. Based on the surface tunnel model, therelationship between leakage current and surface current integration is discussed.Meanwhile, the discharge resistance increasing problem with surface current integrationis studied. By summarizing the mechanisms of surface current integration, twotechniques are proposed: surface generated current restrain technique and surfacetransport current restrain technique.
2. Based on the surface current reduce model and techniques, settle differentproblems for devices under ESD stress.
(1) Surface generated current restrain technique is realized by restraining thesurface electric field and surface impact ionization generation rate, or by enhance the current gain of the parasitic devices to reduce the avalanche multiple currentcomponent.
Based on the surface generated current restrain technique, soft leakage problem of20V LDMOS with epitaxial process is settled. The mechanisms of soft leakage underlow level ESD stress is analyzed with electric field induce and thermal induce. Theexperiment confirms that, for20V LDMOS, the leakage current of the optimizedstructures keeps consistent at1nA or even0.05nA, and the second breakdown currentincreases from2.2A to4.0A; for40V LDMOS, the leakage current of the optimizedstructures keeps consistent at1nA, and the second breakdown current increases from1.17A to1.62A.
The influences of parasitic bulk resistance are discussed. Besides reducing oftrigger voltage, larger bulk resistance can restrain the surface generated current byincreasing the current gain of parasitic NPN. The bulk parasitic resistances arecalculated with geometric parameter. The experiment confirms that, the device withsegmentation P+implant has best ESD discharge ability, whose second breakdowncurrent increases from1.0A to1.88A.
(2) Surface transport current restrain technique is realized by shunting the lateralcurrent component through the parasitic vertical devices, or by pushing the carriers deepinto the device body.
The mechanism of strong snapback of700V LDMOS with bulk-silicon process isstudied. Based on surface transport current reduce technique, a parasitic vertical PNP isinduced in the novel structure to shunt the lateral part current. As the simulation results,the triggering of parasitic lateral NPN is restrained, and the novel structure has twiceESD discharge ability compared with the conventional one.
Power clamp ESD protection of190V SOI PDP scan driver IC is studied. Based onthe surface current reduce model, the deep discharge LIGBT is used to replace theconventional HV Diode. With the parasitic PNP to reduce the avalanche currentcomponent, the surface generated current is reduced; with holes instead of electros inthe drift region, the carriers are pushed deep into the device, and the surface transportcurrent is restrained. The experiment confirms that, the second breakdown voltage ofdeep discharge LIGBT is217V compared with the HV Diode of251V, and the secondbreakdown current is0.52A compared with the HV Diode of0.39A. The PDP scandriver IC with deep discharge LIGBT is tested with HBM standard, and it has8KV HBM ESD robustness.
3. The double snapback characteristics of LDMOS-SCR with bulk-silicon processare studied. With the analysis of mechanism, a criterion is proposed for the secondsnapback. By reducing the second snapback current and voltage, better ESD dischargeability can be obtained. The experiment confirms that, the second breakdown current ofoptimized structure increases from0.57A to3.1A.
本文对功率集成电路中高压ESD防护器件表面电流集中问题进行研究，提出了一个模型和两项技术，即：提出表面电流抑制模型，并藉此发展了表面产生电流和表面输运电流的抑制技术。基于表面电流抑制模型和技术，对20V/40V外延工艺、190V SOI（Silicon On Insulator）工艺、700V单晶工艺条件下的不同器件进行了优化。此外，提出了LDMOS-SCR（Silicon Controlled Rectifer）器件二次回扫发生判据，并以此对其双回扫特性进行优化。本文主要有以下工作：
1、提出ESD防护器件表面电流抑制模型。基于器件体内温度分布及电-热模型，结合二次击穿发生条件，分析了表面电流集中造成的晶格温度升高以及与此伴生的热点（Hot Pot）问题；基于表面隧穿产生机理，分析了泄漏电流增加与表面电流集中的关系；阐述了表面电流集中导致的导通电阻增大，以及由此引起的ESD泄放能力降低问题。通过分析LDMOS器件在ESD应力下的泄放原理，研究并总结了表面电流集中的产生原因，提出抑制表面电流来提高器件ESD泄放能力的优化模型，并发展出抑制表面电流集中的两项技术：表面产生电流抑制技术和表面输运电流抑制技术。
2、基于表面电流抑制模型和技术，指导高压ESD防护器件性能优化。
（1）表面产生电流抑制技术，即通过抑制表面电场峰值，降低表面碰撞电离产生率；或通过增强寄生器件电流增益，降低维持同样泄放电流中雪崩倍增电流分量，以抑制表面局部产生电流。针对外延型20V/40V LDMOS，采用表面产生电流抑制技术，解决了由于隧穿和局部热熔丝导致的软击穿问题。实验证实，优化后20V LDMOS泄漏电流恒定在1nA甚至0.05nA，二次击穿电流由原始器件的2.2A上升至4.0A；优化后40V LDMOS泄漏电流恒定在约1nA，二次击穿电流由原始器件的1.17A提升至1.62A。讨论了LDMOS器件衬底寄生电阻与ESD特性的关系，通过增大衬底寄生电阻可增强寄生NPN电流增益，降低维持同样泄放电流中雪崩倍增电流分量，从而抑制表面产生电流。设计了具有分段隔离式P+注入的器件源-衬结构。实验证实，优化后器件二次击穿电流由1.0A提升至1.88A，将优化结构运用到芯片ESD防护中时，其HBM（Human Body Model）ESD能力由3KV上升至5.5KV。
（2）表面输运电流抑制技术，即通过增强纵向寄生器件电流能力，以纵向分流来抑制表面横向电流分量；或通过抑制纵向电场对自由载流子向表面吸附作用，来减小电流在表面的输运量。针对单晶型700V LDMOS器件出现的强回扫，通过设计新的体内纵向寄生器件VPNP，以分流来达到来抑制表面横向电流分量的目的，避免因寄生NPN开启导致强回扫发生。仿真结果显示，新结构电流泄放能力较原始器件提高约一倍。针对SOI基190V PDP（Plasma Display Panels）驱动芯片高压电源钳位，综合运用抑制表面电流的两项技术，采用深体泄放LIGBT（LateralInsulated Gate Bipolar Transistor）替代常规HV（High Voltage） Diode器件。其寄生PNP参与导电以降低雪崩倍增分量，从而抑制表面产生电流；其纵向电场将漂移区中的自由空穴推离器件表面，以抑制表面输运电流。实验证实，器件二次击穿电压由251V下降至217V，二次击穿电流则由0.39A上升至0.52A。将深体泄放LIGBT应用在PDP驱动IC中作为高压电源钳位，获得了8KV的HBM ESD能力。
3、研究并优化LDMOS-SCR器件双回扫特性。分析单晶型5V CMOS工艺条件下LDMOS-SCR器件双回扫现象产生机理，提出其二次回扫发生判据。通过降低二次回扫电压和电流，以减小器件在低ESD应力下的功耗，从而获得更强的ESD泄放能力。实验证实，优化后器件的二次击穿电流由0.57A上升至3.1A。
In integrated smart power application, the robustness of ESD (Electro-StaticDischarge) is one of determining factors for stability and reliability of the system. Withstronger ESD robustness, the design cycle and design cost of HV （high Voltage）power IC can be cut down. Therefore, it's very important and useful to study theworking mechanisms of the ESD protection devices and improve their protectionabilities. However, surface current integration easily occurs with high voltage and highelectric field, and worsens the lattice temperature, rises up leakage current, andincreases the discharge resistance. Therefore, A series of HV ESD protection deviceshave been designed and optimized at home and abroad to optimize the discharge path,and improve the discharge ability.
However, the characteristics of HV ESD protection devices are sensitive withmanufactory process parameters, and the optimize methods for one process may notavailable for other processes. It’s very hard to set up a universality theory for ESDrobustness optimization. Meanwhile, the modification of manufactory process willlower down the compatibility and increase the cost.
In this thesis, the surface current integration problem is studied, and the main workis as follows.
1. Surface current reduce model is proposed. The problems caused by surfacecurrent integration are studied. Based on the temperature distribution andelectro-thermal model, the lattice temperature increasing and the hot pot problem withsurface current integration are analyzed. Based on the surface tunnel model, therelationship between leakage current and surface current integration is discussed.Meanwhile, the discharge resistance increasing problem with surface current integrationis studied. By summarizing the mechanisms of surface current integration, twotechniques are proposed: surface generated current restrain technique and surfacetransport current restrain technique.
2. Based on the surface current reduce model and techniques, settle differentproblems for devices under ESD stress.
(1) Surface generated current restrain technique is realized by restraining thesurface electric field and surface impact ionization generation rate, or by enhance the current gain of the parasitic devices to reduce the avalanche multiple currentcomponent.
Based on the surface generated current restrain technique, soft leakage problem of20V LDMOS with epitaxial process is settled. The mechanisms of soft leakage underlow level ESD stress is analyzed with electric field induce and thermal induce. Theexperiment confirms that, for20V LDMOS, the leakage current of the optimizedstructures keeps consistent at1nA or even0.05nA, and the second breakdown currentincreases from2.2A to4.0A; for40V LDMOS, the leakage current of the optimizedstructures keeps consistent at1nA, and the second breakdown current increases from1.17A to1.62A.
The influences of parasitic bulk resistance are discussed. Besides reducing oftrigger voltage, larger bulk resistance can restrain the surface generated current byincreasing the current gain of parasitic NPN. The bulk parasitic resistances arecalculated with geometric parameter. The experiment confirms that, the device withsegmentation P+implant has best ESD discharge ability, whose second breakdowncurrent increases from1.0A to1.88A.
(2) Surface transport current restrain technique is realized by shunting the lateralcurrent component through the parasitic vertical devices, or by pushing the carriers deepinto the device body.
The mechanism of strong snapback of700V LDMOS with bulk-silicon process isstudied. Based on surface transport current reduce technique, a parasitic vertical PNP isinduced in the novel structure to shunt the lateral part current. As the simulation results,the triggering of parasitic lateral NPN is restrained, and the novel structure has twiceESD discharge ability compared with the conventional one.
Power clamp ESD protection of190V SOI PDP scan driver IC is studied. Based onthe surface current reduce model, the deep discharge LIGBT is used to replace theconventional HV Diode. With the parasitic PNP to reduce the avalanche currentcomponent, the surface generated current is reduced; with holes instead of electros inthe drift region, the carriers are pushed deep into the device, and the surface transportcurrent is restrained. The experiment confirms that, the second breakdown voltage ofdeep discharge LIGBT is217V compared with the HV Diode of251V, and the secondbreakdown current is0.52A compared with the HV Diode of0.39A. The PDP scandriver IC with deep discharge LIGBT is tested with HBM standard, and it has8KV HBM ESD robustness.
3. The double snapback characteristics of LDMOS-SCR with bulk-silicon processare studied. With the analysis of mechanism, a criterion is proposed for the secondsnapback. By reducing the second snapback current and voltage, better ESD dischargeability can be obtained. The experiment confirms that, the second breakdown current ofoptimized structure increases from0.57A to3.1A.
引文
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