MEMS封装中的残余应力演化及其相关可靠性研究
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摘要
本论文主要研究对MEMS封装中芯片粘贴于基板时所引起的应力问题。本文用硅压阻芯片作为测量载体，对粘贴中所涉及的基板、粘合剂、芯片在基板的不同位置以及芯片在热处理过程中对表面残余应力的影响作了系统的研究，得到如下主要结论：
1．在不同基板上固化时，芯片表面应力演化过程不同。对于FR4基板，在固化过程中，芯片表面的剪切应力和正应力的值很小，其数值在原点上下很窄的范围内波动。在降温过程中，热膨胀系数的失配随着温度的降低而越来越显著，引起应力的积聚。对于陶瓷基板，在固化过程中，剪切应力并不象FR4基板上所表现的那样，在零点上下波动，而是处于一个绝对值较大的负值。该现象是由于粘合剂的热膨胀系数在固化温度附近不稳定性所致。在降温过程中，剪切应力的绝对值逐渐从一个较高水平逐渐开始减小，并趋于平衡。采用芯片直接粘接在基板上的方式固定芯片时，欲获得较低的残余应力和较理想的应力分布，采用Al_2O_3陶瓷基板要优于FR4基板。当采用陶瓷基板时，剪切应力和正应力的平均值均比采用FR4基板时降低40％左右。
2．使用不同有机粘合剂于芯片粘贴时，应力演化过程基本相似。在冷却过程中某些局域正应力差的变化规律为：该差值从正值变到负值再回到正值，呈振荡状态；局域随热循环进行应力将急剧增加，即处于应力相对集中的状态，这样的区域是芯片易于失效的区域。使用热膨胀系数较小的有机粘合剂粘贴芯片时，可获得较低的残余应力和相对优越的应力分布。该规律可以作为选择有机粘合剂时的参照。
中国科学院博士学位论文
3．当芯片粘贴在基板中心和靠近基板边缘的位置时粘合剂固化后残余
应力的平均值、最大值和数值的分散性皆处于相接近的水平，而当
粘贴在基板靠近一角的位置时应力分布状况则有很大不同：应力的
分散性增大，应力最大值也远大于粘贴于另外两个位置时的值。芯
片粘贴在中心位置和靠近边缘位置时，残余应力在热处理过程中随
不同的热处理制度呈有规律的起伏变化，而粘贴在靠近一角的位置
时芯片的应力在热处理过程中变化剧烈，出现“突跳”和“尖点”。
这一应力剧变现象是通过硅压阻芯片的方法首次观测到的。
4．在粘合剂固化后紧接着进行热处理，可以使残余应力稳定在一个相
对低的值；而固化后在空气中储存20天后，应力在热处理过程中会
急剧增加。在固化完成后进行适当的热处理，可以避免芯片使用一
段时间后，经过高温而产生的芯片表面应力的剧烈增加、进而导致
对芯片性能和结构的危害。运用TGA、DTA等热分析手段对粘合
剂的固化过程和再固化过程进行了研究，并对实验中的应力突变的
机理进行探讨，认为水汽是导致应力突变的主要原因。这一发现为
克服粘合剂粘贴的残余应力并使之稳定化提供了依据。
5．硅压阻传感芯片测量结果与计算机模拟结果的比较表明，硅压阻传
感芯片测量值与计算机模拟值很接近，测量值的正负区间与模拟值
的正负区间完全吻合。但有限元模拟具有一定的局限性，实验测量
才能对封装所致残余应力进行真实模拟，从而得到与实际情况相符
合的结果。
The thesis focuses on the stress issue induced by die attachment in MEMS (namely, Micro-Electronic-Mechanical System) packaging. With silicon piezoresistive sensor chip as the media of in-situ measurement, a series of investigation have been carried out including the studying of residual stress affected by different substrates, different adhesives, different positions of the chip attached on the substrate as well as the thermal treatment. The main results are summarized as follows:
1. While the chips are attached to different kinds of substrates, the evolution trends of surface residual stress are also different. When the substrate is FR4, the surface shear stress and normal stress difference is at a low level and near zero during curing process and build up during cooling down because of the mismatch of CTEs of silicon and substrate. When the substrate is AliOs ceramic substrate, the shear stress hovers over a relatively high negative level during curing process and steps to a relatively low level during cooling down. If low residual stress and better residual stress distribution map are expected, A12O3 ceramic substrate is a better choice compared to FR4. The mean residual stress of A^Os ceramic substrate is lower than the mean residual stress of FR4 with the difference around 40%.
2. While the chips are attached to substrates with different organic adhesives, the evolution trends of surface residual stress are alike. It is found during the cooling down in some local region that the normal stress difference varies from positive to negative and then turns positive again. The stress accumulates rapidly in the followed thermal treatment in this region, where the chip-on-board package tends to fail from. If low residual stress and better
residual stress distribution map are expected, adhesives with low CTE is preferred, which could be a criteria to select organic adhesives.
3. While the chips are attached to near center or near a edge of subatrate, the mean, deviation and maximum are at the almost same level; when the chip is attached near a corner, the deviation and the maximum is far larger than those of the above two positions; During thermal treatment followed ,the residual stress demonstrates a regular cycle trend when the chips are attached near center or edge of the substrate and fluctuates in a wide range when the chip is attached near a corner. Sudden increase or decrease can be found in the trend of residual stress of the latter case.
4. After 20 days' storage in air at room temperature after curing, the residual stresses accumulate significantly in re-curing process and after additional curing, the residual stress stabilizes at a relatively low level. Thermal analysis of the adhesive was performed to identify the incomplete cure of the adhesive after first curing process and the penetration of moisture into the package is the main reason for sharp stress increase. This result could be utilized to lower and stabilize the residual stress induced by the adhesive attachment.
5. In the simulated distribution residual stress map, the results of FE simulation is close to those measured by silicon piezoresistive sensor chip while the distribution of negative region and positive region matches with the measured map. However, the FE method has its limit, experimental measurement is the essential way to investigate the packaging related issues. Only by experimental measurement, can results accords with reality be obtained.
1．在不同基板上固化时，芯片表面应力演化过程不同。对于FR4基板，在固化过程中，芯片表面的剪切应力和正应力的值很小，其数值在原点上下很窄的范围内波动。在降温过程中，热膨胀系数的失配随着温度的降低而越来越显著，引起应力的积聚。对于陶瓷基板，在固化过程中，剪切应力并不象FR4基板上所表现的那样，在零点上下波动，而是处于一个绝对值较大的负值。该现象是由于粘合剂的热膨胀系数在固化温度附近不稳定性所致。在降温过程中，剪切应力的绝对值逐渐从一个较高水平逐渐开始减小，并趋于平衡。采用芯片直接粘接在基板上的方式固定芯片时，欲获得较低的残余应力和较理想的应力分布，采用Al_2O_3陶瓷基板要优于FR4基板。当采用陶瓷基板时，剪切应力和正应力的平均值均比采用FR4基板时降低40％左右。
2．使用不同有机粘合剂于芯片粘贴时，应力演化过程基本相似。在冷却过程中某些局域正应力差的变化规律为：该差值从正值变到负值再回到正值，呈振荡状态；局域随热循环进行应力将急剧增加，即处于应力相对集中的状态，这样的区域是芯片易于失效的区域。使用热膨胀系数较小的有机粘合剂粘贴芯片时，可获得较低的残余应力和相对优越的应力分布。该规律可以作为选择有机粘合剂时的参照。
中国科学院博士学位论文
3．当芯片粘贴在基板中心和靠近基板边缘的位置时粘合剂固化后残余
应力的平均值、最大值和数值的分散性皆处于相接近的水平，而当
粘贴在基板靠近一角的位置时应力分布状况则有很大不同：应力的
分散性增大，应力最大值也远大于粘贴于另外两个位置时的值。芯
片粘贴在中心位置和靠近边缘位置时，残余应力在热处理过程中随
不同的热处理制度呈有规律的起伏变化，而粘贴在靠近一角的位置
时芯片的应力在热处理过程中变化剧烈，出现“突跳”和“尖点”。
这一应力剧变现象是通过硅压阻芯片的方法首次观测到的。
4．在粘合剂固化后紧接着进行热处理，可以使残余应力稳定在一个相
对低的值；而固化后在空气中储存20天后，应力在热处理过程中会
急剧增加。在固化完成后进行适当的热处理，可以避免芯片使用一
段时间后，经过高温而产生的芯片表面应力的剧烈增加、进而导致
对芯片性能和结构的危害。运用TGA、DTA等热分析手段对粘合
剂的固化过程和再固化过程进行了研究，并对实验中的应力突变的
机理进行探讨，认为水汽是导致应力突变的主要原因。这一发现为
克服粘合剂粘贴的残余应力并使之稳定化提供了依据。
5．硅压阻传感芯片测量结果与计算机模拟结果的比较表明，硅压阻传
感芯片测量值与计算机模拟值很接近，测量值的正负区间与模拟值
的正负区间完全吻合。但有限元模拟具有一定的局限性，实验测量
才能对封装所致残余应力进行真实模拟，从而得到与实际情况相符
合的结果。
The thesis focuses on the stress issue induced by die attachment in MEMS (namely, Micro-Electronic-Mechanical System) packaging. With silicon piezoresistive sensor chip as the media of in-situ measurement, a series of investigation have been carried out including the studying of residual stress affected by different substrates, different adhesives, different positions of the chip attached on the substrate as well as the thermal treatment. The main results are summarized as follows:
1. While the chips are attached to different kinds of substrates, the evolution trends of surface residual stress are also different. When the substrate is FR4, the surface shear stress and normal stress difference is at a low level and near zero during curing process and build up during cooling down because of the mismatch of CTEs of silicon and substrate. When the substrate is AliOs ceramic substrate, the shear stress hovers over a relatively high negative level during curing process and steps to a relatively low level during cooling down. If low residual stress and better residual stress distribution map are expected, A12O3 ceramic substrate is a better choice compared to FR4. The mean residual stress of A^Os ceramic substrate is lower than the mean residual stress of FR4 with the difference around 40%.
2. While the chips are attached to substrates with different organic adhesives, the evolution trends of surface residual stress are alike. It is found during the cooling down in some local region that the normal stress difference varies from positive to negative and then turns positive again. The stress accumulates rapidly in the followed thermal treatment in this region, where the chip-on-board package tends to fail from. If low residual stress and better
residual stress distribution map are expected, adhesives with low CTE is preferred, which could be a criteria to select organic adhesives.
3. While the chips are attached to near center or near a edge of subatrate, the mean, deviation and maximum are at the almost same level; when the chip is attached near a corner, the deviation and the maximum is far larger than those of the above two positions; During thermal treatment followed ,the residual stress demonstrates a regular cycle trend when the chips are attached near center or edge of the substrate and fluctuates in a wide range when the chip is attached near a corner. Sudden increase or decrease can be found in the trend of residual stress of the latter case.
4. After 20 days' storage in air at room temperature after curing, the residual stresses accumulate significantly in re-curing process and after additional curing, the residual stress stabilizes at a relatively low level. Thermal analysis of the adhesive was performed to identify the incomplete cure of the adhesive after first curing process and the penetration of moisture into the package is the main reason for sharp stress increase. This result could be utilized to lower and stabilize the residual stress induced by the adhesive attachment.
5. In the simulated distribution residual stress map, the results of FE simulation is close to those measured by silicon piezoresistive sensor chip while the distribution of negative region and positive region matches with the measured map. However, the FE method has its limit, experimental measurement is the essential way to investigate the packaging related issues. Only by experimental measurement, can results accords with reality be obtained.
引文
1．王正，刘之景，封装技术评述，半导体技术，24(6)，2000：7～9
2. Jianjun Wang, Zhengfang Qian, Daqing Zou, and Sheng Liu, Creep Behavior of a Flip-chip package by Both FEM Modeling and Real Time Moiré Interferometry, 1998 IEEE Electronic Components and Technology Conference, 1438～1445
3. Jiansen Zhu, Daqing Zou, Sheng Liu, High Temperature Deformation of Area Array Packages by Moiré Interferometry/FEM Hybrid Method, 1997 IEEE Electronic Components and Technology Conference, 444～452
4. L.T.Nguyen, Reliablity of postmolded IC packages, Transactions of the ASME, Journal of Electronic Packaging, Vol.115, December 1993,346～355)
5. B.Kloeck and N.F. De Rooij, Mechanical Sensors, (Chapter4 of Semiconductor Sensors, Edited by S.M.Sze), John Wiley & Sons, Inc., New York, 1994
6. Zou, Y., et al. Characterization of plastic packages using (100) silicon stresstest chips. in Proceedings of the 1997 ASME International Mechanical Engineering Congress and Exposition. 1997. Dallas, TX, USA: Applications of Experimental Mechanics to Electronic Packaging American Society of Mechanical Engineers, EEP. v 22 1997. ASME, Fairfield, NJ, USA.
7. Spencer, J.L., Schroen, W.H., Bednarz, G.A., Bryan, J.A., Metzgar, T.D., Cleveland, R.D., and Edwards, D.R. New Quantitative Measurements of IC Stress Introduced by Plastic Packages. in Proceeding of the 19th Annual Reliability Physics Symposium, IEEE. 1981.
8. Edwards, D.R., Heinen, K.G., Martinez, J.E., and Groothuis, S.TestStructure Metholodgy of IC Package Material Characterization. inProceedings of the 33rd Electronic Components Conference, IEEE. 1983.
9. Beaty, R.E., et al. Calibration considerations for piezoresistive-based stress sensors. in Proceedings of the 40th Electronic Components and Technology Conference. 1990. Las Vegas, NV, USA: Proceedings-ElectronicComponents Conference. Publ by IEEE, IEEE Service Center, Piscataway, NJ, USA (IEEE cat n 90CH2893-6). v 1.
10. Natarajan, B., and Bhattacharyya, B. Die Surface Stresses in a Molded Plastic Package. in Proceedings of the 36th Electronic Components Conference, IEEE. 1986.
11. Gee, S.A., Van Den Bogert, W.F., and Akylas, V.R., Strain-Gauge Mapping of Die Surface Stresses. IEEE Transactions on Components, Hybrids, and Manufacturing Technology, 1989. 12(4): p. 587-593.
12. Bittle, D.A., et al., Piezoresistive stress sensors for structural analysis of electronic packages. Journal of Electronic Packaging, 1991. 113(3): p. 203-215.
13. Suhling, J.C., R.C. Jaeger, and R. Ramani. Stress measurement using 0-90 piezoresistive rosettes on (111) silicon. in Proceedings of the 1994 International Mechanical Engineering Congress and Exposition. 1994. Chicago, IL, USA: Mechanics and Materials for Electronic Packaging American Society of Mechanical Engineers, Applied Mechanics Division, AMD. v 195 1994. ASME, New York, NY, USA.
14. Jaeger, R.C., et al., Off-axis sensor rosettes for measurement of the piezoresistive coefficients of silicon. IEEE Transactions on Components, Hybrids & Manufacturing Technology, 1993. 16(8): p. 925-931.
15. Jaeger, R.C., J.C. Suhling, and R. Ramani. Errors associated with the design and calibration of piezoresistive stress sensors in (100) silicon. in Proceedings of the 1992 Joint ASME/JSME Conference on Electronic Packaging. 1992. Milpitas,
CA, USA: Advances in Electronic Packaging-1992 American Society of Mechanical Engineers, EEP. Publ by ASME, New York, NY, USA. v 1.
16. Zou, Y., et al. Characterization of plastic packages using(100) silicon stress test chips. in Proceedings of the 1997 ASME International Mechanical Engineering Congress and Exposition. 1997. Dallas, TX, USA: Applications of Experimental Mechanics to Electronic Packaging American Society of Mechanical Engineers, EEP. v 22 1997. ASME, Fairfield, NJ, USA.
17. Zou, Y., et al. Three-dimensional die surface stress measurements in delaminated and non-delaminated plastic packages. in Proceedings of the 1998 48th Electronic Components & Technology Conference. 1998. Seattle, WA, USA: Proceedings-Electronic Components and Technology Conference 1998. IEEE, Piscataway, NJ, USA,98CB36206..
18. Zou, Y., et al., In-situ stress state measurements during chip-on-board assembly. IEEE Transactions on Electronics Packaging Manufacturing, 1999.22(1):p.38-52.
19. Zou, Y., J.C.Suhling, and R.C.Jaeger, Die surface stress variation during thermal cycling and thermal aging reliability tests. Proceedings-Electronic Components and Technology Conference, 1999:p.1249-1260.
20. Zou, Y., et al. Die stress measurements using high temperature die-attachment materials, in Proceedings of the 1998 ASME International Mechanical Engineering Congress and Exposition. 1998. Anaheim, CA, USA: Thermo-Mechanical Characterization of Evolving Packaging Materials and Structures American Society of Mechanical Engineers, EEP. v 24 1998. ASME, Fairfield, NJ, USA.
21. Suhling, J.C., et al., Measurement of backside flip chip die stresses using
piezoresistive test die. Proceedings of Spie-the International Society for Optical Engineering. v 3906 1999, 1999:p.298-303.
22．贾松良，朱浩颖，罗艳斌，压阻型集成电路封装应力测试芯片的研究与应用，半导体学报，Vol．19，1998(11)：812～817
23. Beaty, R.E., et al. Calibration considerations for piezoresistive-based stress sensors. in Proceedings of the 40th Electronic Components and Technology Conference. 1990. Las Vegas, NV, USA: Proceedings-Electronic Components Conference. Publ by IEEE, IEEE Service Center, Piscataway, NJ, USA(IEEE cat n 90CH2893-6). v 1.
24. Gee, S.A., Akylas, V.R., and Van Den Bogert, W.F. The Design and Calibration of a Semiconductor Strain Gauge Array. in Proceedings of the 1988 IEEE International Conference on Microelectronic Test Structures. 1988.
25. Lo, T.C.P., Design, Fabrication and Characterization of Micro-Strain Gauges for VLSI packaging Applications, in Department of Electrical and Eletronic Engineering. 1996, The Hong Kong University of Science and Technology: Hong Kong(SAR).
26. Suhling, J.C., et al. Wafer-level calibration of stress sensing test chips. In Proceedings of the 1994 IEEE 44th Electronic Components & Technology Conference. 1994. Washington, DC, USA: Proceedings-Electronic Components and Technology Conference. Publ by IEEE, IEEE Service Center, Piscataway, NJ, USA. 1994.
27. Kang, Y., et al. Hydrostatic response of piezoresistive stress sensors. In Proceedings of the 1997 ASME International Mechanical Engineering Congress and Exposition. 1997. Dallas, TX, USA: Applications of Experimental Mechanics to Electronic Packaging American Society of Mechanical Engineers,
EEP.v 22 1997. ASME, Fairfield, NJ, USA.
28. Bittle, D.A., et al., Piezoresistive stress sensors for structural analysis of electronic packages. Journal of Electronic Packaging, 1991.113(3):p.203-215.
2. Jianjun Wang, Zhengfang Qian, Daqing Zou, and Sheng Liu, Creep Behavior of a Flip-chip package by Both FEM Modeling and Real Time Moiré Interferometry, 1998 IEEE Electronic Components and Technology Conference, 1438～1445
3. Jiansen Zhu, Daqing Zou, Sheng Liu, High Temperature Deformation of Area Array Packages by Moiré Interferometry/FEM Hybrid Method, 1997 IEEE Electronic Components and Technology Conference, 444～452
4. L.T.Nguyen, Reliablity of postmolded IC packages, Transactions of the ASME, Journal of Electronic Packaging, Vol.115, December 1993,346～355)
5. B.Kloeck and N.F. De Rooij, Mechanical Sensors, (Chapter4 of Semiconductor Sensors, Edited by S.M.Sze), John Wiley & Sons, Inc., New York, 1994
6. Zou, Y., et al. Characterization of plastic packages using (100) silicon stresstest chips. in Proceedings of the 1997 ASME International Mechanical Engineering Congress and Exposition. 1997. Dallas, TX, USA: Applications of Experimental Mechanics to Electronic Packaging American Society of Mechanical Engineers, EEP. v 22 1997. ASME, Fairfield, NJ, USA.
7. Spencer, J.L., Schroen, W.H., Bednarz, G.A., Bryan, J.A., Metzgar, T.D., Cleveland, R.D., and Edwards, D.R. New Quantitative Measurements of IC Stress Introduced by Plastic Packages. in Proceeding of the 19th Annual Reliability Physics Symposium, IEEE. 1981.
8. Edwards, D.R., Heinen, K.G., Martinez, J.E., and Groothuis, S.TestStructure Metholodgy of IC Package Material Characterization. inProceedings of the 33rd Electronic Components Conference, IEEE. 1983.
9. Beaty, R.E., et al. Calibration considerations for piezoresistive-based stress sensors. in Proceedings of the 40th Electronic Components and Technology Conference. 1990. Las Vegas, NV, USA: Proceedings-ElectronicComponents Conference. Publ by IEEE, IEEE Service Center, Piscataway, NJ, USA (IEEE cat n 90CH2893-6). v 1.
10. Natarajan, B., and Bhattacharyya, B. Die Surface Stresses in a Molded Plastic Package. in Proceedings of the 36th Electronic Components Conference, IEEE. 1986.
11. Gee, S.A., Van Den Bogert, W.F., and Akylas, V.R., Strain-Gauge Mapping of Die Surface Stresses. IEEE Transactions on Components, Hybrids, and Manufacturing Technology, 1989. 12(4): p. 587-593.
12. Bittle, D.A., et al., Piezoresistive stress sensors for structural analysis of electronic packages. Journal of Electronic Packaging, 1991. 113(3): p. 203-215.
13. Suhling, J.C., R.C. Jaeger, and R. Ramani. Stress measurement using 0-90 piezoresistive rosettes on (111) silicon. in Proceedings of the 1994 International Mechanical Engineering Congress and Exposition. 1994. Chicago, IL, USA: Mechanics and Materials for Electronic Packaging American Society of Mechanical Engineers, Applied Mechanics Division, AMD. v 195 1994. ASME, New York, NY, USA.
14. Jaeger, R.C., et al., Off-axis sensor rosettes for measurement of the piezoresistive coefficients of silicon. IEEE Transactions on Components, Hybrids & Manufacturing Technology, 1993. 16(8): p. 925-931.
15. Jaeger, R.C., J.C. Suhling, and R. Ramani. Errors associated with the design and calibration of piezoresistive stress sensors in (100) silicon. in Proceedings of the 1992 Joint ASME/JSME Conference on Electronic Packaging. 1992. Milpitas,
CA, USA: Advances in Electronic Packaging-1992 American Society of Mechanical Engineers, EEP. Publ by ASME, New York, NY, USA. v 1.
16. Zou, Y., et al. Characterization of plastic packages using(100) silicon stress test chips. in Proceedings of the 1997 ASME International Mechanical Engineering Congress and Exposition. 1997. Dallas, TX, USA: Applications of Experimental Mechanics to Electronic Packaging American Society of Mechanical Engineers, EEP. v 22 1997. ASME, Fairfield, NJ, USA.
17. Zou, Y., et al. Three-dimensional die surface stress measurements in delaminated and non-delaminated plastic packages. in Proceedings of the 1998 48th Electronic Components & Technology Conference. 1998. Seattle, WA, USA: Proceedings-Electronic Components and Technology Conference 1998. IEEE, Piscataway, NJ, USA,98CB36206..
18. Zou, Y., et al., In-situ stress state measurements during chip-on-board assembly. IEEE Transactions on Electronics Packaging Manufacturing, 1999.22(1):p.38-52.
19. Zou, Y., J.C.Suhling, and R.C.Jaeger, Die surface stress variation during thermal cycling and thermal aging reliability tests. Proceedings-Electronic Components and Technology Conference, 1999:p.1249-1260.
20. Zou, Y., et al. Die stress measurements using high temperature die-attachment materials, in Proceedings of the 1998 ASME International Mechanical Engineering Congress and Exposition. 1998. Anaheim, CA, USA: Thermo-Mechanical Characterization of Evolving Packaging Materials and Structures American Society of Mechanical Engineers, EEP. v 24 1998. ASME, Fairfield, NJ, USA.
21. Suhling, J.C., et al., Measurement of backside flip chip die stresses using
piezoresistive test die. Proceedings of Spie-the International Society for Optical Engineering. v 3906 1999, 1999:p.298-303.
22．贾松良，朱浩颖，罗艳斌，压阻型集成电路封装应力测试芯片的研究与应用，半导体学报，Vol．19，1998(11)：812～817
23. Beaty, R.E., et al. Calibration considerations for piezoresistive-based stress sensors. in Proceedings of the 40th Electronic Components and Technology Conference. 1990. Las Vegas, NV, USA: Proceedings-Electronic Components Conference. Publ by IEEE, IEEE Service Center, Piscataway, NJ, USA(IEEE cat n 90CH2893-6). v 1.
24. Gee, S.A., Akylas, V.R., and Van Den Bogert, W.F. The Design and Calibration of a Semiconductor Strain Gauge Array. in Proceedings of the 1988 IEEE International Conference on Microelectronic Test Structures. 1988.
25. Lo, T.C.P., Design, Fabrication and Characterization of Micro-Strain Gauges for VLSI packaging Applications, in Department of Electrical and Eletronic Engineering. 1996, The Hong Kong University of Science and Technology: Hong Kong(SAR).
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