RapidIO高速互联接口的设计研究与应用
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摘要
嵌入式处理技术的快速发展,给高性能嵌入式系统的高速互联方面带来了严峻的挑战。为了应对这类挑战,同时适应嵌入式系统的发展需要,业界领先的半导体和系统制造商联合制订了一种可实现任意拓扑和点对点操作、高效且具有很高可靠性和有效拥塞控制的高速互联协议——RapidIO。
本文正是基于嵌入式技术所面临的数据传输瓶颈以及RapidIO所体现出的优越性,对RapidIO进行了大量的分析和研究工作,具体如下:
1.首先对串行RapidIO协议结构进行了深入研究。串行RapidIO协议分为三层:逻辑层、传输层、物理层。这种层次结构的一大特点是,在任意层对事务类型进行修改都不会影响到其它层的规范,具有很强的灵活可变性。本文依据该层次结构,分别对每一层次所完成的操作进行了细致的分析。
2.根据对协议的研究分析结果,本文对串行RapidIO物理层进行了FPGA逻辑实现。串行RapidIO物理层,其不仅需要完成对包的物理层字段的封装,还要负责端口的初始化、包的发送和接收、流量控制、错误管理等操作。本文以上述操作为索引,对其实现过程进行了详细阐述。
3.完成了串行RapidIO物理层的设计和FPGA逻辑实现后,本文紧接着对逻辑实现的代码进行了RTL级仿真并给出了逻辑资源消耗情况。整个仿真过程分别对端口的初始化、包的发送和接收、流量控制、错误管理进行了验证,证明了其功能正确并符合RapidIO 1.3协议版本对串行物理层的描述,从而保证了本文的逻辑实现成果能顺利地与芯片厂商提供的IP核进行互联通信。
4.针对串行RapidIO的各种优点,本文将其应用到第三代和第四代无线通信技术中,完成了基于串行RapidIO的基带处理架构方案。最后通过搭建硬件测试平台,根据实际上板所得到的流量测试结果从灵活性、可靠性、可扩展性等方面验证了该架构方案的正确性和可行性。
The fast development of embedded processing technology is posed a serious challenge to high-performance embedded system high-speed interconnection. In order to cope with such challenges and meet the needs of embedded system development, the industry's leading semiconductor and system manufacturers work together to set up a high-speed Internet Protocol - RapidIO.This protocol can support arbitrary topology and point-to-point operation, provide effective congestion control, high transmission efficiency and reliability.
Because of the bottleneck on data transmission of embedded system and the superiority of RapidIO on interconnection, this dissertation does many works to analyse and research on the RapidIO. The main results are as follows:
1. First of all, this dissertation carries out study on the structure of Serial RapidIO protocol. Serial RapidIO protocol is divided into three layers: logical layer, transport layer, physical layer. Such a hierarchical structure characterized by a layer of affairs in any type of change will not affect other layers of the norms, is highly flexible and variable. Based on the hierarchical structure, this dissertation carries out detailed analysis on the operation of each layer.
2. Based on results of the RapidIO protocol analysis, this dissertation does logic implementation of the serial physical layer. Serial physical layer is not only required to complete the physical layer packet fields encapsulation but also is in charge of port initialization, sending and receiving packets and control symbols, flow control, error management, and other operations. This dissertation discusses the logic implementation process in detail based on the functions of the physical layer.
3. After the accomplishment of the serial RapidIO physical layer FPGA logic implementation, this dissertation does RTL simulation immediately for the implementation of the logic code and shows the logic resource consumption. Throughout the simulation of the initialization of the port, sending and receiving packets, flow control, and error management, it verifies that the functions are correct in accordance with the RapidIO 1.3 protocol version. Consequently, the FPGA logic implementation of this dissertation can successfully communicate with the chip vendor IP core.
4. For a variety of advantages, this dissertation applies Serial RapidIO into the fourth generation of wireless communications technology.this dissertation completes a Serial RapidIO-based architecture of the baseband process system. Finally this dissertation sets up a hardware test platform, according to the test results it verifyies correctness and feasibility of this architecture.
本文正是基于嵌入式技术所面临的数据传输瓶颈以及RapidIO所体现出的优越性,对RapidIO进行了大量的分析和研究工作,具体如下:
1.首先对串行RapidIO协议结构进行了深入研究。串行RapidIO协议分为三层:逻辑层、传输层、物理层。这种层次结构的一大特点是,在任意层对事务类型进行修改都不会影响到其它层的规范,具有很强的灵活可变性。本文依据该层次结构,分别对每一层次所完成的操作进行了细致的分析。
2.根据对协议的研究分析结果,本文对串行RapidIO物理层进行了FPGA逻辑实现。串行RapidIO物理层,其不仅需要完成对包的物理层字段的封装,还要负责端口的初始化、包的发送和接收、流量控制、错误管理等操作。本文以上述操作为索引,对其实现过程进行了详细阐述。
3.完成了串行RapidIO物理层的设计和FPGA逻辑实现后,本文紧接着对逻辑实现的代码进行了RTL级仿真并给出了逻辑资源消耗情况。整个仿真过程分别对端口的初始化、包的发送和接收、流量控制、错误管理进行了验证,证明了其功能正确并符合RapidIO 1.3协议版本对串行物理层的描述,从而保证了本文的逻辑实现成果能顺利地与芯片厂商提供的IP核进行互联通信。
4.针对串行RapidIO的各种优点,本文将其应用到第三代和第四代无线通信技术中,完成了基于串行RapidIO的基带处理架构方案。最后通过搭建硬件测试平台,根据实际上板所得到的流量测试结果从灵活性、可靠性、可扩展性等方面验证了该架构方案的正确性和可行性。
The fast development of embedded processing technology is posed a serious challenge to high-performance embedded system high-speed interconnection. In order to cope with such challenges and meet the needs of embedded system development, the industry's leading semiconductor and system manufacturers work together to set up a high-speed Internet Protocol - RapidIO.This protocol can support arbitrary topology and point-to-point operation, provide effective congestion control, high transmission efficiency and reliability.
Because of the bottleneck on data transmission of embedded system and the superiority of RapidIO on interconnection, this dissertation does many works to analyse and research on the RapidIO. The main results are as follows:
1. First of all, this dissertation carries out study on the structure of Serial RapidIO protocol. Serial RapidIO protocol is divided into three layers: logical layer, transport layer, physical layer. Such a hierarchical structure characterized by a layer of affairs in any type of change will not affect other layers of the norms, is highly flexible and variable. Based on the hierarchical structure, this dissertation carries out detailed analysis on the operation of each layer.
2. Based on results of the RapidIO protocol analysis, this dissertation does logic implementation of the serial physical layer. Serial physical layer is not only required to complete the physical layer packet fields encapsulation but also is in charge of port initialization, sending and receiving packets and control symbols, flow control, error management, and other operations. This dissertation discusses the logic implementation process in detail based on the functions of the physical layer.
3. After the accomplishment of the serial RapidIO physical layer FPGA logic implementation, this dissertation does RTL simulation immediately for the implementation of the logic code and shows the logic resource consumption. Throughout the simulation of the initialization of the port, sending and receiving packets, flow control, and error management, it verifies that the functions are correct in accordance with the RapidIO 1.3 protocol version. Consequently, the FPGA logic implementation of this dissertation can successfully communicate with the chip vendor IP core.
4. For a variety of advantages, this dissertation applies Serial RapidIO into the fourth generation of wireless communications technology.this dissertation completes a Serial RapidIO-based architecture of the baseband process system. Finally this dissertation sets up a hardware test platform, according to the test results it verifyies correctness and feasibility of this architecture.
引文
[1] Sam Fuller.RapidIO The Embedded System Interconnect.北京:电子工业出版社.2006.
[2]张昆藏.计算机系统结构教程.北京:国防工业出版社.2001,10-36
[3]刘星.微机原理与接口技术.北京:电子工业出版社.2002,7-23
[4] Tom Shanley,Don Anderson.PCI system architecture(4th edition).北京:电子工业出版社.2000, 6-26
[5] Mindshare,Inc, Tom Shanley.PCI-X系统的体系结构.北京:清华大学出版社.2002,1-28
[6]郭淦.高速串行通信中的时钟恢复技术.博士学位论文.复旦大学.2005
[7] S.Mathew,M.Anders,R.Kriskiamurthy,S.Borkar.A 4-GHz 130-nmAddress Generation Unit with 32-bit Sparse-tree Adder Core.IEEE J.Solid State Circuits. 2003.Vol.38,NO.5,PP689-695.
[8]伊亚明.新型高性能RapidIO互联技术研究.计算机工程与科学.2004.26.(12):85-87
[9] G. F. Pfister.“An introduction to the InfiniBand architecture”in High Performance mass Storage and Parallel I/O: Technologies and Applications (H. Jin, T. Cortes, and R. Buyya, eds.). IEEE Computer Society Press and Wiley. 2001. ch. 42, pp. 617-632.
[10] PCI ExpressTM Base Specification Revision 1.1.PCI-SIG.2005
[11] David Bueno, Adam Leko, Chris Conger, Ian Troxel, and Alan D. George.Simulative Analysis of the RapidIO Embedded Interconnect Architecture for Real-Time,Network-Intensive Applications. IEEE Computer Society Press and Wiley. the 29th Annual IEEE International Conference.
[12] RapidIO Interconnect Specification Documentation Overview.RapidIO Trade Association. 2002.
[13] RapidIO Interconnect Specification Rev1.3 Part 1: Input/Output Logical Specification.RapidIO Trade Association.2005.
[14] RapidIO Interconnect Specification Rev1.3 Part 2: Message Passing Logical Specification.RapidIO Trade Association.2005.
[15] RapidIO Interconnect Specification Rev1.3 Part 3: Common Transport Specification.RapidIO Trade Association. 2005.
[16] RapidIO Interconnect Specification Rev1.3 Part 6: 1x/4x LP-Serial Physical Layer Specification.RapidIO Trade Association.2005.
[17] RapidIO Interconnect Specification Rev1.3 Part 7: System and Device Inter-operability Specification.RapidIO Trade Association.2005.
[18] RapidIO Interconnect Specification Rev1.3 Part 8: Error Management Extensions Specification,RapidIO Trade Association.2005.
[19] Xiongkui Zhang, Meiguo Gao, Guoman Liu, A Scalable Heterogeneous Multi-Processor Signal Processing System Based on the RapidIO Interconnect.IEEE Computer Society.2008.61.pp.761-764.
[20] Xiaojun Yang, Tao Liu, Fei Chen, Hailiang Cheng, MemoryIO: an Extended I/O Technology in Embedded Systems.IEEE Computer Society.2008. 23.pp.319-322.
[21] Martin MCKWZ, Transporting multiple classes of traffic over a generic routing device– An investigation into the performance of the RapidIO interconnect architecture. IEEE.2003. 3.pp.39-44
[22]孙永明.千兆高速串行接口集成电路系统设计机器关键技术的研究.博士学位论文.东南大学.2005.
[23]李宥谋.8B/10B编码器的设计实现.电视技术.2005.6:26-33
[24]马鸿开.10GB/s高速SERDES电路的MUX/DEMUX设计.微电子学与计算机. 2007.24(12): 174-176
[25]陈炳军.PCI Express数据链路层的设计.硕士学位论文.浙江大学.2006.
[26]马克杰. PCI Express交换器IP核的设计与研究.硕士学位论文.山东大学.2007.
[27]廖海红.通信系统中的CRC算法的研究和工程实现.硕士学位论文.北京邮电大学.2006.
[28]潘国振.系统传输标准协议的研究与电路设计.硕士学位论文.浙江大学.2004.
[29]崔维嘉.新一代的总线结构-RapidIO.通信技术.2001.4.31(1):37-38
[30]杜旭.基于FPGA的高速串行传输接口的设计与实现.计算机工程与应用.2007.43(12):94-96
[31]刘洁.基于FPGA的RapidIO核接口芯片的设计和实现.微型计算机.2004.25(2):203-207
[32]林琌.RapidIO在多处理器系统互联中的应用.计算机工程.2006.32(4):244-246
[33]刘祥远.LVDS高速I/O接口单元的设计研究.计算机工程与科学.2001.23(4):52-56
[34]邓豹.基于串行RapidIO的嵌入式互联研究.航空计算技术.2008.38(3):123-126
[35] Dan Bouvier.An embedded system component network architecture. RapidIO technical working group.2001.
[36]鲁胜兵.B3G系统中高速串行接口的研究与实现.硕士学位论文.华中科技大学.2005.
[2]张昆藏.计算机系统结构教程.北京:国防工业出版社.2001,10-36
[3]刘星.微机原理与接口技术.北京:电子工业出版社.2002,7-23
[4] Tom Shanley,Don Anderson.PCI system architecture(4th edition).北京:电子工业出版社.2000, 6-26
[5] Mindshare,Inc, Tom Shanley.PCI-X系统的体系结构.北京:清华大学出版社.2002,1-28
[6]郭淦.高速串行通信中的时钟恢复技术.博士学位论文.复旦大学.2005
[7] S.Mathew,M.Anders,R.Kriskiamurthy,S.Borkar.A 4-GHz 130-nmAddress Generation Unit with 32-bit Sparse-tree Adder Core.IEEE J.Solid State Circuits. 2003.Vol.38,NO.5,PP689-695.
[8]伊亚明.新型高性能RapidIO互联技术研究.计算机工程与科学.2004.26.(12):85-87
[9] G. F. Pfister.“An introduction to the InfiniBand architecture”in High Performance mass Storage and Parallel I/O: Technologies and Applications (H. Jin, T. Cortes, and R. Buyya, eds.). IEEE Computer Society Press and Wiley. 2001. ch. 42, pp. 617-632.
[10] PCI ExpressTM Base Specification Revision 1.1.PCI-SIG.2005
[11] David Bueno, Adam Leko, Chris Conger, Ian Troxel, and Alan D. George.Simulative Analysis of the RapidIO Embedded Interconnect Architecture for Real-Time,Network-Intensive Applications. IEEE Computer Society Press and Wiley. the 29th Annual IEEE International Conference.
[12] RapidIO Interconnect Specification Documentation Overview.RapidIO Trade Association. 2002.
[13] RapidIO Interconnect Specification Rev1.3 Part 1: Input/Output Logical Specification.RapidIO Trade Association.2005.
[14] RapidIO Interconnect Specification Rev1.3 Part 2: Message Passing Logical Specification.RapidIO Trade Association.2005.
[15] RapidIO Interconnect Specification Rev1.3 Part 3: Common Transport Specification.RapidIO Trade Association. 2005.
[16] RapidIO Interconnect Specification Rev1.3 Part 6: 1x/4x LP-Serial Physical Layer Specification.RapidIO Trade Association.2005.
[17] RapidIO Interconnect Specification Rev1.3 Part 7: System and Device Inter-operability Specification.RapidIO Trade Association.2005.
[18] RapidIO Interconnect Specification Rev1.3 Part 8: Error Management Extensions Specification,RapidIO Trade Association.2005.
[19] Xiongkui Zhang, Meiguo Gao, Guoman Liu, A Scalable Heterogeneous Multi-Processor Signal Processing System Based on the RapidIO Interconnect.IEEE Computer Society.2008.61.pp.761-764.
[20] Xiaojun Yang, Tao Liu, Fei Chen, Hailiang Cheng, MemoryIO: an Extended I/O Technology in Embedded Systems.IEEE Computer Society.2008. 23.pp.319-322.
[21] Martin MCKWZ, Transporting multiple classes of traffic over a generic routing device– An investigation into the performance of the RapidIO interconnect architecture. IEEE.2003. 3.pp.39-44
[22]孙永明.千兆高速串行接口集成电路系统设计机器关键技术的研究.博士学位论文.东南大学.2005.
[23]李宥谋.8B/10B编码器的设计实现.电视技术.2005.6:26-33
[24]马鸿开.10GB/s高速SERDES电路的MUX/DEMUX设计.微电子学与计算机. 2007.24(12): 174-176
[25]陈炳军.PCI Express数据链路层的设计.硕士学位论文.浙江大学.2006.
[26]马克杰. PCI Express交换器IP核的设计与研究.硕士学位论文.山东大学.2007.
[27]廖海红.通信系统中的CRC算法的研究和工程实现.硕士学位论文.北京邮电大学.2006.
[28]潘国振.系统传输标准协议的研究与电路设计.硕士学位论文.浙江大学.2004.
[29]崔维嘉.新一代的总线结构-RapidIO.通信技术.2001.4.31(1):37-38
[30]杜旭.基于FPGA的高速串行传输接口的设计与实现.计算机工程与应用.2007.43(12):94-96
[31]刘洁.基于FPGA的RapidIO核接口芯片的设计和实现.微型计算机.2004.25(2):203-207
[32]林琌.RapidIO在多处理器系统互联中的应用.计算机工程.2006.32(4):244-246
[33]刘祥远.LVDS高速I/O接口单元的设计研究.计算机工程与科学.2001.23(4):52-56
[34]邓豹.基于串行RapidIO的嵌入式互联研究.航空计算技术.2008.38(3):123-126
[35] Dan Bouvier.An embedded system component network architecture. RapidIO technical working group.2001.
[36]鲁胜兵.B3G系统中高速串行接口的研究与实现.硕士学位论文.华中科技大学.2005.