基于RapidIO系统互连协议的逻辑设计与验证
|
摘要
随着通信和网络技术的飞速发展,各种嵌入式系统都对设备内部的数据传输速率提出了更高的要求。传统的分级共享总线结构已达到了极限性能,互连技术问题已经成为制约嵌入式系统整体性能提高的瓶颈。面对这些挑战,一些基于点对点交换式高性能总线互连结构应运而生,而RapidIO系统互连技术正是其中的佼佼者,它最适合用于高性能嵌入式系统内部互连。
RapidIO属于系统内部互连技术,是一种新型高性能、低引脚数、结构灵活、基于报文交换的点对点互连体系结构,广泛应用在连接多处理器、存储器阵列、DSP阵列、网络设备中的存储器映射I／O器件、以及通用计算平台。而4x模式的串行RapidIO,简称SRIO (Serial RapidIO),是本论文的研究重点。SRIO1.3协议的物理层支持1.25GHz、2.5GHz、3.125GHz三种信号速率,持续的全双工数据带宽范围最高可达到4Gbps到18 Gbps。
本文在深入研究了串行RapidIO1.3互连协议三层体系结构中逻辑层和传输层的基础上,对这两层的功能做了一些改进。并且着重对逻辑层和传输层进行了FPGA (Field Programmable Gate Array)逻辑设计,包括实现多种事务请求包和响应包的封装和解析、各层之间的接口时序转换、多通道轮询调度,以及各层内部寄存器维护等功能。然后搭建了TCL自动化功能仿真平台和上板FPGA验证平台,对逻辑实现的Verilog代码进行RTL级仿真和上板验证。最后根据功能仿真时序波形图和实际上板所测结果分析,该逻辑层和传输层的逻辑设计在灵活性、可靠性、可扩展性方面都有非常良好的表现,完全可以封装为成熟的RapidIO软核嵌入到各种通信和网络系统之中。
Due to the rapid development of the communications and network technology, various Embedded systems have higher requirement for transfer rate of data in device. Traditional hierarchical shared bus architecture has already come to its extreme performance, and the technical aspects of interconnection has become a serious problem limiting the improvement of Embedded performance. Facing these challenges, some high performance interconnect bus structures, based on point to point and exchange function, come into being. And RapidIO system interconnect technology is the top one.
RapidIO is a technology within the system interconnect. It is point to point interconnect architecture with New high-performance, Low Pin Count, Structural flexibility and based on packet switching, and is widely used to connect multi-processor, Memory Array, DSP Array, Network devices in the memory-mapped I/O devices and Universal Computing Platform. Then 4x mode SRIO(Serial RapidIO) which supports three Baud including 1.25GHz、2.5GHz、3.125GHz and persistent Full-duplex data bandwidth from 4Gbps to18 Gbps, is important point of this papers.
This paper has simplified the function of Logic and Transport Layer, based on in-depth study for Serial RapidIO interconnect protocol three-tier architecture such as Logic Layer, Transport Layer. The key research is FPGA(Field Programmable Gate Array) logic design for Logic and Transport Layer including the functions such as accomplishing encapsulation and analysis for a variety of services request packets and response packets, interface sequence change of each layer, the fair polling for multiply channels and maintenance of each layer's registers. Verilog program of the design has been offered to RTL simulation and verification by building TCL platform of automated functional simulation and verification environment based on FPGA. Finally, analyzing from timing simulation waveform and measured results from verification environment, logic design of this logic and transport layers all have good performance on flexibility, reliability and expansibility, and can be packed to be a mature RapidIO soft core to be embedded into every communication and network system.
RapidIO属于系统内部互连技术,是一种新型高性能、低引脚数、结构灵活、基于报文交换的点对点互连体系结构,广泛应用在连接多处理器、存储器阵列、DSP阵列、网络设备中的存储器映射I／O器件、以及通用计算平台。而4x模式的串行RapidIO,简称SRIO (Serial RapidIO),是本论文的研究重点。SRIO1.3协议的物理层支持1.25GHz、2.5GHz、3.125GHz三种信号速率,持续的全双工数据带宽范围最高可达到4Gbps到18 Gbps。
本文在深入研究了串行RapidIO1.3互连协议三层体系结构中逻辑层和传输层的基础上,对这两层的功能做了一些改进。并且着重对逻辑层和传输层进行了FPGA (Field Programmable Gate Array)逻辑设计,包括实现多种事务请求包和响应包的封装和解析、各层之间的接口时序转换、多通道轮询调度,以及各层内部寄存器维护等功能。然后搭建了TCL自动化功能仿真平台和上板FPGA验证平台,对逻辑实现的Verilog代码进行RTL级仿真和上板验证。最后根据功能仿真时序波形图和实际上板所测结果分析,该逻辑层和传输层的逻辑设计在灵活性、可靠性、可扩展性方面都有非常良好的表现,完全可以封装为成熟的RapidIO软核嵌入到各种通信和网络系统之中。
Due to the rapid development of the communications and network technology, various Embedded systems have higher requirement for transfer rate of data in device. Traditional hierarchical shared bus architecture has already come to its extreme performance, and the technical aspects of interconnection has become a serious problem limiting the improvement of Embedded performance. Facing these challenges, some high performance interconnect bus structures, based on point to point and exchange function, come into being. And RapidIO system interconnect technology is the top one.
RapidIO is a technology within the system interconnect. It is point to point interconnect architecture with New high-performance, Low Pin Count, Structural flexibility and based on packet switching, and is widely used to connect multi-processor, Memory Array, DSP Array, Network devices in the memory-mapped I/O devices and Universal Computing Platform. Then 4x mode SRIO(Serial RapidIO) which supports three Baud including 1.25GHz、2.5GHz、3.125GHz and persistent Full-duplex data bandwidth from 4Gbps to18 Gbps, is important point of this papers.
This paper has simplified the function of Logic and Transport Layer, based on in-depth study for Serial RapidIO interconnect protocol three-tier architecture such as Logic Layer, Transport Layer. The key research is FPGA(Field Programmable Gate Array) logic design for Logic and Transport Layer including the functions such as accomplishing encapsulation and analysis for a variety of services request packets and response packets, interface sequence change of each layer, the fair polling for multiply channels and maintenance of each layer's registers. Verilog program of the design has been offered to RTL simulation and verification by building TCL platform of automated functional simulation and verification environment based on FPGA. Finally, analyzing from timing simulation waveform and measured results from verification environment, logic design of this logic and transport layers all have good performance on flexibility, reliability and expansibility, and can be packed to be a mature RapidIO soft core to be embedded into every communication and network system.
引文
[1]Sam Fuller.RapidIO The Embedded System Interconnect London:John Wiley & Sons,Inc,2005.
[2]RapidIO Trade Association. RapidIO Interconnect Specification Rev1.32005
[3]Altera Corporation.RapidIO MegaCore Fuction (V8.1) [Z].2008.
[4]Xilinx Corporation. IP CORE RapidIO Getting Start Guide. http://www.xilinx.com/rapidio, February 2007.
[5]Xilinx.LogiCORE RapidIO Logical I/O and Transport Layer v4.1User Guide, http://www.xilinx.com/rapidio, February 2007.
[6]RapidIO Trade Association, RapidIO Interconnect SpecificationsV1.3 Part 1: Input/Output Logical Specification, http://www.rapidio.org, June 2005
[7]TMS320C645x Serial RapidIO User's Guide [M].Texas In-struments Corporation,2006.
[8]Stratix II GX Device Handbook[M].Altera Corporation,2005.
[9]RapidIO Trade Association. RapidIO Technology Overview and applications [EB].http://www.rapidio.org/.2005.
[10]Dan Bouvier.An embedded system component network architecture. RapidIO technical working group.2001.
[1I]Motorola Semiconductor Product Sector,"RapidIO:An Embedded System Component Network Architecture,"RapidIO Whitepaper,February 2000.
[12]王勇,林粤伟,吴冰冰.RapidIO嵌入式系统互连[M].北京：电子工业出版社,2006.
[13]杨卿.RapidIO高速互联接口的设计研究与应用[D].硕士学位论文.电子科技大学.2009.
[14]杨涛RapidIO互联技术在下一代无线基站中的应用[D].硕士学位论文.西安电子科技大学.2008
[15]潘灵.基于RapidIO总线的进程间通信系统的研究与实现[D].硕士学位论文.电子科技大学.2009.
[16]尹亚明,李琼等,新型高性能RapidIO互联技术研究,计算机工程与科,2004.3
[17]李琼,郭御风等.I／O互联技术及体系结构的研究与发展[J].网络与通信. 2006.32
[18]夏宇闻.Verilog数字系统设计教程,北京航空航天大学出版社,2003.7
[19]邓豹,赵小冬.基于串行RapidIO的嵌入式互连研究[J].航空计算技术,2008,(03)
[20]谢智勇,罗明,蒋俊.串行RapidIO验证模型[J].计算机工程,2008,(S1).
[21]王帆,刘云.串行RapidIO在多DSP系统中的应用初探[J].计算机与数字工程,2008,(08).
[22]刘旭,吴云峰.基于SRIO的双DSP并行图像处理系统[J].中国科技信息,2009,(11).
[23]马春江,牛文生,孙靖国.几种串行总线互连技术分析[J]航空计算技术,2007,(05)
[24]林玲,蒋俊,倪明,柴小丽.]RapidIO在多处理器系统互连中的应用[J]计算机工程,2006,(04)
[25]黄亮,刘福岩.基于RapidIO和存储映射的高速互连网络[J].计算机工程,2008,(14)
[26]李琼,郭御风,刘光明,刘涛.I/O互联技术及体系结构的研究与发展[J].计算机工程,2006,(12).
[27]冯华亮.串行RapidIO高性能嵌入式互连技术[J]今日电子,2007,(09)
[28]王诚,吴继华,范丽珍.Altera FPGA/CPLD设计(基础篇).人民邮电出版社,2005：117-139,187-213,237-317
[29]王诚,吴继华,范丽珍.Altera FPGA/CPLD设计(高级篇).人民邮电出版社,2005：1-117
[30]J Bhasker. Verilog HDL硬件描述语言.机械工业出版社.2000：1-38
[31]Xilinx Inc, Virtex-4 User guide. www.Xilinx.com.2007
[32]Altera Inc, Stratix II Device Handbook. www.Altera.com.2008
[33]RapidIO Trade Association. RapidIO Interconnect Specifications V1.3 Part 6: 1x/4x LP-Serial Physical Layer Specification.http://www.rapidio.org.
[34]RapidIO Trade Association. RapidIO Interconnect Specifications V1.3 Part 3: Common Transport Specification.http://www.rapidio.org.
[35]RapidIO Trade Association. RapidIO Interconnect Specifications Part 7: System and Device Inter-operability Specification, Rev.1.3.2005-06
[36]RapidIO Trade Association. RapidIO? Interconnect Specification Part 9: Flow Control Logical Layer Extensions Specification, Rev.1.3.2005-06
[37]RapidIO Trade Association. RapidIO? Interconnect Specification Part 2: Message Passing Logical Specification, Rev.1.3.2005-06
[38]Tundra Semiconductor Corporation. Tsi578 Serial RapidIO Switch User Manual.2007.05
[39]Cohen Strod. RapidIO fabric unifies VITA and PICMG platform architectures.Mercury Computer Systems, Inc, Feb 2006
[40]Nicholas Cravotta. RapidIO versus HyperTransport:A battle between equals or unintentional.EDN,2002.06
[41]David Bueno,Adam Leko. Simulative Analysis of the RapidIO Embedded Interconnect Architecture for Real-Time Network-Intensive Application IEEE computer Society,2004.03
[42]金亨科,雷咏梅,梁基.基于RapidIO的MPI设备层的设计与实现[J].计算机工程与设计,2008,(21)
[43]Tom Cox.以太网与RapidIO的对比[J].电子设计应用,2007,(06)
[44]聂俊英.RapidIO技术在无线基站中的应用[D].西安电子科技大学,2008
[45]牛彦茹.基于RAPIDIO架构基站系统的设计仿真分析[D].西安电子科技大学.2008
[46]王诚,薛小刚,钟信潮,FPGA/CPLD设计工具—Xilinx ISE5.X使用详解,北京：人民邮电出版社,2003.
[47]刘洁.基于FPGA的RapidIO核接口芯片的设计和实现.微型计算机.2004.25(2)：203-207
[48]杜旭.基于FPGA的高速串行传输接口的设计与实现.计算机工程与应用.2007.43(12)：94-96
[49]刘祥远..LVDS高速I／O接口单元的设计研究.计算机工程与科学.2001.23(4)：52-56
[50]陈炳军.PCI Express数据链路层的设计.硕士学位论文.浙江大学.2006.
[51]潘国振.系统传输标准协议的研究与电路设计.硕士学位论文.浙江大学.2004.
[52]马克杰.PCI Express交换器IP核的设计与研究.硕士学位论文.山东大学.2007.
[2]RapidIO Trade Association. RapidIO Interconnect Specification Rev1.32005
[3]Altera Corporation.RapidIO MegaCore Fuction (V8.1) [Z].2008.
[4]Xilinx Corporation. IP CORE RapidIO Getting Start Guide. http://www.xilinx.com/rapidio, February 2007.
[5]Xilinx.LogiCORE RapidIO Logical I/O and Transport Layer v4.1User Guide, http://www.xilinx.com/rapidio, February 2007.
[6]RapidIO Trade Association, RapidIO Interconnect SpecificationsV1.3 Part 1: Input/Output Logical Specification, http://www.rapidio.org, June 2005
[7]TMS320C645x Serial RapidIO User's Guide [M].Texas In-struments Corporation,2006.
[8]Stratix II GX Device Handbook[M].Altera Corporation,2005.
[9]RapidIO Trade Association. RapidIO Technology Overview and applications [EB].http://www.rapidio.org/.2005.
[10]Dan Bouvier.An embedded system component network architecture. RapidIO technical working group.2001.
[1I]Motorola Semiconductor Product Sector,"RapidIO:An Embedded System Component Network Architecture,"RapidIO Whitepaper,February 2000.
[12]王勇,林粤伟,吴冰冰.RapidIO嵌入式系统互连[M].北京：电子工业出版社,2006.
[13]杨卿.RapidIO高速互联接口的设计研究与应用[D].硕士学位论文.电子科技大学.2009.
[14]杨涛RapidIO互联技术在下一代无线基站中的应用[D].硕士学位论文.西安电子科技大学.2008
[15]潘灵.基于RapidIO总线的进程间通信系统的研究与实现[D].硕士学位论文.电子科技大学.2009.
[16]尹亚明,李琼等,新型高性能RapidIO互联技术研究,计算机工程与科,2004.3
[17]李琼,郭御风等.I／O互联技术及体系结构的研究与发展[J].网络与通信. 2006.32
[18]夏宇闻.Verilog数字系统设计教程,北京航空航天大学出版社,2003.7
[19]邓豹,赵小冬.基于串行RapidIO的嵌入式互连研究[J].航空计算技术,2008,(03)
[20]谢智勇,罗明,蒋俊.串行RapidIO验证模型[J].计算机工程,2008,(S1).
[21]王帆,刘云.串行RapidIO在多DSP系统中的应用初探[J].计算机与数字工程,2008,(08).
[22]刘旭,吴云峰.基于SRIO的双DSP并行图像处理系统[J].中国科技信息,2009,(11).
[23]马春江,牛文生,孙靖国.几种串行总线互连技术分析[J]航空计算技术,2007,(05)
[24]林玲,蒋俊,倪明,柴小丽.]RapidIO在多处理器系统互连中的应用[J]计算机工程,2006,(04)
[25]黄亮,刘福岩.基于RapidIO和存储映射的高速互连网络[J].计算机工程,2008,(14)
[26]李琼,郭御风,刘光明,刘涛.I/O互联技术及体系结构的研究与发展[J].计算机工程,2006,(12).
[27]冯华亮.串行RapidIO高性能嵌入式互连技术[J]今日电子,2007,(09)
[28]王诚,吴继华,范丽珍.Altera FPGA/CPLD设计(基础篇).人民邮电出版社,2005：117-139,187-213,237-317
[29]王诚,吴继华,范丽珍.Altera FPGA/CPLD设计(高级篇).人民邮电出版社,2005：1-117
[30]J Bhasker. Verilog HDL硬件描述语言.机械工业出版社.2000：1-38
[31]Xilinx Inc, Virtex-4 User guide. www.Xilinx.com.2007
[32]Altera Inc, Stratix II Device Handbook. www.Altera.com.2008
[33]RapidIO Trade Association. RapidIO Interconnect Specifications V1.3 Part 6: 1x/4x LP-Serial Physical Layer Specification.http://www.rapidio.org.
[34]RapidIO Trade Association. RapidIO Interconnect Specifications V1.3 Part 3: Common Transport Specification.http://www.rapidio.org.
[35]RapidIO Trade Association. RapidIO Interconnect Specifications Part 7: System and Device Inter-operability Specification, Rev.1.3.2005-06
[36]RapidIO Trade Association. RapidIO? Interconnect Specification Part 9: Flow Control Logical Layer Extensions Specification, Rev.1.3.2005-06
[37]RapidIO Trade Association. RapidIO? Interconnect Specification Part 2: Message Passing Logical Specification, Rev.1.3.2005-06
[38]Tundra Semiconductor Corporation. Tsi578 Serial RapidIO Switch User Manual.2007.05
[39]Cohen Strod. RapidIO fabric unifies VITA and PICMG platform architectures.Mercury Computer Systems, Inc, Feb 2006
[40]Nicholas Cravotta. RapidIO versus HyperTransport:A battle between equals or unintentional.EDN,2002.06
[41]David Bueno,Adam Leko. Simulative Analysis of the RapidIO Embedded Interconnect Architecture for Real-Time Network-Intensive Application IEEE computer Society,2004.03
[42]金亨科,雷咏梅,梁基.基于RapidIO的MPI设备层的设计与实现[J].计算机工程与设计,2008,(21)
[43]Tom Cox.以太网与RapidIO的对比[J].电子设计应用,2007,(06)
[44]聂俊英.RapidIO技术在无线基站中的应用[D].西安电子科技大学,2008
[45]牛彦茹.基于RAPIDIO架构基站系统的设计仿真分析[D].西安电子科技大学.2008
[46]王诚,薛小刚,钟信潮,FPGA/CPLD设计工具—Xilinx ISE5.X使用详解,北京：人民邮电出版社,2003.
[47]刘洁.基于FPGA的RapidIO核接口芯片的设计和实现.微型计算机.2004.25(2)：203-207
[48]杜旭.基于FPGA的高速串行传输接口的设计与实现.计算机工程与应用.2007.43(12)：94-96
[49]刘祥远..LVDS高速I／O接口单元的设计研究.计算机工程与科学.2001.23(4)：52-56
[50]陈炳军.PCI Express数据链路层的设计.硕士学位论文.浙江大学.2006.
[51]潘国振.系统传输标准协议的研究与电路设计.硕士学位论文.浙江大学.2004.
[52]马克杰.PCI Express交换器IP核的设计与研究.硕士学位论文.山东大学.2007.